include/configs/PCIPPC2.h

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the PCIPPC-2 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_PCIPPC2          1       /* this is a PCIPPC2 board      */
  45
  46 #define CONFIG_BOARD_PRE_INIT   1
  47 #define CONFIG_MISC_INIT_R      1
  48
  49 #define CONFIG_CONS_INDEX       1
  50 #define CONFIG_BAUDRATE         9600
  51 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  52
  53 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passed to Linux in MHz */
  54
  55 #define CONFIG_PREBOOT          ""
  56 #define CONFIG_BOOTDELAY        5
  57
  58 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
  59                                  CONFIG_BOOTP_BOOTFILESIZE)
  60
  61 #define CONFIG_MAC_PARTITION
  62 #define CONFIG_DOS_PARTITION
  63
  64 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
  65                                  CFG_CMD_ASKENV | \
  66                                  CFG_CMD_BSP    | \
  67                                  CFG_CMD_DATE   | \
  68                                  CFG_CMD_DHCP   | \
  69                                  CFG_CMD_DOC    | \
  70                                  CFG_CMD_ELF    | \
  71                                  CFG_CMD_PCI    )
  72
  73 #define CONFIG_PCI              1
  74 #define CONFIG_PCI_PNP          1       /* PCI plug-and-play */
  75
  76 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  77  */
  78 #include <cmd_confdefs.h>
  79
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84 #define CFG_LONGHELP                    /* undef to save memory         */
  85 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  86
  87 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
  88 #ifdef  CFG_HUSH_PARSER
  89 #define CFG_PROMPT_HUSH_PS2     "> "
  90 #endif
  91 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  92
  93 /* Print Buffer Size
  94  */
  95 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  96
  97 #define CFG_MAXARGS     64              /* max number of command args   */
  98 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  99 #define CFG_LOAD_ADDR   0x00100000      /* Default load address         */
 100
 101 /*-----------------------------------------------------------------------
 102  * Start addresses for the final memory configuration
 103  * (Set up by the startup code)
 104  * Please note that CFG_SDRAM_BASE _must_ start at 0
 105  */
 106 #define CFG_SDRAM_BASE      0x00000000
 107 #define CFG_FLASH_BASE      0xFFF00000
 108 #define CFG_FLASH_MAX_SIZE  0x00100000
 109 /* Maximum amount of RAM.
 110  */
 111 #define CFG_MAX_RAM_SIZE    0x20000000  /* 512Mb                        */
 112
 113 #define CFG_RESET_ADDRESS   0xFFF00100
 114
 115 #define CFG_MONITOR_BASE    TEXT_BASE
 116
 117 #define CFG_MONITOR_LEN     (256 << 10) /* Reserve 256 kB for Monitor   */
 118 #define CFG_MALLOC_LEN      (128 << 10) /* Reserve 128 kB for malloc()  */
 119
 120 #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
 121     CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
 122 #define CFG_RAMBOOT
 123 #else
 124 #undef CFG_RAMBOOT
 125 #endif
 126
 127 #define CFG_MEMTEST_START   0x00004000  /* memtest works on             */
 128 #define CFG_MEMTEST_END     0x02000000  /* 0 ... 32 MB in DRAM          */
 129
 130 /*-----------------------------------------------------------------------
 131  * Definitions for initial stack pointer and data area
 132  */
 133
 134 /* Size in bytes reserved for initial data
 135  */
 136 #define CFG_GBL_DATA_SIZE    128
 137
 138 #define CFG_INIT_RAM_ADDR     0x40000000
 139 #define CFG_INIT_RAM_END      0x8000
 140 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 141 #define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
 142
 143 #define CFG_INIT_RAM_LOCK
 144
 145 /*
 146  * Temporary buffer for serial data until the real serial driver
 147  * is initialised (memtest will destroy this buffer)
 148  */
 149 #define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
 150 #define CFG_SCONSOLE_SIZE     0x0002000
 151
 152 /* SDRAM 0 - 256MB
 153  */
 154 #define CFG_DBAT0L            (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 155 #define CFG_DBAT0U            (CFG_SDRAM_BASE | \
 156                                BATU_BL_256M | BATU_VS | BATU_VP)
 157 /* SDRAM 1 - 256MB
 158  */
 159 #define CFG_DBAT1L            ((CFG_SDRAM_BASE + 0x10000000) | \
 160                                BATL_PP_10 | BATL_MEMCOHERENCE)
 161 #define CFG_DBAT1U            ((CFG_SDRAM_BASE + 0x10000000) | \
 162                                BATU_BL_256M | BATU_VS | BATU_VP)
 163
 164 /* Init RAM in the CPU DCache (no backing memory)
 165  */
 166 #define CFG_DBAT2L            (CFG_INIT_RAM_ADDR | \
 167                                BATL_PP_10 | BATL_MEMCOHERENCE)
 168 #define CFG_DBAT2U            (CFG_INIT_RAM_ADDR | \
 169                                BATU_BL_128K | BATU_VS | BATU_VP)
 170
 171 /* I/O and PCI memory at 0xf0000000
 172  */
 173 #define CFG_DBAT3L            (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 174 #define CFG_DBAT3U            (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 175
 176 #define CFG_IBAT0L            CFG_DBAT0L
 177 #define CFG_IBAT0U            CFG_DBAT0U
 178 #define CFG_IBAT1L            CFG_DBAT1L
 179 #define CFG_IBAT1U            CFG_DBAT1U
 180 #define CFG_IBAT2L            CFG_DBAT2L
 181 #define CFG_IBAT2U            CFG_DBAT2U
 182 #define CFG_IBAT3L            CFG_DBAT3L
 183 #define CFG_IBAT3U            CFG_DBAT3U
 184
 185 /*
 186  * Low Level Configuration Settings
 187  * (address mappings, register initial values, etc.)
 188  * You should know what you are doing if you make changes here.
 189  * For the detail description refer to the PCIPPC2 user's manual.
 190  */
 191 #define CFG_HZ                1000
 192 #define CFG_BUS_HZ            100000000 /* bus speed - 100 mhz          */
 193 #define CFG_CPU_CLK           300000000
 194 #define CFG_BUS_CLK           100000000
 195
 196 /*
 197  * For booting Linux, the board info and command line data
 198  * have to be in the first 8 MB of memory, since this is
 199  * the maximum mapped by the Linux kernel during initialization.
 200  */
 201 #define CFG_BOOTMAPSZ         (8 << 20) /* Initial Memory map for Linux */
 202
 203 /*-----------------------------------------------------------------------
 204  * FLASH organization
 205  */
 206 #define CFG_MAX_FLASH_BANKS     1       /* Max number of flash banks            */
 207 #define CFG_MAX_FLASH_SECT      16      /* Max number of sectors in one bank    */
 208
 209 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 210 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 211
 212 /*
 213  * Note: environment is not EMBEDDED in the U-Boot code.
 214  * It's stored in flash separately.
 215  */
 216 #define CFG_ENV_IS_IN_FLASH     1
 217 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x70000)
 218 #define CFG_ENV_SIZE            0x1000  /* Size of the Environment              */
 219 #define CFG_ENV_SECT_SIZE       0x10000 /* Size of the Environment Sector       */
 220
 221 /*-----------------------------------------------------------------------
 222  * Cache Configuration
 223  */
 224 #define CFG_CACHELINE_SIZE      32
 225 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 226 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 227 #endif
 228
 229 /*
 230  * L2 cache
 231  */
 232 #undef CFG_L2
 233 #define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 234                    L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 235 #define L2_ENABLE (L2_INIT | L2CR_L2E)
 236
 237 /*
 238  * Internal Definitions
 239  *
 240  * Boot Flags
 241  */
 242 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 243 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 244
 245 /*-----------------------------------------------------------------------
 246  * Disk-On-Chip configuration
 247  */
 248
 249 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 250
 251 #define CFG_DOC_SUPPORT_2000
 252 #undef CFG_DOC_SUPPORT_MILLENNIUM
 253
 254 /*-----------------------------------------------------------------------
 255   RTC m48t59
 256 */
 257 #define CONFIG_RTC_MK48T59
 258
 259 #define CONFIG_WATCHDOG
 260
 261 #define CONFIG_NET_MULTI                        /* Multi ethernet cards support */
 262
 263 #define CONFIG_EEPRO100
 264 #define CONFIG_TULIP
 265
 266 #endif  /* __CONFIG_H */