include/configs/PLU405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_PLU405           1       /* ...on a PLU405 board         */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  24 #define CONFIG_DISPLAY_BOARDINFO
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  28
  29 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  30
  31 #define CONFIG_BAUDRATE         9600
  32
  33 #undef  CONFIG_BOOTARGS
  34 #undef  CONFIG_BOOTCOMMAND
  35
  36 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  37
  38 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  39
  40 #undef  CONFIG_HAS_ETH1
  41
  42 #define CONFIG_PPC4xx_EMAC
  43 #define CONFIG_MII              1       /* MII PHY management           */
  44 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  45 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  46 #define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
  47
  48 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  49
  50 /*
  51  * BOOTP options
  52  */
  53 #define CONFIG_BOOTP_BOOTFILESIZE
  54 #define CONFIG_BOOTP_BOOTPATH
  55 #define CONFIG_BOOTP_GATEWAY
  56 #define CONFIG_BOOTP_HOSTNAME
  57
  58 /*
  59  * Command line configuration.
  60  */
  61 #define CONFIG_CMD_PCI
  62 #define CONFIG_CMD_IRQ
  63 #define CONFIG_CMD_IDE
  64 #define CONFIG_CMD_NAND
  65 #define CONFIG_CMD_DATE
  66 #define CONFIG_CMD_EEPROM
  67
  68 #define CONFIG_MAC_PARTITION
  69 #define CONFIG_DOS_PARTITION
  70
  71 #define CONFIG_SUPPORT_VFAT
  72
  73 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  74
  75 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  76 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
  77
  78 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  79
  80 /*
  81  * Miscellaneous configurable options
  82  */
  83 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  84
  85 #if defined(CONFIG_CMD_KGDB)
  86 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  87 #else
  88 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  89 #endif
  90 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  91 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  92 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  93
  94 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  95
  96 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  97
  98 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  99
 100 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 101 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 102
 103 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 104 #define CONFIG_SYS_NS16550_SERIAL
 105 #define CONFIG_SYS_NS16550_REG_SIZE     1
 106 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 107
 108 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 109 #define CONFIG_SYS_BASE_BAUD        691200
 110
 111 /* The following table includes the supported baudrates */
 112 #define CONFIG_SYS_BAUDRATE_TABLE       \
 113         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 114          57600, 115200, 230400, 460800, 921600 }
 115
 116 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 117 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 118
 119 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 120 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 121 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 122
 123 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 124
 125 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 126
 127 /*
 128  * NAND-FLASH stuff
 129  */
 130 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 131 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 132 #define NAND_BIG_DELAY_US       25
 133
 134 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 135 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 136 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 137 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 138
 139 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 140 #define CONFIG_SYS_NAND_QUIET          1
 141
 142 /*
 143  * PCI stuff
 144  */
 145 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 146 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 147 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 148
 149 #define CONFIG_PCI                      /* include pci support          */
 150 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 151 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 152 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 153                                         /* resource configuration       */
 154
 155 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 156
 157 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 158
 159 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 160 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 161 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 162 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 163 #define CONFIG_SYS_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
 164 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 165 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 166 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 167 #define CONFIG_SYS_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
 168
 169 /*
 170  * IDE/ATA stuff
 171  */
 172 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 173 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 174 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 175
 176 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 177 /* max. 1 drives per IDE bus */
 178 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1)
 179
 180 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 181 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 182
 183 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O */
 184 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register access */
 185 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers */
 186
 187 /*
 188  * For booting Linux, the board info and command line data
 189  * have to be in the first 8 MB of memory, since this is
 190  * the maximum mapped by the Linux kernel during initialization.
 191  */
 192 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 193
 194 /*
 195  * FLASH organization
 196  */
 197 #define FLASH_BASE0_PRELIM      0xFFC00000 /* FLASH bank #0 */
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 201
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 203 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms) */
 204
 205 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width) */
 206 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st addr for flash config cycles */
 207 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd addr for flash config cycles */
 208 /*
 209  * The following defines are added for buggy IOP480 byte interface.
 210  * All other boards should use the standard values (CPCI405 etc.)
 211  */
 212 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard */
 213 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard */
 214 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard */
 215
 216 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector */
 217
 218 /*
 219  * Start addresses for the final memory configuration
 220  * (Set up by the startup code)
 221  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 222  */
 223 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 224 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 225 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 226 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 227 #define CONFIG_SYS_MALLOC_LEN           (1024 << 10)
 228
 229 /*
 230  * Environment Variable setup
 231  */
 232 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 233 #define CONFIG_ENV_OFFSET               0x100   /* reseve 0x100 bytes for strapping */
 234 #define CONFIG_ENV_SIZE         0x700
 235
 236 /*
 237  * I2C EEPROM (24WC16) for environment
 238  */
 239 #define CONFIG_SYS_I2C
 240 #define CONFIG_SYS_I2C_PPC4XX
 241 #define CONFIG_SYS_I2C_PPC4XX_CH0
 242 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 243 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 244
 245 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM 24WC16 */
 246 #define CONFIG_SYS_EEPROM_WREN         1
 247
 248 /* 24WC16 */
 249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 250 /* mask of address bits that overflow into the "EEPROM chip address"    */
 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The 24WC16 has   */
 253                                         /* 16 byte page write mode using */
 254                                         /* last 4 bits of the address   */
 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 256
 257 /*
 258  * External Bus Controller (EBC) Setup
 259  */
 260 #define CAN0_BA         0xF0000000          /* CAN0 Base Address        */
 261 #define CAN1_BA         0xF0000100          /* CAN1 Base Address        */
 262 #define DUART0_BA       0xF0000400          /* DUART Base Address       */
 263 #define DUART1_BA       0xF0000408          /* DUART Base Address       */
 264 #define RTC_BA          0xF0000500          /* RTC Base Address         */
 265 #define VGA_BA          0xF1000000          /* Epson VGA Base Address   */
 266 #define CONFIG_SYS_NAND_BASE    0xF4000000          /* NAND FLASH Base Address  */
 267
 268 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
 269 /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 270 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 271 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 272 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000
 273
 274 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
 275 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 276 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
 277 #define CONFIG_SYS_EBC_PB1CR            0xF4018000
 278
 279 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
 280 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 281 #define CONFIG_SYS_EBC_PB2AP            0x010053C0
 282 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 283 #define CONFIG_SYS_EBC_PB2CR            0xF0018000
 284
 285 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
 286 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 287 #define CONFIG_SYS_EBC_PB3AP            0x010053C0
 288 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 289 #define CONFIG_SYS_EBC_PB3CR            0xF011A000
 290
 291 /*
 292  * FPGA stuff
 293  */
 294 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100        /* FPGA internal Base Address */
 295
 296 /* FPGA internal regs */
 297 #define CONFIG_SYS_FPGA_CTRL            0x000
 298
 299 /* FPGA Control Reg */
 300 #define CONFIG_SYS_FPGA_CTRL_CF_RESET   0x0001
 301 #define CONFIG_SYS_FPGA_CTRL_WDI        0x0002
 302 #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 303
 304 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now */
 305 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024    /* 128kByte is enough for XC2S50E*/
 306
 307 /* FPGA program pin configuration */
 308 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 309 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output) */
 310 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output) */
 311 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input) */
 312 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input) */
 313
 314 /*
 315  * Definitions for initial stack pointer and data area (in data cache)
 316  */
 317 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 318 #define CONFIG_SYS_TEMP_STACK_OCM         1
 319
 320 /* On Chip Memory location */
 321 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 322 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 323 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
 324 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM  */
 325
 326 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 327 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 328
 329 /*
 330  * Definitions for GPIO setup (PPC405EP specific)
 331  *
 332  * GPIO0[0]     - External Bus Controller BLAST output
 333  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 334  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 335  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 336  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 337  * GPIO0[24-27] - UART0 control signal inputs/outputs
 338  * GPIO0[28-29] - UART1 data signal input/output
 339  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 340  */
 341 #define CONFIG_SYS_GPIO0_OSRL           0x00000550
 342 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 343 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 344 #define CONFIG_SYS_GPIO0_ISR1H          0x15555445
 345 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 346 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 347 #define CONFIG_SYS_GPIO0_TCR            0x77FE0014
 348
 349 #define CONFIG_SYS_DUART_RST            (0x80000000 >> 14)
 350 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 0)
 351
 352 /*
 353  * Default speed selection (cpu_plb_opb_ebc) in MHz.
 354  * This value will be set if iic boot eprom is disabled.
 355  */
 356 #if 1
 357 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 358 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 359 #endif
 360 #if 0
 361 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 362 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 363 #endif
 364 #if 0
 365 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 366 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 367 #endif
 368
 369 /*
 370  * PCI OHCI controller
 371  */
 372 #define CONFIG_USB_OHCI_NEW     1
 373 #define CONFIG_PCI_OHCI         1
 374 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 375 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 376 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 377 #define CONFIG_USB_STORAGE      1
 378
 379 /*
 380  * UBI
 381  */
 382 #define CONFIG_CMD_UBI
 383 #define CONFIG_RBTREE
 384 #define CONFIG_MTD_DEVICE
 385 #define CONFIG_MTD_PARTITIONS
 386 #define CONFIG_CMD_MTDPARTS
 387 #define CONFIG_LZO
 388
 389 #endif  /* __CONFIG_H */