include/configs/PLU405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_PLU405           1       /* ...on a PLU405 board         */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  28
  29 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  30
  31 #define CONFIG_BAUDRATE         9600
  32
  33 #undef  CONFIG_BOOTARGS
  34 #undef  CONFIG_BOOTCOMMAND
  35
  36 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  37
  38 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  39
  40 #undef  CONFIG_HAS_ETH1
  41
  42 #define CONFIG_PPC4xx_EMAC
  43 #define CONFIG_MII              1       /* MII PHY management           */
  44 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  45 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  46 #define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
  47
  48 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  49
  50
  51 /*
  52  * BOOTP options
  53  */
  54 #define CONFIG_BOOTP_BOOTFILESIZE
  55 #define CONFIG_BOOTP_BOOTPATH
  56 #define CONFIG_BOOTP_GATEWAY
  57 #define CONFIG_BOOTP_HOSTNAME
  58
  59
  60 /*
  61  * Command line configuration.
  62  */
  63 #include <config_cmd_default.h>
  64
  65 #define CONFIG_CMD_DHCP
  66 #define CONFIG_CMD_PCI
  67 #define CONFIG_CMD_IRQ
  68 #define CONFIG_CMD_IDE
  69 #define CONFIG_CMD_FAT
  70 #define CONFIG_CMD_ELF
  71 #define CONFIG_CMD_NAND
  72 #define CONFIG_CMD_DATE
  73 #define CONFIG_CMD_I2C
  74 #define CONFIG_CMD_MII
  75 #define CONFIG_CMD_PING
  76 #define CONFIG_CMD_EEPROM
  77 #define CONFIG_CMD_USB
  78
  79 #define CONFIG_OF_LIBFDT
  80 #define CONFIG_OF_BOARD_SETUP
  81
  82 #define CONFIG_MAC_PARTITION
  83 #define CONFIG_DOS_PARTITION
  84
  85 #define CONFIG_SUPPORT_VFAT
  86
  87 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  88
  89 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  90 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
  91
  92 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  93
  94 /*
  95  * Miscellaneous configurable options
  96  */
  97 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  98
  99 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 100
 101 #if defined(CONFIG_CMD_KGDB)
 102 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 103 #else
 104 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 105 #endif
 106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 107 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 108 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 109
 110 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 111
 112 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 113
 114 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 115
 116 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 117 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 118
 119 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 120 #define CONFIG_SYS_NS16550
 121 #define CONFIG_SYS_NS16550_SERIAL
 122 #define CONFIG_SYS_NS16550_REG_SIZE     1
 123 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 124
 125 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 126 #define CONFIG_SYS_BASE_BAUD        691200
 127
 128 /* The following table includes the supported baudrates */
 129 #define CONFIG_SYS_BAUDRATE_TABLE       \
 130         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 131          57600, 115200, 230400, 460800, 921600 }
 132
 133 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 134 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 135
 136 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 137
 138 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 139 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 140 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 141
 142 /* Only interrupt boot if space is pressed */
 143 /* If a long serial cable is connected but */
 144 /* other end is dead, garbage will be read */
 145 #define CONFIG_AUTOBOOT_KEYED   1
 146 #define CONFIG_AUTOBOOT_PROMPT  \
 147         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 148 #undef CONFIG_AUTOBOOT_DELAY_STR
 149 #define CONFIG_AUTOBOOT_STOP_STR " "
 150
 151 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 152
 153 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 154
 155 /*
 156  * NAND-FLASH stuff
 157  */
 158 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 159 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 160 #define NAND_BIG_DELAY_US       25
 161
 162 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 163 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 164 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 165 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 166
 167 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 168 #define CONFIG_SYS_NAND_QUIET          1
 169
 170 /*
 171  * PCI stuff
 172  */
 173 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 174 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 175 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 176
 177 #define CONFIG_PCI                      /* include pci support          */
 178 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 179 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 180 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 181                                         /* resource configuration       */
 182
 183 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 184
 185 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 186
 187 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 188 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 189 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 190 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 191 #define CONFIG_SYS_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
 192 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 193 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 194 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 195 #define CONFIG_SYS_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
 196
 197 /*
 198  * IDE/ATA stuff
 199  */
 200 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 201 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 202 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 203
 204 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 205 /* max. 1 drives per IDE bus */
 206 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1)
 207
 208 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 209 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 210
 211 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O */
 212 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register access */
 213 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers */
 214
 215 /*
 216  * For booting Linux, the board info and command line data
 217  * have to be in the first 8 MB of memory, since this is
 218  * the maximum mapped by the Linux kernel during initialization.
 219  */
 220 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 221
 222 /*
 223  * FLASH organization
 224  */
 225 #define FLASH_BASE0_PRELIM      0xFFC00000 /* FLASH bank #0 */
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 228 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 229
 230 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 231 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms) */
 232
 233 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width) */
 234 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st addr for flash config cycles */
 235 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd addr for flash config cycles */
 236 /*
 237  * The following defines are added for buggy IOP480 byte interface.
 238  * All other boards should use the standard values (CPCI405 etc.)
 239  */
 240 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard */
 241 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard */
 242 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard */
 243
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector */
 245
 246 /*
 247  * Start addresses for the final memory configuration
 248  * (Set up by the startup code)
 249  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 250  */
 251 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 252 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 253 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 254 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 255 #define CONFIG_SYS_MALLOC_LEN           (1024 << 10)
 256
 257 /*
 258  * Environment Variable setup
 259  */
 260 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 261 #define CONFIG_ENV_OFFSET               0x100   /* reseve 0x100 bytes for strapping */
 262 #define CONFIG_ENV_SIZE         0x700
 263
 264 /*
 265  * I2C EEPROM (24WC16) for environment
 266  */
 267 #define CONFIG_SYS_I2C
 268 #define CONFIG_SYS_I2C_PPC4XX
 269 #define CONFIG_SYS_I2C_PPC4XX_CH0
 270 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 271 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 272
 273 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM 24WC16 */
 274 #define CONFIG_SYS_EEPROM_WREN         1
 275
 276 /* 24WC16 */
 277 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 278 /* mask of address bits that overflow into the "EEPROM chip address"    */
 279 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 280 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The 24WC16 has   */
 281                                         /* 16 byte page write mode using */
 282                                         /* last 4 bits of the address   */
 283 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 284
 285 /*
 286  * External Bus Controller (EBC) Setup
 287  */
 288 #define CAN0_BA         0xF0000000          /* CAN0 Base Address        */
 289 #define CAN1_BA         0xF0000100          /* CAN1 Base Address        */
 290 #define DUART0_BA       0xF0000400          /* DUART Base Address       */
 291 #define DUART1_BA       0xF0000408          /* DUART Base Address       */
 292 #define RTC_BA          0xF0000500          /* RTC Base Address         */
 293 #define VGA_BA          0xF1000000          /* Epson VGA Base Address   */
 294 #define CONFIG_SYS_NAND_BASE    0xF4000000          /* NAND FLASH Base Address  */
 295
 296 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
 297 /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 298 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 299 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 300 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000
 301
 302 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
 303 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 304 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
 305 #define CONFIG_SYS_EBC_PB1CR            0xF4018000
 306
 307 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
 308 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 309 #define CONFIG_SYS_EBC_PB2AP            0x010053C0
 310 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 311 #define CONFIG_SYS_EBC_PB2CR            0xF0018000
 312
 313 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
 314 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 315 #define CONFIG_SYS_EBC_PB3AP            0x010053C0
 316 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 317 #define CONFIG_SYS_EBC_PB3CR            0xF011A000
 318
 319 /*
 320  * FPGA stuff
 321  */
 322 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100        /* FPGA internal Base Address */
 323
 324 /* FPGA internal regs */
 325 #define CONFIG_SYS_FPGA_CTRL            0x000
 326
 327 /* FPGA Control Reg */
 328 #define CONFIG_SYS_FPGA_CTRL_CF_RESET   0x0001
 329 #define CONFIG_SYS_FPGA_CTRL_WDI        0x0002
 330 #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 331
 332 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now */
 333 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024    /* 128kByte is enough for XC2S50E*/
 334
 335 /* FPGA program pin configuration */
 336 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 337 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output) */
 338 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output) */
 339 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input) */
 340 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input) */
 341
 342 /*
 343  * Definitions for initial stack pointer and data area (in data cache)
 344  */
 345 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 346 #define CONFIG_SYS_TEMP_STACK_OCM         1
 347
 348 /* On Chip Memory location */
 349 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 350 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 351 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
 352 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM  */
 353
 354 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 355 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 356
 357 /*
 358  * Definitions for GPIO setup (PPC405EP specific)
 359  *
 360  * GPIO0[0]     - External Bus Controller BLAST output
 361  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 362  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 363  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 364  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 365  * GPIO0[24-27] - UART0 control signal inputs/outputs
 366  * GPIO0[28-29] - UART1 data signal input/output
 367  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 368  */
 369 #define CONFIG_SYS_GPIO0_OSRL           0x00000550
 370 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 371 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 372 #define CONFIG_SYS_GPIO0_ISR1H          0x15555445
 373 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 374 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 375 #define CONFIG_SYS_GPIO0_TCR            0x77FE0014
 376
 377 #define CONFIG_SYS_DUART_RST            (0x80000000 >> 14)
 378 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 0)
 379
 380 /*
 381  * Default speed selection (cpu_plb_opb_ebc) in MHz.
 382  * This value will be set if iic boot eprom is disabled.
 383  */
 384 #if 1
 385 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 386 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 387 #endif
 388 #if 0
 389 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 390 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 391 #endif
 392 #if 0
 393 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 394 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 395 #endif
 396
 397 /*
 398  * PCI OHCI controller
 399  */
 400 #define CONFIG_USB_OHCI_NEW     1
 401 #define CONFIG_PCI_OHCI         1
 402 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 403 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 404 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 405 #define CONFIG_USB_STORAGE      1
 406
 407 /*
 408  * UBI
 409  */
 410 #define CONFIG_CMD_UBI
 411 #define CONFIG_RBTREE
 412 #define CONFIG_MTD_DEVICE
 413 #define CONFIG_MTD_PARTITIONS
 414 #define CONFIG_CMD_MTDPARTS
 415 #define CONFIG_LZO
 416
 417 #endif  /* __CONFIG_H */