include/configs/PM520.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  34 #define CONFIG_PM520            1       /* ... on PM520 board */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33MHz */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  41 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  42
  43 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  49 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  50 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  51
  52
  53 #ifdef CONFIG_MPC5200   /* MPC5100 PCI is not supported yet. */
  54 /*
  55  * PCI Mapping:
  56  * 0x40000000 - 0x4fffffff - PCI Memory
  57  * 0x50000000 - 0x50ffffff - PCI IO Space
  58  */
  59 #define CONFIG_PCI              1
  60 #define CONFIG_PCI_PNP          1
  61 #define CONFIG_PCI_SCAN_SHOW    1
  62 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  63
  64 #define CONFIG_PCI_MEM_BUS      0x40000000
  65 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  66 #define CONFIG_PCI_MEM_SIZE     0x10000000
  67
  68 #define CONFIG_PCI_IO_BUS       0x50000000
  69 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  70 #define CONFIG_PCI_IO_SIZE      0x01000000
  71
  72 #define CONFIG_NET_MULTI        1
  73 #define CONFIG_MII              1
  74 #define CONFIG_EEPRO100         1
  75 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  76 #undef  CONFIG_NS8382X
  77
  78 #endif
  79
  80 /* Partitions */
  81 #define CONFIG_DOS_PARTITION
  82
  83 /* USB */
  84 #if 1
  85 #define CONFIG_USB_OHCI
  86 #define CONFIG_USB_STORAGE
  87 #endif
  88
  89 #if !defined(CONFIG_BOOT_ROM)
  90 /* DoC requires legacy NAND for now */
  91 #define CONFIG_NAND_LEGACY
  92 #endif
  93
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_BOOTFILESIZE
  99 #define CONFIG_BOOTP_BOOTPATH
 100 #define CONFIG_BOOTP_GATEWAY
 101 #define CONFIG_BOOTP_HOSTNAME
 102
 103
 104 /*
 105  * Command line configuration.
 106  */
 107 #include <config_cmd_default.h>
 108
 109 #define CONFIG_CMD_BEDBUG
 110 #define CONFIG_CMD_DATE
 111 #define CONFIG_CMD_DHCP
 112 #define CONFIG_CMD_EEPROM
 113 #define CONFIG_CMD_FAT
 114 #define CONFIG_CMD_I2C
 115 #define CONFIG_CMD_IDE
 116 #define CONFIG_CMD_NFS
 117 #define CONFIG_CMD_SNTP
 118 #define CONFIG_CMD_USB
 119
 120 #if !defined(CONFIG_BOOT_ROM)
 121 #define CONFIG_CMD_DOC
 122 #endif
 123
 124 #if defined(CONFIG_MPC5200)
 125 #define CONFIG_CMD_PCI
 126 #endif
 127
 128
 129 /*
 130  * Autobooting
 131  */
 132 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 133
 134 #define CONFIG_PREBOOT  "echo;" \
 135         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 136         "echo"
 137
 138 #undef  CONFIG_BOOTARGS
 139
 140 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 141         "netdev=eth0\0"                                                 \
 142         "hostname=pm520\0"                                                      \
 143         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 144                 "nfsroot=${serverip}:${rootpath}\0"                     \
 145         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 146         "addip=setenv bootargs ${bootargs} "                            \
 147                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 148                 ":${hostname}:${netdev}:off panic=1\0"                  \
 149         "flash_nfs=run nfsargs addip;"                                  \
 150                 "bootm ${kernel_addr}\0"                                \
 151         "flash_self=run ramargs addip;"                                 \
 152                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 153         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 154         "rootpath=/opt/eldk30/ppc_82xx\0"                                       \
 155         "bootfile=/tftpboot/PM520/uImage\0"                             \
 156         ""
 157
 158 #define CONFIG_BOOTCOMMAND      "run flash_self"
 159
 160 #if defined(CONFIG_MPC5200)
 161 /*
 162  * IPB Bus clocking configuration.
 163  */
 164 #undef CFG_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 165 #endif
 166 /*
 167  * I2C configuration
 168  */
 169 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 170 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 171
 172 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 173 #define CFG_I2C_SLAVE           0x7F
 174
 175 /*
 176  * EEPROM configuration
 177  */
 178 #define CFG_I2C_EEPROM_ADDR             0x58
 179 #define CFG_I2C_EEPROM_ADDR_LEN         1
 180 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 181 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 182
 183 /*
 184  * RTC configuration
 185  */
 186 #define CONFIG_RTC_PCF8563
 187 #define CFG_I2C_RTC_ADDR                0x51
 188
 189 /*
 190  * Disk-On-Chip configuration
 191  */
 192
 193 #define CFG_DOC_SHORT_TIMEOUT
 194 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
 195
 196 #define CFG_DOC_SUPPORT_2000
 197 #define CFG_DOC_SUPPORT_MILLENNIUM
 198 #define CFG_DOC_BASE            0xE0000000
 199 #define CFG_DOC_SIZE            0x00100000
 200
 201 #if defined(CONFIG_BOOT_ROM)
 202 /*
 203  * Flash configuration (8,16 or 32 MB)
 204  * TEXT base always at 0xFFF00000
 205  * ENV_ADDR always at  0xFFF40000
 206  * FLASH_BASE at 0xFA000000 for 64 MB
 207  *               0xFC000000 for 32 MB
 208  *               0xFD000000 for 16 MB
 209  *               0xFD800000 for  8 MB
 210  */
 211 #define CFG_FLASH_BASE          0xFA000000
 212 #define CFG_FLASH_SIZE          0x04000000
 213 #define CFG_BOOTROM_BASE        0xFFF00000
 214 #define CFG_BOOTROM_SIZE        0x00080000
 215 #define CFG_ENV_ADDR            (0xFDF00000 + 0x40000)
 216 #else
 217 /*
 218  * Flash configuration (8,16 or 32 MB)
 219  * TEXT base always at 0xFFF00000
 220  * ENV_ADDR always at  0xFFF40000
 221  * FLASH_BASE at 0xFC000000 for 64 MB
 222  *               0xFE000000 for 32 MB
 223  *               0xFF000000 for 16 MB
 224  *               0xFF800000 for  8 MB
 225  */
 226 #define CFG_FLASH_BASE          0xFC000000
 227 #define CFG_FLASH_SIZE          0x04000000
 228 #define CFG_ENV_ADDR            (0xFFF00000 + 0x40000)
 229 #endif
 230 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 231
 232 #define CFG_MAX_FLASH_SECT      256     /* max num of sects on one chip */
 233
 234 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 235 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 236 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 237 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 238 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 239
 240 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 241
 242 #undef CONFIG_FLASH_16BIT       /* Flash is 32-bit */
 243
 244
 245 /*
 246  * Environment settings
 247  */
 248 #define CFG_ENV_IS_IN_FLASH     1
 249 #define CFG_ENV_SIZE            0x10000
 250 #define CFG_ENV_SECT_SIZE       0x40000
 251 #define CONFIG_ENV_OVERWRITE    1
 252
 253 /*
 254  * Memory map
 255  */
 256 #define CFG_MBAR                0xf0000000
 257 #define CFG_SDRAM_BASE          0x00000000
 258 #define CFG_DEFAULT_MBAR        0x80000000
 259
 260 /* Use SRAM until RAM will be available */
 261 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 262 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 263
 264
 265 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 266 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 267 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 268
 269 #define CFG_MONITOR_BASE    TEXT_BASE
 270 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 271 #   define CFG_RAMBOOT          1
 272 #endif
 273
 274 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 275 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 276 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 277
 278 /*
 279  * Ethernet configuration
 280  */
 281 #define CONFIG_MPC5xxx_FEC      1
 282 /*
 283  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 284  */
 285 /* #define CONFIG_FEC_10MBIT 1 */
 286 #define CONFIG_PHY_ADDR         0x00
 287
 288 /*
 289  * GPIO configuration
 290  */
 291 #define CFG_GPS_PORT_CONFIG     0x10000004
 292
 293 /*
 294  * Miscellaneous configurable options
 295  */
 296 #define CFG_LONGHELP                    /* undef to save memory     */
 297 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 298 #if defined(CONFIG_CMD_KGDB)
 299 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 300 #else
 301 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 302 #endif
 303 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 304 #define CFG_MAXARGS             16              /* max number of command args   */
 305 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 306
 307 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 308 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 309
 310 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 311
 312 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 313
 314 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 315 #if defined(CONFIG_CMD_KGDB)
 316 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 317 #endif
 318
 319 /*
 320  * Various low-level settings
 321  */
 322 #if defined(CONFIG_MPC5200)
 323 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 324 #define CFG_HID0_FINAL          HID0_ICE
 325 #else
 326 #define CFG_HID0_INIT           0
 327 #define CFG_HID0_FINAL          0
 328 #endif
 329
 330 #if defined(CONFIG_BOOT_ROM)
 331 #define CFG_BOOTCS_START        CFG_BOOTROM_BASE
 332 #define CFG_BOOTCS_SIZE         CFG_BOOTROM_SIZE
 333 #define CFG_BOOTCS_CFG          0x00047800
 334 #define CFG_CS0_START           CFG_BOOTROM_BASE
 335 #define CFG_CS0_SIZE            CFG_BOOTROM_SIZE
 336 #define CFG_CS1_START           CFG_FLASH_BASE
 337 #define CFG_CS1_SIZE            CFG_FLASH_SIZE
 338 #define CFG_CS1_CFG             0x0004FF00
 339 #else
 340 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 341 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 342 #define CFG_BOOTCS_CFG          0x0004FF00
 343 #define CFG_CS0_START           CFG_FLASH_BASE
 344 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 345 #define CFG_CS1_START           CFG_DOC_BASE
 346 #define CFG_CS1_SIZE            CFG_DOC_SIZE
 347 #define CFG_CS1_CFG             0x00047800
 348 #endif
 349
 350 #define CFG_CS_BURST            0x00000000
 351 #define CFG_CS_DEADCYCLE        0x33333333
 352
 353 #define CFG_RESET_ADDRESS       0xff000000
 354
 355 /*-----------------------------------------------------------------------
 356  * USB stuff
 357  *-----------------------------------------------------------------------
 358  */
 359 #define CONFIG_USB_CLOCK        0x0001BBBB
 360 #define CONFIG_USB_CONFIG       0x00005000
 361
 362 /*-----------------------------------------------------------------------
 363  * IDE/ATA stuff Supports IDE harddisk
 364  *-----------------------------------------------------------------------
 365  */
 366
 367 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 368
 369 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 370 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 371
 372 #undef  CONFIG_IDE_RESET                /* reset for ide supported      */
 373 #define CONFIG_IDE_PREINIT
 374
 375 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 376 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drive per IDE bus     */
 377
 378 #define CFG_ATA_IDE0_OFFSET     0x0000
 379
 380 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 381
 382 /* Offset for data I/O                  */
 383 #define CFG_ATA_DATA_OFFSET     (0x0060)
 384
 385 /* Offset for normal register accesses  */
 386 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 387
 388 /* Offset for alternate registers       */
 389 #define CFG_ATA_ALT_OFFSET      (0x005C)
 390
 391 /* Interval between registers                                                */
 392 #define CFG_ATA_STRIDE          4
 393
 394 #endif /* __CONFIG_H */