include/configs/PM520.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  34 #define CONFIG_PM520            1       /* ... on PM520 board */
  35
  36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  41 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  42
  43 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  49 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  50 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  51
  52
  53 #ifdef CONFIG_MPC5200   /* MPC5100 PCI is not supported yet. */
  54 /*
  55  * PCI Mapping:
  56  * 0x40000000 - 0x4fffffff - PCI Memory
  57  * 0x50000000 - 0x50ffffff - PCI IO Space
  58  */
  59 #define CONFIG_PCI              1
  60 #define CONFIG_PCI_PNP          1
  61 #define CONFIG_PCI_SCAN_SHOW    1
  62 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  63
  64 #define CONFIG_PCI_MEM_BUS      0x40000000
  65 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  66 #define CONFIG_PCI_MEM_SIZE     0x10000000
  67
  68 #define CONFIG_PCI_IO_BUS       0x50000000
  69 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  70 #define CONFIG_PCI_IO_SIZE      0x01000000
  71
  72 #define CONFIG_NET_MULTI        1
  73 #define CONFIG_MII              1
  74 #define CONFIG_EEPRO100         1
  75 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  76 #undef  CONFIG_NS8382X
  77
  78 #endif
  79
  80 /* Partitions */
  81 #define CONFIG_DOS_PARTITION
  82
  83 /* USB */
  84 #if 1
  85 #define CONFIG_USB_OHCI
  86 #define CONFIG_USB_STORAGE
  87 #endif
  88
  89 /*
  90  * BOOTP options
  91  */
  92 #define CONFIG_BOOTP_BOOTFILESIZE
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_GATEWAY
  95 #define CONFIG_BOOTP_HOSTNAME
  96
  97
  98 /*
  99  * Command line configuration.
 100  */
 101 #include <config_cmd_default.h>
 102
 103 #define CONFIG_CMD_BEDBUG
 104 #define CONFIG_CMD_DATE
 105 #define CONFIG_CMD_DHCP
 106 #define CONFIG_CMD_EEPROM
 107 #define CONFIG_CMD_FAT
 108 #define CONFIG_CMD_I2C
 109 #define CONFIG_CMD_IDE
 110 #define CONFIG_CMD_NFS
 111 #define CONFIG_CMD_SNTP
 112 #define CONFIG_CMD_USB
 113
 114 #if defined(CONFIG_MPC5200)
 115 #define CONFIG_CMD_PCI
 116 #endif
 117
 118
 119 /*
 120  * Autobooting
 121  */
 122 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 123
 124 #define CONFIG_PREBOOT  "echo;" \
 125         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 126         "echo"
 127
 128 #undef  CONFIG_BOOTARGS
 129
 130 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 131         "netdev=eth0\0"                                                 \
 132         "hostname=pm520\0"                                                      \
 133         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 134                 "nfsroot=${serverip}:${rootpath}\0"                     \
 135         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 136         "addip=setenv bootargs ${bootargs} "                            \
 137                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 138                 ":${hostname}:${netdev}:off panic=1\0"                  \
 139         "flash_nfs=run nfsargs addip;"                                  \
 140                 "bootm ${kernel_addr}\0"                                \
 141         "flash_self=run ramargs addip;"                                 \
 142                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 143         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 144         "rootpath=/opt/eldk30/ppc_82xx\0"                                       \
 145         "bootfile=/tftpboot/PM520/uImage\0"                             \
 146         ""
 147
 148 #define CONFIG_BOOTCOMMAND      "run flash_self"
 149
 150 #if defined(CONFIG_MPC5200)
 151 /*
 152  * IPB Bus clocking configuration.
 153  */
 154 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 155 #endif
 156 /*
 157  * I2C configuration
 158  */
 159 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 160 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 161
 162 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 163 #define CONFIG_SYS_I2C_SLAVE            0x7F
 164
 165 /*
 166  * EEPROM configuration
 167  */
 168 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 169 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 170 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 172
 173 /*
 174  * RTC configuration
 175  */
 176 #define CONFIG_RTC_PCF8563
 177 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 178
 179 #define CONFIG_SYS_DOC_BASE             0xE0000000
 180 #define CONFIG_SYS_DOC_SIZE             0x00100000
 181
 182 #if defined(CONFIG_BOOT_ROM)
 183 /*
 184  * Flash configuration (8,16 or 32 MB)
 185  * TEXT base always at 0xFFF00000
 186  * ENV_ADDR always at  0xFFF40000
 187  * FLASH_BASE at 0xFA000000 for 64 MB
 188  *               0xFC000000 for 32 MB
 189  *               0xFD000000 for 16 MB
 190  *               0xFD800000 for  8 MB
 191  */
 192 #define CONFIG_SYS_FLASH_BASE           0xFA000000
 193 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 194 #define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
 195 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 196 #define CONFIG_ENV_ADDR         (0xFDF00000 + 0x40000)
 197 #else
 198 /*
 199  * Flash configuration (8,16 or 32 MB)
 200  * TEXT base always at 0xFFF00000
 201  * ENV_ADDR always at  0xFFF40000
 202  * FLASH_BASE at 0xFC000000 for 64 MB
 203  *               0xFE000000 for 32 MB
 204  *               0xFF000000 for 16 MB
 205  *               0xFF800000 for  8 MB
 206  */
 207 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 208 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 209 #define CONFIG_ENV_ADDR         (0xFFF00000 + 0x40000)
 210 #endif
 211 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 212
 213 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 214
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 217 #define CONFIG_SYS_FLASH_LOCK_TOUT      5       /* Timeout for Flash Set Lock Bit (in ms) */
 218 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 219 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 220
 221 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 222
 223 #undef CONFIG_FLASH_16BIT       /* Flash is 32-bit */
 224
 225
 226 /*
 227  * Environment settings
 228  */
 229 #define CONFIG_ENV_IS_IN_FLASH  1
 230 #define CONFIG_ENV_SIZE         0x10000
 231 #define CONFIG_ENV_SECT_SIZE    0x40000
 232 #define CONFIG_ENV_OVERWRITE    1
 233
 234 /*
 235  * Memory map
 236  */
 237 #define CONFIG_SYS_MBAR         0xf0000000
 238 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 239 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 240
 241 /* Use SRAM until RAM will be available */
 242 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 243 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 244
 245
 246 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 247 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 248 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 249
 250 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 251 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 252 #   define CONFIG_SYS_RAMBOOT           1
 253 #endif
 254
 255 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 256 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 257 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 258
 259 /*
 260  * Ethernet configuration
 261  */
 262 #define CONFIG_MPC5xxx_FEC      1
 263 #define CONFIG_MPC5xxx_FEC_MII100
 264 /*
 265  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 266  */
 267 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 268 #define CONFIG_PHY_ADDR         0x00
 269
 270 /*
 271  * GPIO configuration
 272  */
 273 #define CONFIG_SYS_GPS_PORT_CONFIG      0x10000004
 274
 275 /*
 276  * Miscellaneous configurable options
 277  */
 278 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 279 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 280 #if defined(CONFIG_CMD_KGDB)
 281 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 282 #else
 283 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 284 #endif
 285 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 286 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 287 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 288
 289 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 290 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 291
 292 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 293
 294 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 295
 296 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 297 #if defined(CONFIG_CMD_KGDB)
 298 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 299 #endif
 300
 301 /*
 302  * Various low-level settings
 303  */
 304 #if defined(CONFIG_MPC5200)
 305 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 306 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 307 #else
 308 #define CONFIG_SYS_HID0_INIT            0
 309 #define CONFIG_SYS_HID0_FINAL           0
 310 #endif
 311
 312 #if defined(CONFIG_BOOT_ROM)
 313 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
 314 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_BOOTROM_SIZE
 315 #define CONFIG_SYS_BOOTCS_CFG           0x00047800
 316 #define CONFIG_SYS_CS0_START            CONFIG_SYS_BOOTROM_BASE
 317 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_BOOTROM_SIZE
 318 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE
 319 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 320 #define CONFIG_SYS_CS1_CFG              0x0004FF00
 321 #else
 322 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 323 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 324 #define CONFIG_SYS_BOOTCS_CFG           0x0004FF00
 325 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 326 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 327 #define CONFIG_SYS_CS1_START            CONFIG_SYS_DOC_BASE
 328 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_DOC_SIZE
 329 #define CONFIG_SYS_CS1_CFG              0x00047800
 330 #endif
 331
 332 #define CONFIG_SYS_CS_BURST             0x00000000
 333 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 334
 335 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 336
 337 /*-----------------------------------------------------------------------
 338  * USB stuff
 339  *-----------------------------------------------------------------------
 340  */
 341 #define CONFIG_USB_CLOCK        0x0001BBBB
 342 #define CONFIG_USB_CONFIG       0x00005000
 343
 344 /*-----------------------------------------------------------------------
 345  * IDE/ATA stuff Supports IDE harddisk
 346  *-----------------------------------------------------------------------
 347  */
 348
 349 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 350
 351 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 352 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 353
 354 #undef  CONFIG_IDE_RESET                /* reset for ide supported      */
 355 #define CONFIG_IDE_PREINIT
 356
 357 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 358 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drive per IDE bus     */
 359
 360 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 361
 362 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 363
 364 /* Offset for data I/O                  */
 365 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 366
 367 /* Offset for normal register accesses  */
 368 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 369
 370 /* Offset for alternate registers       */
 371 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 372
 373 /* Interval between registers                                                */
 374 #define CONFIG_SYS_ATA_STRIDE          4
 375
 376 #endif /* __CONFIG_H */