include/configs/PMC405DE.h

   1 /*
   2  * (C) Copyright 2009
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  12 #define CONFIG_PMC405DE         1       /* ...on a PMC405DE board       */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15 #define CONFIG_SYS_GENERIC_BOARD
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  19 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  20 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  21
  22 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  23
  24 #define CONFIG_BAUDRATE         115200
  25 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  26
  27 #undef  CONFIG_BOOTARGS
  28 #undef  CONFIG_BOOTCOMMAND
  29
  30 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  31
  32 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change*/
  33
  34 #define CONFIG_HAS_ETH1
  35
  36 #define CONFIG_PPC4xx_EMAC
  37 #define CONFIG_MII              1       /* MII PHY management           */
  38 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
  39 #define CONFIG_PHY1_ADDR        2       /* 2nd PHY address              */
  40
  41 #define CONFIG_SYS_RX_ETH_BUFFER        16 /* use 16 rx buffer on 405 emac */
  42
  43 /*
  44  * BOOTP options
  45  */
  46 #define CONFIG_BOOTP_SUBNETMASK
  47 #define CONFIG_BOOTP_GATEWAY
  48 #define CONFIG_BOOTP_HOSTNAME
  49 #define CONFIG_BOOTP_BOOTPATH
  50 #define CONFIG_BOOTP_DNS
  51 #define CONFIG_BOOTP_DNS2
  52 #define CONFIG_BOOTP_SEND_HOSTNAME
  53
  54 /*
  55  * Command line configuration.
  56  */
  57 #include <config_cmd_default.h>
  58
  59 #define CONFIG_CMD_BSP
  60 #define CONFIG_CMD_CHIP_CONFIG
  61 #define CONFIG_CMD_DATE
  62 #define CONFIG_CMD_DHCP
  63 #define CONFIG_CMD_EEPROM
  64 #define CONFIG_CMD_ELF
  65 #define CONFIG_CMD_I2C
  66 #define CONFIG_CMD_IRQ
  67 #define CONFIG_CMD_MII
  68 #define CONFIG_CMD_NFS
  69 #define CONFIG_CMD_PCI
  70 #define CONFIG_CMD_PING
  71
  72 #define CONFIG_OF_LIBFDT
  73 #define CONFIG_OF_BOARD_SETUP
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
  76 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  77 #define CONFIG_PRAM             0
  78
  79 /*
  80  * Miscellaneous configurable options
  81  */
  82 #define CONFIG_SYS_LONGHELP
  83
  84 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
  85 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  86 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
  87 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  88
  89 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  90 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console info */
  91
  92 #define CONFIG_SYS_MEMTEST_START        0x0100000 /* memtest works on */
  93 #define CONFIG_SYS_MEMTEST_END          0x3000000 /* 1 ... 48 MB in DRAM */
  94
  95 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  96 #define CONFIG_SYS_NS16550
  97 #define CONFIG_SYS_NS16550_SERIAL
  98 #define CONFIG_SYS_NS16550_REG_SIZE     1
  99 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 100
 101 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK
 102 #define CONFIG_SYS_BASE_BAUD            691200
 103
 104 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 105 #define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
 106
 107 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 108 #define CONFIG_LOOPW            1       /* enable loopw command         */
 109 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 110 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 111 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 112
 113 #define CONFIG_AUTOBOOT_KEYED   1
 114 #define CONFIG_AUTOBOOT_PROMPT  \
 115         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 116 #undef CONFIG_AUTOBOOT_DELAY_STR
 117 #define CONFIG_AUTOBOOT_STOP_STR " "
 118
 119 /*
 120  * PCI stuff
 121  */
 122 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 123 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 124 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 125
 126 #define CONFIG_PCI              /* include pci support                  */
 127 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 128 #define CONFIG_PCI_HOST PCI_HOST_AUTO  /* select pci host function      */
 129 #define CONFIG_PCI_PNP          /* do (not) pci plug-and-play           */
 130
 131 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup          */
 132
 133 /*
 134  * PCI identification
 135  */
 136 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          PCI_VENDOR_ID_ESDGMBH
 137 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
 138 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
 139 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 140 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 141
 142 #define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
 143 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 144
 145 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
 146 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
 147 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
 148 #define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
 149 #define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
 150 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */
 151
 152 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 153
 154 /*
 155  * For booting Linux, the board info and command line data
 156  * have to be in the first 8 MB of memory, since this is
 157  * the maximum mapped by the Linux kernel during initialization.
 158  */
 159 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 160 /*
 161  * FLASH organization
 162  */
 163 #define CONFIG_SYS_FLASH_CFI            1       /* CFI compatible */
 164 #define CONFIG_FLASH_CFI_DRIVER         1       /* Use common CFI driver */
 165
 166 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 167
 168 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max. no. memory banks */
 169 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per chip */
 170
 171 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* erase timeout (in ms) */
 172 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* write timeout (in ms) */
 173
 174 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* buffered writes (faster) */
 175 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection */
 176
 177 #define CONFIG_SYS_FLASH_EMPTY_INFO     1 /* 'E' for empty sector (flinfo) */
 178 #define CONFIG_SYS_FLASH_QUIET_TEST     1 /* don't warn upon unknown flash */
 179
 180
 181 /*
 182  * Start addresses for the final memory configuration
 183  * (Set up by the startup code)
 184  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 185  */
 186 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 187 #define CONFIG_SYS_FLASH_BASE           0xfe000000
 188 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 189 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 190 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 191
 192 /*
 193  * Environment in EEPROM setup
 194  */
 195 #define CONFIG_ENV_IS_IN_EEPROM         1
 196 #define CONFIG_ENV_OFFSET               0x100
 197 #define CONFIG_ENV_SIZE                 0x700
 198
 199 /*
 200  * I2C EEPROM (24W16) for environment
 201  */
 202 #define CONFIG_SYS_I2C
 203 #define CONFIG_SYS_I2C_PPC4XX
 204 #define CONFIG_SYS_I2C_PPC4XX_CH0
 205 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 206 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 207
 208 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM 24W16 */
 209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 210 /* mask of address bits that overflow into the "EEPROM chip address" */
 211 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has */
 213                                         /* 16 byte page write mode using*/
 214                                         /* last 4 bits of the address */
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
 216 #define CONFIG_SYS_EEPROM_WREN          1
 217
 218 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 219 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0x40
 220 #define CONFIG_4xx_CONFIG_BLOCKSIZE             0x20
 221
 222 /*
 223  * RTC
 224  */
 225 #define CONFIG_RTC_RX8025
 226
 227 /*
 228  * External Bus Controller (EBC) Setup
 229  * (max. 55MHZ EBC clock)
 230  */
 231 /* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
 232 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 233 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xba000)
 234
 235 /* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
 236 #define CONFIG_SYS_CPLD_BASE            0xef000000
 237 #define CONFIG_SYS_EBC_PB1AP            0x00800000
 238 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 239
 240 /*
 241  * Definitions for initial stack pointer and data area (in data cache)
 242  */
 243 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 244 #define CONFIG_SYS_TEMP_STACK_OCM         1
 245
 246 /* On Chip Memory location */
 247 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 248 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 249 /* inside SDRAM */
 250 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 251 /* End of used area in RAM */
 252 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_OCM_DATA_SIZE
 253
 254 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 255                                          GENERATED_GBL_DATA_SIZE)
 256 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 257
 258 /*
 259  * GPIO Configuration
 260  */
 261 #define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
 262 {                                                                             \
 263 /* GPIO Core 0 */                                                             \
 264 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
 265 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
 266 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
 267 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
 268 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
 269 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
 270 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
 271 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
 272 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
 273 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
 274 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
 275 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
 276 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
 277 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
 278 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
 279 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
 280 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
 281 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
 282 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
 283 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
 284 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
 285 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
 286 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
 287 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
 288 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
 289 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
 290 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
 291 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
 292 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
 293 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
 294 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 295 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 296 }                                                                             \
 297 }
 298
 299 #define CONFIG_SYS_GPIO_HWREV_MASK      (0xf0000000 >> 1)       /* GPIO1..4 */
 300 #define CONFIG_SYS_GPIO_HWREV_SHIFT     27
 301 #define CONFIG_SYS_GPIO_LEDRUN_N        (0x80000000 >> 5)       /* GPIO5 */
 302 #define CONFIG_SYS_GPIO_LEDA_N          (0x80000000 >> 6)       /* GPIO6 */
 303 #define CONFIG_SYS_GPIO_LEDB_N          (0x80000000 >> 7)       /* GPIO7 */
 304 #define CONFIG_SYS_GPIO_SELFRST_N       (0x80000000 >> 8)       /* GPIO8 */
 305 #define CONFIG_SYS_GPIO_EEPROM_WP       (0x80000000 >> 9)       /* GPIO9 */
 306 #define CONFIG_SYS_GPIO_MONARCH_N       (0x80000000 >> 11)      /* GPIO11 */
 307 #define CONFIG_SYS_GPIO_EREADY          (0x80000000 >> 12)      /* GPIO12 */
 308 #define CONFIG_SYS_GPIO_M66EN           (0x80000000 >> 13)      /* GPIO13 */
 309
 310 /*
 311  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 312  * This value will be set if iic boot eprom is disabled.
 313  */
 314 #undef CONFIG_SYS_FCPU333MHZ
 315 #define CONFIG_SYS_FCPU266MHZ
 316 #undef CONFIG_SYS_FCPU133MHZ
 317
 318 #if defined(CONFIG_SYS_FCPU333MHZ)
 319 /*
 320  * CPU: 333MHz
 321  * PLB/SDRAM/MAL: 111MHz
 322  * OPB: 55MHz
 323  * EBC: 55MHz
 324  * PCI: 55MHz (111MHz on M66EN=1)
 325  */
 326 #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |           \
 327                         PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |        \
 328                         PLL_MALDIV_1 | PLL_PCIDIV_2)
 329 #define PLLMR1_DEFAULT (PLL_FBKDIV_10  |                        \
 330                         PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 331                         PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 332 #endif
 333
 334 #if defined(CONFIG_SYS_FCPU266MHZ)
 335 /*
 336  * CPU: 266MHz
 337  * PLB/SDRAM/MAL: 133MHz
 338  * OPB: 66MHz
 339  * EBC: 44MHz
 340  * PCI: 44MHz (66MHz on M66EN=1)
 341  */
 342 #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |           \
 343                         PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 344                         PLL_MALDIV_1 | PLL_PCIDIV_3)
 345 #define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
 346                         PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 347                         PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 348 #endif
 349
 350 #if defined(CONFIG_SYS_FCPU133MHZ)
 351 /*
 352  * CPU: 133MHz
 353  * PLB/SDRAM/MAL: 133MHz
 354  * OPB: 66MHz
 355  * EBC: 44MHz
 356  * PCI: 44MHz (66MHz on M66EN=1)
 357  */
 358 #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |           \
 359                         PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 360                         PLL_MALDIV_1 | PLL_PCIDIV_3)
 361 #define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
 362                         PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |         \
 363                         PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 364 #endif
 365
 366 #endif /* __CONFIG_H */