include/configs/PMC440.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on the sequoia configuration file.
   5  *
   6  * (C) Copyright 2006-2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 /************************************************************************
  17  * PMC440.h - configuration for esd PMC440 boards
  18  ***********************************************************************/
  19 #ifndef __CONFIG_H
  20 #define __CONFIG_H
  21
  22 /*-----------------------------------------------------------------------
  23  * High Level Configuration Options
  24  *----------------------------------------------------------------------*/
  25 #define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  26 #define CONFIG_440              1       /* ... PPC440 family    */
  27
  28 #ifndef CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_SYS_TEXT_BASE    0xFFF90000
  30 #endif
  31
  32 #define CONFIG_SYS_CLK_FREQ     33333400
  33
  34 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */
  35 #define CONFIG_4xx_DCACHE               /* enable dcache        */
  36 #endif
  37
  38 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  39 #define CONFIG_MISC_INIT_F      1
  40 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  41 #define CONFIG_BOARD_TYPES      1       /* support board types  */
  42 /*-----------------------------------------------------------------------
  43  * Base addresses -- Note these are effective addresses where the
  44  * actual resources get mapped (not physical addresses)
  45  *----------------------------------------------------------------------*/
  46 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
  47 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  48
  49 #define CONFIG_PRAM             0       /* use pram variable to overwrite */
  50
  51 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  52 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  53 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  54 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  55 #define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  56 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  57 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  58 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  59 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  60 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  61 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  62 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  63 #define CONFIG_SYS_PCI_MEMSIZE          0x80000000      /* 2GB! */
  64
  65 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  66 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  67 #define CONFIG_SYS_USB_HOST             0xe0000400
  68 #define CONFIG_SYS_FPGA_BASE0           0xef000000      /* 32 bit */
  69 #define CONFIG_SYS_FPGA_BASE1           0xef100000      /* 16 bit */
  70 #define CONFIG_SYS_RESET_BASE           0xef200000
  71
  72 /*-----------------------------------------------------------------------
  73  * Initial RAM & stack pointer
  74  *----------------------------------------------------------------------*/
  75 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  76 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  77 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  78 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  79 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  80
  81 /*-----------------------------------------------------------------------
  82  * Serial Port
  83  *----------------------------------------------------------------------*/
  84 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  85 #define CONFIG_SYS_NS16550_SERIAL
  86 #define CONFIG_SYS_NS16550_REG_SIZE     1
  87 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  88 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  89 #define CONFIG_BAUDRATE         115200
  90
  91 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
  92         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  93
  94 /*-----------------------------------------------------------------------
  95  * Environment
  96  *----------------------------------------------------------------------*/
  97 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use FLASH for environment vars */
  98
  99 /*-----------------------------------------------------------------------
 100  * RTC
 101  *----------------------------------------------------------------------*/
 102 #define CONFIG_RTC_RX8025
 103
 104 /*-----------------------------------------------------------------------
 105  * FLASH related
 106  *----------------------------------------------------------------------*/
 107 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 108 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
 109
 110 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 111
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 113 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 114
 115 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 116 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 117
 118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 119 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 120
 121 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 122 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 123
 124 #ifdef CONFIG_ENV_IS_IN_FLASH
 125 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 126 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 127 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 128
 129 /* Address and size of Redundant Environment Sector     */
 130 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 131 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 132 #endif
 133
 134 #ifdef CONFIG_ENV_IS_IN_EEPROM
 135 #define CONFIG_I2C_ENV_EEPROM_BUS       0
 136 #define CONFIG_ENV_OFFSET               0       /* environment starts at the beginning of the EEPROM */
 137 #define CONFIG_ENV_SIZE         0x1000  /* 4096 bytes may be used for env vars */
 138 #endif
 139
 140 /*-----------------------------------------------------------------------
 141  * DDR SDRAM
 142  *----------------------------------------------------------------------*/
 143 #define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 144 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
 145                                                   /* 440EPx errata CHIP 11 */
 146
 147 /*-----------------------------------------------------------------------
 148  * I2C
 149  *----------------------------------------------------------------------*/
 150 #define CONFIG_SYS_I2C
 151 #define CONFIG_SYS_I2C_PPC4XX
 152 #define CONFIG_SYS_I2C_PPC4XX_CH0
 153 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 154 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 155 #define CONFIG_SYS_I2C_PPC4XX_CH1
 156 #define CONFIG_SYS_I2C_PPC4XX_SPEED_1           400000
 157 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1           0x7F
 158
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 164
 165 #define CONFIG_SYS_EEPROM_WREN                  1
 166 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 167
 168 /*
 169  * standard dtt sensor configuration - bottom bit will determine local or
 170  * remote sensor of the TMP401
 171  */
 172 #define CONFIG_DTT_SENSORS              { 0, 1 }
 173
 174 /*
 175  * The PMC440 uses a TI TMP401 temperature sensor. This part
 176  * is basically compatible to the ADM1021 that is supported
 177  * by U-Boot.
 178  *
 179  * - i2c addr 0x4c
 180  * - conversion rate 0x02 = 0.25 conversions/second
 181  * - ALERT ouput disabled
 182  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 183  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 184  */
 185 #define CONFIG_DTT_ADM1021
 186 #define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 187
 188 #define CONFIG_PREBOOT          "echo Add \\\"run fpga\\\" and "        \
 189                                 "\\\"painit\\\" to preboot command"
 190
 191 #undef  CONFIG_BOOTARGS
 192
 193 /* Setup some board specific values for the default environment variables */
 194 #define CONFIG_HOSTNAME         pmc440
 195 #define CONFIG_SYS_BOOTFILE     "bootfile=/tftpboot/pmc440/uImage\0"
 196 #define CONFIG_SYS_ROOTPATH     "rootpath=/opt/eldk/ppc_4xxFP\0"
 197
 198 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 199         CONFIG_SYS_BOOTFILE                                             \
 200         CONFIG_SYS_ROOTPATH                                             \
 201         "fdt_file=/tftpboot/pmc440/pmc440.dtb\0"                        \
 202         "netdev=eth0\0"                                                 \
 203         "ethrotate=no\0"                                                \
 204         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 205         "nfsroot=${serverip}:${rootpath}\0"                             \
 206         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 207         "addip=setenv bootargs ${bootargs} "                            \
 208                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 209                 ":${hostname}:${netdev}:off panic=1\0"                  \
 210         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 211         "addmisc=setenv bootargs ${bootargs} mem=${mem}\0"              \
 212         "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 213         "nand_boot_fdt=run nandargs addip addtty addmisc;"              \
 214                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 215         "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"                \
 216                 "tftp  ${fdt_addr_r} ${fdt_file};"                      \
 217                 "run nfsargs addip addtty addmisc;"                     \
 218                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 219         "kernel_addr=ffc00000\0"                                        \
 220         "kernel_addr_r=200000\0"                                        \
 221         "fpga_addr=fff00000\0"                                          \
 222         "fdt_addr=fff80000\0"                                           \
 223         "fdt_addr_r=800000\0"                                           \
 224         "fpga=fpga loadb 0 ${fpga_addr}\0"                              \
 225         "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 226         "update=protect off fff90000 ffffffff;era fff90000 ffffffff;"   \
 227                 "cp.b 200000 fff90000 70000\0"                          \
 228         ""
 229
 230
 231 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 232 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 233
 234 #define CONFIG_PPC4xx_EMAC
 235 #define CONFIG_IBM_EMAC4_V4     1
 236 #define CONFIG_MII              1       /* MII PHY management           */
 237 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 238
 239 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 240
 241 #define CONFIG_HAS_ETH0
 242 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 243
 244 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 245 #define CONFIG_PHY1_ADDR        1
 246 #define CONFIG_RESET_PHY_R      1
 247
 248 /* USB */
 249 #define CONFIG_USB_OHCI_NEW
 250 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 251
 252 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 253 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 254 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 255 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 256 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 257
 258 /* Comment this out to enable USB 1.1 device */
 259 #define USB_2_0_DEVICE
 260
 261 /* Partitions */
 262 #define CONFIG_MAC_PARTITION
 263 #define CONFIG_DOS_PARTITION
 264 #define CONFIG_ISO_PARTITION
 265
 266 #define CONFIG_CMD_BSP
 267 #define CONFIG_CMD_DATE
 268 #define CONFIG_CMD_DTT
 269 #define CONFIG_CMD_EEPROM
 270 #define CONFIG_CMD_NAND
 271 #define CONFIG_CMD_PCI
 272 #define CONFIG_CMD_REGINFO
 273
 274 /* POST support */
 275 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY |       \
 276                                  CONFIG_SYS_POST_CPU    |       \
 277                                  CONFIG_SYS_POST_UART   |       \
 278                                  CONFIG_SYS_POST_I2C    |       \
 279                                  CONFIG_SYS_POST_CACHE  |       \
 280                                  CONFIG_SYS_POST_FPU    |       \
 281                                  CONFIG_SYS_POST_ETHER  |       \
 282                                  CONFIG_SYS_POST_SPR)
 283
 284 #define CONFIG_LOGBUFFER
 285 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 286
 287 #define CONFIG_SUPPORT_VFAT
 288
 289 /*-----------------------------------------------------------------------
 290  * Miscellaneous configurable options
 291  *----------------------------------------------------------------------*/
 292 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 293 #if defined(CONFIG_CMD_KGDB)
 294 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 295 #else
 296 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 297 #endif
 298 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 299 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 300 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 301
 302 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on          */
 303 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM       */
 304
 305 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address      */
 306 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 307
 308 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 309 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 310
 311 /*-----------------------------------------------------------------------
 312  * PCI stuff
 313  *----------------------------------------------------------------------*/
 314 /* General PCI */
 315 #define CONFIG_PCI              /* include pci support          */
 316 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 317 #define CONFIG_PCI_PNP          /* do (not) pci plug-and-play   */
 318 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 319 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 320 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 321
 322 /* Board-specific PCI */
 323 #define CONFIG_SYS_PCI_TARGET_INIT
 324 #define CONFIG_SYS_PCI_MASTER_INIT
 325 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 326
 327 #define CONFIG_PCI_BOOTDELAY 0
 328
 329 /* PCI identification */
 330 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 331 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441      /* PCI Device ID: Non-Monarch */
 332 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
 333 /* for weak __pci_target_init() */
 334 #define CONFIG_SYS_PCI_SUBSYS_ID        CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 335 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 336 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 337
 338 /*
 339  * For booting Linux, the board info and command line data
 340  * have to be in the first 8 MB of memory, since this is
 341  * the maximum mapped by the Linux kernel during initialization.
 342  */
 343 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 344
 345 /*-----------------------------------------------------------------------
 346  * FPGA stuff
 347  *----------------------------------------------------------------------*/
 348 #define CONFIG_FPGA
 349 #define CONFIG_FPGA_XILINX
 350 #define CONFIG_FPGA_SPARTAN2
 351 #define CONFIG_FPGA_SPARTAN3
 352
 353 #define CONFIG_FPGA_COUNT       2
 354 /*-----------------------------------------------------------------------
 355  * External Bus Controller (EBC) Setup
 356  *----------------------------------------------------------------------*/
 357
 358 /*
 359  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 360  */
 361 #define CONFIG_SYS_NAND_CS              2       /* NAND chip connected to CSx   */
 362
 363 /* Memory Bank 0 (NOR-FLASH) initialization */
 364 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 365 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 366
 367 /* Memory Bank 2 (NAND-FLASH) initialization */
 368 #define CONFIG_SYS_EBC_PB2AP            0x018003c0
 369 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 370
 371 /* Memory Bank 1 (RESET) initialization */
 372 #define CONFIG_SYS_EBC_PB1AP            0x7f817200 /* 0x03017200 */
 373 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_RESET_BASE | 0x1c000)
 374
 375 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 376 #define CONFIG_SYS_EBC_PB4AP            0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 377 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_FPGA_BASE0 | 0x1c000)       /* BS=1M,BU=R/W,BW=32bit */
 378
 379 /* Memory Bank 5 (FPGA / 16Bit) initialization */
 380 #define CONFIG_SYS_EBC_PB5AP            0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 381 #define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_FPGA_BASE1 | 0x1a000)       /* BS=1M,BU=R/W,BW=16bit */
 382
 383 /*-----------------------------------------------------------------------
 384  * NAND FLASH
 385  *----------------------------------------------------------------------*/
 386 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 387 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 388 #define CONFIG_SYS_NAND_SELECT_DEVICE   1 /* nand driver supports mutipl. chips */
 389
 390 #if defined(CONFIG_CMD_KGDB)
 391 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 392 #endif
 393
 394 #define CONFIG_API              1
 395
 396 #endif /* __CONFIG_H */