include/configs/PMC440.h

   1 /*
   2  * (C) Copyright 2007
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on the sequoia configuration file.
   5  *
   6  * (C) Copyright 2006-2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /************************************************************************
  30  * PMC440.h - configuration for esd PMC440 boards
  31  ***********************************************************************/
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /*-----------------------------------------------------------------------
  36  * High Level Configuration Options
  37  *----------------------------------------------------------------------*/
  38 #define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  39 #define CONFIG_440              1       /* ... PPC440 family    */
  40 #define CONFIG_4xx              1       /* ... PPC4xx family    */
  41
  42 #define CONFIG_SYS_CLK_FREQ     33333400
  43
  44 #define CONFIG_4xx_DCACHE               /* enable dcache        */
  45
  46 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  47 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  48 #define CONFIG_BOARD_TYPES      1       /* support board types  */
  49 /*-----------------------------------------------------------------------
  50  * Base addresses -- Note these are effective addresses where the
  51  * actual resources get mapped (not physical addresses)
  52  *----------------------------------------------------------------------*/
  53 #define CFG_MONITOR_LEN         (384  * 1024)   /* Reserve 384 kB for Monitor   */
  54 #define CFG_MALLOC_LEN          (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  55
  56 #define CONFIG_PRAM             0       /* use pram variable to overwrite */
  57
  58 #define CFG_BOOT_BASE_ADDR      0xf0000000
  59 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  60 #define CFG_FLASH_BASE          0xfc000000      /* start of FLASH       */
  61 #define CFG_MONITOR_BASE        TEXT_BASE
  62 #define CFG_NAND_ADDR           0xd0000000      /* NAND Flash           */
  63 #define CFG_OCM_BASE            0xe0010000      /* ocm                  */
  64 #define CFG_OCM_DATA_ADDR       CFG_OCM_BASE
  65 #define CFG_PCI_BASE            0xe0000000      /* Internal PCI regs    */
  66 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
  67 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  68 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  69 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  70 #define CFG_PCI_MEMSIZE         0x80000000      /* 2GB! */
  71
  72 /* Don't change either of these */
  73 #define CFG_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
  74
  75 #define CFG_USB2D0_BASE         0xe0000100
  76 #define CFG_USB_DEVICE          0xe0000000
  77 #define CFG_USB_HOST            0xe0000400
  78 #define CFG_FPGA_BASE0          0xef000000      /* 32 bit */
  79 #define CFG_FPGA_BASE1          0xef100000      /* 16 bit */
  80
  81 /*-----------------------------------------------------------------------
  82  * Initial RAM & stack pointer
  83  *----------------------------------------------------------------------*/
  84 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  85 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  86 #define CFG_INIT_RAM_END        (4 << 10)
  87 #define CFG_GBL_DATA_SIZE       256     /* num bytes initial data */
  88 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  89 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  90
  91 /*-----------------------------------------------------------------------
  92  * Serial Port
  93  *----------------------------------------------------------------------*/
  94 #undef CFG_EXT_SERIAL_CLOCK
  95 #define CONFIG_BAUDRATE         115200
  96 #define CONFIG_SERIAL_MULTI     1
  97 #undef CONFIG_UART1_CONSOLE     /* console on front panel */
  98
  99 #define CFG_BAUDRATE_TABLE                                              \
 100         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 101
 102 /*-----------------------------------------------------------------------
 103  * Environment
 104  *----------------------------------------------------------------------*/
 105 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 106 #define CFG_ENV_IS_IN_EEPROM    1       /* use FLASH for environment vars */
 107 #else
 108 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environment vars */
 109 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
 110 #endif
 111
 112 /*-----------------------------------------------------------------------
 113  * RTC
 114  *----------------------------------------------------------------------*/
 115 #define CONFIG_RTC_RX8025
 116
 117 /*-----------------------------------------------------------------------
 118  * FLASH related
 119  *----------------------------------------------------------------------*/
 120 #define CFG_FLASH_CFI           /* The flash is CFI compatible  */
 121 #define CFG_FLASH_CFI_DRIVER    /* Use common CFI driver        */
 122
 123 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 124
 125 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 126 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 127
 128 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 129 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 130
 131 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 132 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection        */
 133
 134 #define CFG_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
 135 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 136
 137 #ifdef CFG_ENV_IS_IN_FLASH
 138 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector          */
 139 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 140 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 141
 142 /* Address and size of Redundant Environment Sector     */
 143 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 144 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 145 #endif
 146
 147 #ifdef CFG_ENV_IS_IN_EEPROM
 148 #define CFG_ENV_OFFSET          0       /* environment starts at the beginning of the EEPROM */
 149 #define CFG_ENV_SIZE            0x1000  /* 4096 bytes may be used for env vars */
 150 #endif
 151
 152 /*
 153  * IPL (Initial Program Loader, integrated inside CPU)
 154  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 155  *
 156  * SPL (Secondary Program Loader)
 157  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 158  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 159  * controller and the NAND controller so that the special U-Boot image can be
 160  * loaded from NAND to SDRAM.
 161  *
 162  * NUB (NAND U-Boot)
 163  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 164  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 165  *
 166  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 167  * set up. While still running from cache, I experienced problems accessing
 168  * the NAND controller. sr - 2006-08-25
 169  */
 170 #if defined (CONFIG_NAND_U_BOOT)
 171 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
 172 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
 173 #define CFG_NAND_BOOT_SPL_DST   (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here    */
 174 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
 175 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 176 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 177
 178 /*
 179  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 180  */
 181 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
 182 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
 183
 184 /*
 185  * Now the NAND chip has to be defined (no autodetection used!)
 186  */
 187 #define CFG_NAND_PAGE_SIZE      512     /* NAND chip page size          */
 188 #define CFG_NAND_BLOCK_SIZE     (16 << 10) /* NAND chip block size      */
 189 #define CFG_NAND_PAGE_COUNT     32      /* NAND chip page count         */
 190 #define CFG_NAND_BAD_BLOCK_POS  5       /* Location of bad block marker */
 191 #undef CFG_NAND_4_ADDR_CYCLE            /* No fourth addr used (<=32MB) */
 192
 193 #define CFG_NAND_ECCSIZE        256
 194 #define CFG_NAND_ECCBYTES       3
 195 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 196 #define CFG_NAND_OOBSIZE        16
 197 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 198 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 199 #endif
 200
 201 #ifdef CFG_ENV_IS_IN_NAND
 202 /*
 203  * For NAND booting the environment is embedded in the U-Boot image. Please take
 204  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 205  */
 206 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 207 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 208 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 209 #endif
 210
 211 /*-----------------------------------------------------------------------
 212  * DDR SDRAM
 213  *----------------------------------------------------------------------*/
 214 #define CFG_MBYTES_SDRAM        (256)   /* 256MB                        */
 215 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 216 #define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 217 #endif
 218
 219 /*-----------------------------------------------------------------------
 220  * I2C
 221  *----------------------------------------------------------------------*/
 222 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 223 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged               */
 224 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 225 #define CFG_I2C_SLAVE           0x7F
 226
 227 #define CONFIG_I2C_CMD_TREE     1
 228 #define CONFIG_I2C_MULTI_BUS    1
 229
 230 #define CFG_I2C_MULTI_EEPROMS
 231
 232 #define CFG_I2C_EEPROM_ADDR             0x54
 233 #define CFG_I2C_EEPROM_ADDR_LEN         2
 234 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 235 #define CFG_EEPROM_PAGE_WRITE_BITS      5
 236 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 237 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x01
 238
 239 #define CFG_EEPROM_WREN                 1
 240 #define CFG_I2C_BOOT_EEPROM_ADDR        0x52
 241
 242 /*
 243  * standard dtt sensor configuration - bottom bit will determine local or
 244  * remote sensor of the TMP401
 245  */
 246 #define CONFIG_DTT_SENSORS              { 0, 1 }
 247
 248 /*
 249  * The PMC440 uses a TI TMP401 temperature sensor. This part
 250  * is basically compatible to the ADM1021 that is supported
 251  * by U-Boot.
 252  *
 253  * - i2c addr 0x4c
 254  * - conversion rate 0x02 = 0.25 conversions/second
 255  * - ALERT ouput disabled
 256  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 257  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 258  */
 259 #define CONFIG_DTT_ADM1021
 260 #define CFG_DTT_ADM1021         { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 261
 262 #define CONFIG_PREBOOT          /* enable preboot variable */
 263
 264 #undef  CONFIG_BOOTARGS
 265
 266 /* Setup some board specific values for the default environment variables */
 267 #define CONFIG_HOSTNAME         pmc440
 268 #define CFG_BOOTFILE            "bootfile=/tftpboot/pmc440/uImage\0"
 269 #define CFG_ROOTPATH            "rootpath=/opt/eldk_410/ppc_4xx\0"
 270
 271 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 272         CFG_BOOTFILE                                                    \
 273         CFG_ROOTPATH                                                    \
 274         "netdev=eth0\0"                                                 \
 275         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 276         "nfsroot=${serverip}:${rootpath}\0"                             \
 277         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 278         "addip=setenv bootargs ${bootargs} "                            \
 279         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"              \
 280         ":${hostname}:${netdev}:off panic=1\0"                          \
 281         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 282         "flash_nfs=run nfsargs addip addtty;"                           \
 283         "bootm ${kernel_addr}\0"                                        \
 284         "flash_self=run ramargs addip addtty;"                          \
 285         "bootm ${kernel_addr} ${ramdisk_addr}\0"                        \
 286         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 287         "bootm\0"                                                       \
 288         "kernel_addr=FC000000\0"                                        \
 289         "ramdisk_addr=FC180000\0"                                       \
 290         "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 291         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 292         "cp.b 200000 FFFA0000 60000\0"                                  \
 293         ""
 294
 295 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 296
 297 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 298 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 299
 300 #define CONFIG_IBM_EMAC4_V4     1
 301 #define CONFIG_MII              1       /* MII PHY management           */
 302 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 303
 304 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 305
 306 #define CONFIG_HAS_ETH0
 307 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 308
 309 #define CONFIG_NET_MULTI        1
 310 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 311 #define CONFIG_PHY1_ADDR        1
 312 #define CONFIG_RESET_PHY_R      1
 313
 314 /* USB */
 315 #define CONFIG_USB_OHCI_NEW
 316 #define CONFIG_USB_STORAGE
 317 #define CFG_OHCI_BE_CONTROLLER
 318
 319 #define CFG_USB_OHCI_BOARD_INIT 1
 320 #define CFG_USB_OHCI_CPU_INIT   1
 321 #define CFG_USB_OHCI_REGS_BASE  CFG_USB_HOST
 322 #define CFG_USB_OHCI_SLOT_NAME  "ppc440"
 323 #define CFG_USB_OHCI_MAX_ROOT_PORTS     15
 324
 325 /* Comment this out to enable USB 1.1 device */
 326 #define USB_2_0_DEVICE
 327
 328 /* Partitions */
 329 #define CONFIG_MAC_PARTITION
 330 #define CONFIG_DOS_PARTITION
 331 #define CONFIG_ISO_PARTITION
 332
 333 #include <config_cmd_default.h>
 334
 335 #define CONFIG_CMD_BSP
 336 #define CONFIG_CMD_DATE
 337 #define CONFIG_CMD_ASKENV
 338 #define CONFIG_CMD_DHCP
 339 #define CONFIG_CMD_DTT
 340 #define CONFIG_CMD_DIAG
 341 #define CONFIG_CMD_EEPROM
 342 #define CONFIG_CMD_ELF
 343 #define CONFIG_CMD_FAT
 344 #define CONFIG_CMD_I2C
 345 #define CONFIG_CMD_IRQ
 346 #define CONFIG_CMD_MII
 347 #define CONFIG_CMD_NAND
 348 #define CONFIG_CMD_NET
 349 #define CONFIG_CMD_NFS
 350 #define CONFIG_CMD_PCI
 351 #define CONFIG_CMD_PING
 352 #define CONFIG_CMD_USB
 353 #define CONFIG_CMD_REGINFO
 354 #define CONFIG_CMD_SDRAM
 355
 356 /* POST support */
 357 /* ethernet POST sometimes freezes the CPU.
 358  * So disable it for now until issue is solved
 359  */
 360 #if 0
 361 #define CONFIG_POST             (CFG_POST_MEMORY |      \
 362                                  CFG_POST_CPU    |      \
 363                                  CFG_POST_UART   |      \
 364                                  CFG_POST_I2C    |      \
 365                                  CFG_POST_CACHE  |      \
 366                                  CFG_POST_FPU    |      \
 367                                  CFG_POST_ETHER  |      \
 368                                  CFG_POST_SPR)
 369 #else
 370 #define CONFIG_POST             (CFG_POST_MEMORY |      \
 371                                  CFG_POST_CPU    |      \
 372                                  CFG_POST_UART   |      \
 373                                  CFG_POST_I2C    |      \
 374                                  CFG_POST_CACHE  |      \
 375                                  CFG_POST_FPU    |      \
 376                                  CFG_POST_SPR)
 377 #endif
 378
 379 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 380
 381 /* esd expects pram at end of physical memory.
 382  * So no logbuffer at the moment.
 383  */
 384 #if 0
 385 #define CONFIG_LOGBUFFER
 386 #endif
 387 #define CFG_POST_CACHE_ADDR     0x10000000      /* free virtual address     */
 388
 389 #define CFG_CONSOLE_IS_IN_ENV   /* Otherwise it catches logbuffer as output */
 390
 391 #define CONFIG_SUPPORT_VFAT
 392
 393 /*-----------------------------------------------------------------------
 394  * Miscellaneous configurable options
 395  *----------------------------------------------------------------------*/
 396 #define CFG_LONGHELP                    /* undef to save memory         */
 397 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 398 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 399 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 400 #else
 401 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 402 #endif
 403 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
 404 #define CFG_MAXARGS             16      /* max number of command args   */
 405 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 406
 407 #define CFG_MEMTEST_START       0x0400000       /* memtest works on          */
 408 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM       */
 409
 410 #define CFG_LOAD_ADDR           0x100000        /* default load address      */
 411 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 412
 413 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 414
 415 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 416 #define CONFIG_LOOPW            1       /* enable loopw command         */
 417 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 418 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 419 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 420
 421 #define CONFIG_AUTOBOOT_KEYED   1
 422 #define CONFIG_AUTOBOOT_PROMPT  "Press SPACE to abort autoboot in %d seconds\n"
 423 #undef CONFIG_AUTOBOOT_DELAY_STR
 424 #define CONFIG_AUTOBOOT_STOP_STR " "
 425
 426 /*-----------------------------------------------------------------------
 427  * PCI stuff
 428  *----------------------------------------------------------------------*/
 429 /* General PCI */
 430 #define CONFIG_PCI              /* include pci support          */
 431 #define CONFIG_PCI_PNP          /* do (not) pci plug-and-play   */
 432 #define CFG_PCI_CACHE_LINE_SIZE 0       /* to avoid problems with PNP   */
 433 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 434 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
 435
 436 /* Board-specific PCI */
 437 #define CFG_PCI_TARGET_INIT
 438 #define CFG_PCI_MASTER_INIT
 439
 440 /* PCI identification */
 441 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 442 #define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441     /* PCI Device ID: Non-Monarch */
 443 #define CFG_PCI_SUBSYS_ID_MONARCH 0x0440        /* PCI Device ID: Monarch */
 444 #define CFG_PCI_CLASSCODE_NONMONARCH    PCI_CLASS_PROCESSOR_POWERPC
 445 #define CFG_PCI_CLASSCODE_MONARCH       PCI_CLASS_BRIDGE_HOST
 446
 447 /*
 448  * For booting Linux, the board info and command line data
 449  * have to be in the first 8 MB of memory, since this is
 450  * the maximum mapped by the Linux kernel during initialization.
 451  */
 452 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 453
 454 /*-----------------------------------------------------------------------
 455  * FPGA stuff
 456  *----------------------------------------------------------------------*/
 457 #define CONFIG_FPGA
 458 #define CONFIG_FPGA_XILINX
 459 #define CONFIG_FPGA_SPARTAN2
 460 #define CONFIG_FPGA_SPARTAN3
 461
 462 #define CONFIG_FPGA_COUNT       2
 463 /*-----------------------------------------------------------------------
 464  * External Bus Controller (EBC) Setup
 465  *----------------------------------------------------------------------*/
 466
 467 /*
 468  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 469  */
 470 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 471 #define CFG_NAND_CS             2       /* NAND chip connected to CSx   */
 472
 473 /* Memory Bank 0 (NOR-FLASH) initialization */
 474 #define CFG_EBC_PB0AP           0x03017200
 475 #define CFG_EBC_PB0CR           (CFG_FLASH_BASE | 0xda000)
 476
 477 /* Memory Bank 2 (NAND-FLASH) initialization */
 478 #define CFG_EBC_PB2AP           0x018003c0
 479 #define CFG_EBC_PB2CR           (CFG_NAND_ADDR | 0x1c000)
 480 #else
 481 #define CFG_NAND_CS             0       /* NAND chip connected to CSx   */
 482 /* Memory Bank 2 (NOR-FLASH) initialization */
 483 #define CFG_EBC_PB2AP           0x03017200
 484 #define CFG_EBC_PB2CR           (CFG_FLASH_BASE | 0xda000)
 485
 486 /* Memory Bank 0 (NAND-FLASH) initialization */
 487 #define CFG_EBC_PB0AP           0x018003c0
 488 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1c000)
 489 #endif
 490
 491 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 492 #define CFG_EBC_PB4AP           0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 493 #define CFG_EBC_PB4CR           (CFG_FPGA_BASE0 | 0x1c000)      /* BS=1M,BU=R/W,BW=32bit */
 494
 495 /* Memory Bank 5 (FPGA / 16Bit) initialization */
 496 #define CFG_EBC_PB5AP           0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 497 #define CFG_EBC_PB5CR           (CFG_FPGA_BASE1 | 0x1a000)      /* BS=1M,BU=R/W,BW=16bit */
 498
 499 /*-----------------------------------------------------------------------
 500  * NAND FLASH
 501  *----------------------------------------------------------------------*/
 502 #define CFG_MAX_NAND_DEVICE     1
 503 #define NAND_MAX_CHIPS          1
 504 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 505 #define CFG_NAND_SELECT_DEVICE  1 /* nand driver supports mutipl. chips */
 506 #define CFG_NAND_QUIET_TEST     1
 507
 508 /*
 509  * Internal Definitions
 510  *
 511  * Boot Flags
 512  */
 513 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 514 #define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 515
 516 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 517 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 518 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 519 #endif
 520
 521 /* pass open firmware flat tree */
 522 #define CONFIG_OF_LIBFDT        1
 523 #define CONFIG_OF_BOARD_SETUP   1
 524
 525 #endif /* __CONFIG_H */