include/configs/PMC440.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on the sequoia configuration file.
   5  *
   6  * (C) Copyright 2006-2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /************************************************************************
  30  * PMC440.h - configuration for esd PMC440 boards
  31  ***********************************************************************/
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /*-----------------------------------------------------------------------
  36  * High Level Configuration Options
  37  *----------------------------------------------------------------------*/
  38 #define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  39 #define CONFIG_440              1       /* ... PPC440 family    */
  40 #define CONFIG_4xx              1       /* ... PPC4xx family    */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xFFF90000
  44 #endif
  45
  46 #define CONFIG_SYS_CLK_FREQ     33333400
  47
  48 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */
  49 #define CONFIG_4xx_DCACHE               /* enable dcache        */
  50 #endif
  51
  52 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  53 #define CONFIG_MISC_INIT_F      1
  54 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  55 #define CONFIG_BOARD_TYPES      1       /* support board types  */
  56 /*-----------------------------------------------------------------------
  57  * Base addresses -- Note these are effective addresses where the
  58  * actual resources get mapped (not physical addresses)
  59  *----------------------------------------------------------------------*/
  60 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
  61 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  62
  63 #define CONFIG_PRAM             0       /* use pram variable to overwrite */
  64
  65 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  66 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  67 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  68 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  69 #define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  70 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  71 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  72 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  73 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  74 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  75 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  76 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  77 #define CONFIG_SYS_PCI_MEMSIZE          0x80000000      /* 2GB! */
  78
  79 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  80 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  81 #define CONFIG_SYS_USB_HOST             0xe0000400
  82 #define CONFIG_SYS_FPGA_BASE0           0xef000000      /* 32 bit */
  83 #define CONFIG_SYS_FPGA_BASE1           0xef100000      /* 16 bit */
  84 #define CONFIG_SYS_RESET_BASE           0xef200000
  85
  86 /*-----------------------------------------------------------------------
  87  * Initial RAM & stack pointer
  88  *----------------------------------------------------------------------*/
  89 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  90 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  91 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  92 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  93 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  94
  95 /*-----------------------------------------------------------------------
  96  * Serial Port
  97  *----------------------------------------------------------------------*/
  98 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  99 #define CONFIG_SYS_NS16550
 100 #define CONFIG_SYS_NS16550_SERIAL
 101 #define CONFIG_SYS_NS16550_REG_SIZE     1
 102 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 103 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 104 #define CONFIG_BAUDRATE         115200
 105 #define CONFIG_SERIAL_MULTI     1
 106
 107 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
 108         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 109
 110 /*-----------------------------------------------------------------------
 111  * Environment
 112  *----------------------------------------------------------------------*/
 113 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 114 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use FLASH for environment vars */
 115 #else
 116 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars */
 117 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 118 #endif
 119
 120 /*-----------------------------------------------------------------------
 121  * RTC
 122  *----------------------------------------------------------------------*/
 123 #define CONFIG_RTC_RX8025
 124
 125 /*-----------------------------------------------------------------------
 126  * FLASH related
 127  *----------------------------------------------------------------------*/
 128 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 129 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
 130
 131 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 132
 133 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 134 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 135
 136 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 137 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 138
 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 140 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 141
 142 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 143 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 144
 145 #ifdef CONFIG_ENV_IS_IN_FLASH
 146 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 147 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 148 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 149
 150 /* Address and size of Redundant Environment Sector     */
 151 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 152 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 153 #endif
 154
 155 #ifdef CONFIG_ENV_IS_IN_EEPROM
 156 #define CONFIG_ENV_OFFSET               0       /* environment starts at the beginning of the EEPROM */
 157 #define CONFIG_ENV_SIZE         0x1000  /* 4096 bytes may be used for env vars */
 158 #endif
 159
 160 /*
 161  * IPL (Initial Program Loader, integrated inside CPU)
 162  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 163  *
 164  * SPL (Secondary Program Loader)
 165  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 166  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 167  * controller and the NAND controller so that the special U-Boot image can be
 168  * loaded from NAND to SDRAM.
 169  *
 170  * NUB (NAND U-Boot)
 171  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 172  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 173  *
 174  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 175  * set up. While still running from cache, I experienced problems accessing
 176  * the NAND controller. sr - 2006-08-25
 177  */
 178 #if defined (CONFIG_NAND_U_BOOT)
 179 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 180 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 181 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here    */
 182 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 183 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
 184 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 185
 186 /*
 187  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 188  */
 189 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 190 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 191
 192 /*
 193  * Now the NAND chip has to be defined (no autodetection used!)
 194  */
 195 #define CONFIG_SYS_NAND_PAGE_SIZE       512     /* NAND chip page size          */
 196 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10) /* NAND chip block size      */
 197 #define CONFIG_SYS_NAND_PAGE_COUNT      32      /* NAND chip page count         */
 198 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5       /* Location of bad block marker */
 199 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE             /* No fourth addr used (<=32MB) */
 200
 201 #define CONFIG_SYS_NAND_ECCSIZE 256
 202 #define CONFIG_SYS_NAND_ECCBYTES        3
 203 #define CONFIG_SYS_NAND_OOBSIZE 16
 204 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 205 #endif
 206
 207 #ifdef CONFIG_ENV_IS_IN_NAND
 208 /*
 209  * For NAND booting the environment is embedded in the U-Boot image. Please take
 210  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 211  */
 212 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 213 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 214 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * DDR SDRAM
 219  *----------------------------------------------------------------------*/
 220 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 221 #define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 222 #endif
 223 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
 224                                                   /* 440EPx errata CHIP 11 */
 225
 226 /*-----------------------------------------------------------------------
 227  * I2C
 228  *----------------------------------------------------------------------*/
 229 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 230 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged               */
 231 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 232 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 233 #define CONFIG_SYS_I2C_SLAVE            0x7F
 234
 235 #define CONFIG_I2C_MULTI_BUS    1
 236
 237 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 238
 239 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 240 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 243 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 244
 245 #define CONFIG_SYS_EEPROM_WREN                  1
 246 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 247
 248 /*
 249  * standard dtt sensor configuration - bottom bit will determine local or
 250  * remote sensor of the TMP401
 251  */
 252 #define CONFIG_DTT_SENSORS              { 0, 1 }
 253
 254 /*
 255  * The PMC440 uses a TI TMP401 temperature sensor. This part
 256  * is basically compatible to the ADM1021 that is supported
 257  * by U-Boot.
 258  *
 259  * - i2c addr 0x4c
 260  * - conversion rate 0x02 = 0.25 conversions/second
 261  * - ALERT ouput disabled
 262  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 263  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 264  */
 265 #define CONFIG_DTT_ADM1021
 266 #define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 267
 268 #define CONFIG_PREBOOT          "echo Add \\\"run fpga\\\" and "        \
 269                                 "\\\"painit\\\" to preboot command"
 270
 271 #undef  CONFIG_BOOTARGS
 272
 273 /* Setup some board specific values for the default environment variables */
 274 #define CONFIG_HOSTNAME         pmc440
 275 #define CONFIG_SYS_BOOTFILE     "bootfile=/tftpboot/pmc440/uImage\0"
 276 #define CONFIG_SYS_ROOTPATH     "rootpath=/opt/eldk/ppc_4xxFP\0"
 277
 278 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 279         CONFIG_SYS_BOOTFILE                                             \
 280         CONFIG_SYS_ROOTPATH                                             \
 281         "fdt_file=/tftpboot/pmc440/pmc440.dtb\0"                        \
 282         "netdev=eth0\0"                                                 \
 283         "ethrotate=no\0"                                                \
 284         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 285         "nfsroot=${serverip}:${rootpath}\0"                             \
 286         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 287         "addip=setenv bootargs ${bootargs} "                            \
 288                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 289                 ":${hostname}:${netdev}:off panic=1\0"                  \
 290         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 291         "addmisc=setenv bootargs ${bootargs} mem=${mem}\0"              \
 292         "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 293         "nand_boot_fdt=run nandargs addip addtty addmisc;"              \
 294                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 295         "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"                \
 296                 "tftp  ${fdt_addr_r} ${fdt_file};"                      \
 297                 "run nfsargs addip addtty addmisc;"                     \
 298                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 299         "kernel_addr=ffc00000\0"                                        \
 300         "kernel_addr_r=200000\0"                                        \
 301         "fpga_addr=fff00000\0"                                          \
 302         "fdt_addr=fff80000\0"                                           \
 303         "fdt_addr_r=800000\0"                                           \
 304         "fpga=fpga loadb 0 ${fpga_addr}\0"                              \
 305         "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 306         "update=protect off fff90000 ffffffff;era fff90000 ffffffff;"   \
 307                 "cp.b 200000 fff90000 70000\0"                          \
 308         ""
 309
 310 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 311
 312 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 313 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 314
 315 #define CONFIG_PPC4xx_EMAC
 316 #define CONFIG_IBM_EMAC4_V4     1
 317 #define CONFIG_MII              1       /* MII PHY management           */
 318 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 319
 320 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 321
 322 #define CONFIG_HAS_ETH0
 323 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 324
 325 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 326 #define CONFIG_PHY1_ADDR        1
 327 #define CONFIG_RESET_PHY_R      1
 328
 329 /* USB */
 330 #define CONFIG_USB_OHCI_NEW
 331 #define CONFIG_USB_STORAGE
 332 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 333
 334 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 335 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 336 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 337 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 338 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 339
 340 /* Comment this out to enable USB 1.1 device */
 341 #define USB_2_0_DEVICE
 342
 343 /* Partitions */
 344 #define CONFIG_MAC_PARTITION
 345 #define CONFIG_DOS_PARTITION
 346 #define CONFIG_ISO_PARTITION
 347
 348 #include <config_cmd_default.h>
 349
 350 #define CONFIG_CMD_BSP
 351 #define CONFIG_CMD_DATE
 352 #define CONFIG_CMD_DHCP
 353 #define CONFIG_CMD_DTT
 354 #define CONFIG_CMD_EEPROM
 355 #define CONFIG_CMD_ELF
 356 #define CONFIG_CMD_FAT
 357 #define CONFIG_CMD_I2C
 358 #define CONFIG_CMD_MII
 359 #define CONFIG_CMD_NAND
 360 #define CONFIG_CMD_NET
 361 #define CONFIG_CMD_NFS
 362 #define CONFIG_CMD_PCI
 363 #define CONFIG_CMD_PING
 364 #define CONFIG_CMD_USB
 365 #define CONFIG_CMD_REGINFO
 366
 367 /* POST support */
 368 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY |       \
 369                                  CONFIG_SYS_POST_CPU    |       \
 370                                  CONFIG_SYS_POST_UART   |       \
 371                                  CONFIG_SYS_POST_I2C    |       \
 372                                  CONFIG_SYS_POST_CACHE  |       \
 373                                  CONFIG_SYS_POST_FPU    |       \
 374                                  CONFIG_SYS_POST_ETHER  |       \
 375                                  CONFIG_SYS_POST_SPR)
 376
 377 #define CONFIG_LOGBUFFER
 378 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 379
 380 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 381
 382 #define CONFIG_SUPPORT_VFAT
 383
 384 /*-----------------------------------------------------------------------
 385  * Miscellaneous configurable options
 386  *----------------------------------------------------------------------*/
 387 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 388 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 389 #if defined(CONFIG_CMD_KGDB)
 390 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 391 #else
 392 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 393 #endif
 394 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 395 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 396 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 397
 398 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on          */
 399 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM       */
 400
 401 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address      */
 402 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 403
 404 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 405
 406 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 407 #define CONFIG_LOOPW            1       /* enable loopw command         */
 408 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 409 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 410 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 411
 412 #define CONFIG_AUTOBOOT_KEYED   1
 413 #define CONFIG_AUTOBOOT_PROMPT  \
 414         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 415 #undef CONFIG_AUTOBOOT_DELAY_STR
 416 #define CONFIG_AUTOBOOT_STOP_STR " "
 417
 418 /*-----------------------------------------------------------------------
 419  * PCI stuff
 420  *----------------------------------------------------------------------*/
 421 /* General PCI */
 422 #define CONFIG_PCI              /* include pci support          */
 423 #define CONFIG_PCI_PNP          /* do (not) pci plug-and-play   */
 424 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 425 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 426 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 427
 428 /* Board-specific PCI */
 429 #define CONFIG_SYS_PCI_TARGET_INIT
 430 #define CONFIG_SYS_PCI_MASTER_INIT
 431 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 432
 433 #define CONFIG_PCI_BOOTDELAY 0
 434
 435 /* PCI identification */
 436 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 437 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441      /* PCI Device ID: Non-Monarch */
 438 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
 439 /* for weak __pci_target_init() */
 440 #define CONFIG_SYS_PCI_SUBSYS_ID        CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 441 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 442 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 443
 444 /*
 445  * For booting Linux, the board info and command line data
 446  * have to be in the first 8 MB of memory, since this is
 447  * the maximum mapped by the Linux kernel during initialization.
 448  */
 449 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 450
 451 /*-----------------------------------------------------------------------
 452  * FPGA stuff
 453  *----------------------------------------------------------------------*/
 454 #define CONFIG_FPGA
 455 #define CONFIG_FPGA_XILINX
 456 #define CONFIG_FPGA_SPARTAN2
 457 #define CONFIG_FPGA_SPARTAN3
 458
 459 #define CONFIG_FPGA_COUNT       2
 460 /*-----------------------------------------------------------------------
 461  * External Bus Controller (EBC) Setup
 462  *----------------------------------------------------------------------*/
 463
 464 /*
 465  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 466  */
 467 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 468 #define CONFIG_SYS_NAND_CS              2       /* NAND chip connected to CSx   */
 469
 470 /* Memory Bank 0 (NOR-FLASH) initialization */
 471 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 472 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 473
 474 /* Memory Bank 2 (NAND-FLASH) initialization */
 475 #define CONFIG_SYS_EBC_PB2AP            0x018003c0
 476 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 477 #else
 478 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 479 /* Memory Bank 2 (NOR-FLASH) initialization */
 480 #define CONFIG_SYS_EBC_PB2AP            0x03017200
 481 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 482
 483 /* Memory Bank 0 (NAND-FLASH) initialization */
 484 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 485 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 486 #endif
 487
 488 /* Memory Bank 1 (RESET) initialization */
 489 #define CONFIG_SYS_EBC_PB1AP            0x7f817200 /* 0x03017200 */
 490 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_RESET_BASE | 0x1c000)
 491
 492 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 493 #define CONFIG_SYS_EBC_PB4AP            0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 494 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_FPGA_BASE0 | 0x1c000)       /* BS=1M,BU=R/W,BW=32bit */
 495
 496 /* Memory Bank 5 (FPGA / 16Bit) initialization */
 497 #define CONFIG_SYS_EBC_PB5AP            0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 498 #define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_FPGA_BASE1 | 0x1a000)       /* BS=1M,BU=R/W,BW=16bit */
 499
 500 /*-----------------------------------------------------------------------
 501  * NAND FLASH
 502  *----------------------------------------------------------------------*/
 503 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 504 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 505 #define CONFIG_SYS_NAND_SELECT_DEVICE   1 /* nand driver supports mutipl. chips */
 506 #define CONFIG_SYS_NAND_QUIET_TEST      1
 507
 508 #if defined(CONFIG_CMD_KGDB)
 509 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 510 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 511 #endif
 512
 513 /* pass open firmware flat tree */
 514 #define CONFIG_OF_LIBFDT        1
 515 #define CONFIG_OF_BOARD_SETUP   1
 516
 517 #define CONFIG_API              1
 518
 519 #endif /* __CONFIG_H */