include/configs/QS860T.h

   1 /*
   2  * (C) Copyright 2003
   3  * MuLogic B.V.
   4  *
   5  * (C) Copyright 2002
   6  * Simple Network Magic Corporation
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /*
  15  * board/config.h - configuration options, board specific
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /* various debug settings */
  22 #undef CONFIG_SYS_DEVICE_NULLDEV                /* null device */
  23 #undef CONFIG_SILENT_CONSOLE            /* silent console */
  24 #undef CONFIG_SYS_CONSOLE_INFO_QUIET            /* silent console ? */
  25 #undef DEBUG_FLASH                      /* debug flash code */
  26 #undef FLASH_DEBUG                      /* debug fash code */
  27 #undef DEBUG_ENV                        /* debug environment code */
  28
  29 #define CONFIG_SYS_DIRECT_FLASH_TFTP    1       /* allow direct tftp to flash */
  30 #define CONFIG_ENV_OVERWRITE    1       /* allow overwrite MAC address */
  31
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC860           1       /* This is a MPC860 CPU */
  39 #define CONFIG_QS860T           1       /* ...on a QS860T module */
  40
  41 /* Start address of 512K Socketed Flash */
  42 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  43
  44 #define CONFIG_FEC_ENET         1       /* FEC 10/100BaseT ethernet */
  45 #define CONFIG_MII
  46 #define FEC_INTERRUPT           SIU_LEVEL1
  47 #undef CONFIG_SCC1_ENET                 /* SCC1 10BaseT ethernet */
  48 #define CONFIG_SYS_DISCOVER_PHY
  49
  50 #undef CONFIG_8xx_CONS_SMC1
  51 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC */
  52 #undef CONFIG_8xx_CONS_NONE
  53
  54 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps */
  55
  56 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  57
  58 /* Pass clocks to Linux 2.4.18 in Hz */
  59 #undef CONFIG_CLOCKS_IN_MHZ             /* clocks passsed to Linux in MHz */
  60
  61 #define CONFIG_PREBOOT          "echo;" \
  62         "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \
  63         "echo"
  64
  65 #undef CONFIG_BOOTARGS
  66 /* TODO compare against CADM860 */
  67 #define CONFIG_BOOTCOMMAND      "bootp; " \
  68         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  69         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  70         "bootm"
  71
  72 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
  73 #undef CONFIG_SYS_LOADS_BAUD_CHANGE             /* don't allow baudrate change */
  74
  75 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
  76
  77 #undef CONFIG_STATUS_LED                /* Status LED disabled */
  78
  79 #undef CONFIG_CAN_DRIVER                /* CAN Driver support disabled */
  80
  81 /*
  82  * BOOTP options
  83  */
  84 #define CONFIG_BOOTP_SUBNETMASK
  85 #define CONFIG_BOOTP_GATEWAY
  86 #define CONFIG_BOOTP_HOSTNAME
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_BOOTFILESIZE
  89
  90
  91 #define CONFIG_MAC_PARTITION
  92 #define CONFIG_DOS_PARTITION
  93
  94 #define CONFIG_RTC_MPC8xx       /* use internal RTC of MPC8xx */
  95
  96
  97 /*
  98  * Command line configuration.
  99  */
 100 #include <config_cmd_default.h>
 101
 102 #define CONFIG_CMD_REGINFO
 103 #define CONFIG_CMD_IMMAP
 104 #define CONFIG_CMD_ASKENV
 105 #define CONFIG_CMD_NET
 106 #define CONFIG_CMD_DHCP
 107 #define CONFIG_CMD_DATE
 108
 109
 110 /* TODO */
 111 #if 0
 112 /* Look at these */
 113 CONFIG_IPADDR
 114 CONFIG_SERVERIP
 115 CONFIG_I2C
 116 CONFIG_SPI
 117 #endif
 118
 119 /*
 120  * Environment variable storage is in NVRAM
 121  */
 122 #define CONFIG_ENV_IS_IN_NVRAM  1
 123 #define CONFIG_ENV_SIZE         0x00001000      /* We use only the last 4K for PPCBoot */
 124 #define CONFIG_ENV_ADDR         0xD100E000
 125
 126 /*
 127  * Miscellaneous configurable options
 128  */
 129 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 130 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 131
 132 #define CONFIG_SYS_HUSH_PARSER          1               /* use "hush" command parser */
 133
 134 #if defined(CONFIG_CMD_KGDB)
 135 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size */
 136 #else
 137 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size */
 138 #endif
 139 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 140 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 141 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 142
 143 /* TODO - size? */
 144 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works */
 145 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM */
 146
 147 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 148
 149 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 150
 151 /*-----------------------------------------------------------------------
 152  * Low Level Configuration Settings
 153  * (address mappings, register initial values, etc.)
 154  * You should know what you are doing if you make changes here.
 155  */
 156 /*-----------------------------------------------------------------------
 157  * Internal Memory Mapped Register
 158  */
 159 #define CONFIG_SYS_IMMR         0xF0000000
 160
 161 /*-----------------------------------------------------------------------
 162  * Definitions for initial stack pointer and data area (in DPRAM)
 163  */
 164 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 165 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00          /* Size of used area in DPRAM */
 166 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 167 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 168
 169 /*-----------------------------------------------------------------------
 170  * Start addresses for the final memory configuration
 171  * (Set up by the startup code)
 172  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 173  */
 174 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 175 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
 176
 177 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 179 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 180
 181 /*
 182  * For booting Linux, the board info and command line data
 183  * have to be in the first 8 MB of memory, since this is
 184  * the maximum mapped by the Linux kernel during initialization.
 185  */
 186 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 187
 188 /* TODO flash parameters */
 189 /*-----------------------------------------------------------------------
 190  * FLASH organization for Intel Strataflash
 191  */
 192 #define CONFIG_SYS_FLASH_16BIT          1               /* 16-bit wide flash memory */
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* max number of memory banks */
 194 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* max number of sectors on one chip */
 195
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000          /* Timeout for Flash Erase (in ms) */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout for Flash Write (in ms) */
 198
 199 #undef  CONFIG_ENV_IS_IN_FLASH
 200
 201 /*-----------------------------------------------------------------------
 202  * Cache Configuration
 203  */
 204 #define CONFIG_SYS_CACHELINE_SIZE       16              /* For all MPC8xx CPUs */
 205 #if defined(CONFIG_CMD_KGDB)
 206 #define CONFIG_SYS_CACHELINE_SHIFT      4               /* log base 2 of the above value */
 207 #endif
 208
 209 /*-----------------------------------------------------------------------
 210  * SYPCR - System Protection Control 11-9
 211  * SYPCR can only be written once after reset!
 212  *-----------------------------------------------------------------------
 213  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 214  */
 215 #if defined(CONFIG_WATCHDOG)
 216 #define CONFIG_SYS_SYPCR        (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
 217 #else
 218 #define CONFIG_SYS_SYPCR        0xFFFFFF88
 219 #endif
 220
 221 /*-----------------------------------------------------------------------
 222  * SIUMCR - SIU Module Configuration 11-6
 223  *-----------------------------------------------------------------------
 224  */
 225 #define CONFIG_SYS_SIUMCR       0x00620000
 226
 227 /*-----------------------------------------------------------------------
 228  * TBSCR - Time Base Status and Control 11-26
 229  *-----------------------------------------------------------------------
 230  */
 231 #define CONFIG_SYS_TBSCR        0x00C3
 232
 233 /*-----------------------------------------------------------------------
 234  * RTCSC - Real-Time Clock Status and Control Register 11-27
 235  *-----------------------------------------------------------------------
 236  */
 237 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 238
 239 /*-----------------------------------------------------------------------
 240  * PISCR - Periodic Interrupt Status and Control 11-31
 241  *-----------------------------------------------------------------------
 242  */
 243 #define CONFIG_SYS_PISCR        0x0082
 244
 245 /*-----------------------------------------------------------------------
 246  * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
 247  *-----------------------------------------------------------------------
 248  */
 249 #define CONFIG_SYS_PLPRCR       0x0090D000
 250
 251 /*-----------------------------------------------------------------------
 252  * SCCR - System Clock and reset Control Register               15-27
 253  *-----------------------------------------------------------------------
 254  */
 255 #define SCCR_MASK       SCCR_EBDF11
 256 #define CONFIG_SYS_SCCR 0x02000000
 257
 258
 259 /*-----------------------------------------------------------------------
 260  * Debug Enable Register
 261  * 0x73E67C0F - All interrupts handled by BDM
 262  * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
 263  *-----------------------------------------------------------------------
 264 #define CONFIG_SYS_DER                  0x73E67C0F
 265 */
 266 #define CONFIG_SYS_DER                  0x0082400F
 267
 268
 269 /*-----------------------------------------------------------------------
 270  * Memory Controller Initialization Constants
 271  *-----------------------------------------------------------------------
 272  */
 273
 274 /*
 275  * BR0 and OR0 (AMD 512K Socketed FLASH)
 276  * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
 277  */
 278 #define CONFIG_SYS_PRELIM_OR_AM
 279 #define CONFIG_SYS_OR_TIMING_FLASH
 280
 281 #define FLASH_BASE0_PRELIM      0xFFF00001
 282 #define CONFIG_SYS_OR0_PRELIM           0xFFF80D42
 283 #define CONFIG_SYS_BR0_PRELIM           0xFFF00401
 284
 285
 286 /*
 287  * BR1 and OR1 (Intel 8M StrataFLASH)
 288  * Base address = 0xD000_0000 - 0xD07F_FFFF
 289  */
 290
 291 #define FLASH_BASE1_PRELIM      0xD0000000
 292 #define CONFIG_SYS_OR1_PRELIM           0xFF800D42
 293 #define CONFIG_SYS_BR1_PRELIM           0xD0000801
 294 /* #define CONFIG_SYS_OR1               0xFF800D42 */
 295 /* #define CONFIG_SYS_BR1               0xD0000801 */
 296
 297
 298 /*
 299  * BR2 and OR2 (SDRAM)
 300  * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
 301  * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
 302  * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
 303  *
 304  */
 305 #define SDRAM_BASE              0x00000000      /* SDRAM bank */
 306 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 307
 308 /* SDRAM timing */
 309 #define SDRAM_TIMING            0x00000A00
 310
 311 /* For boards with 16M of SDRAM */
 312 #define SDRAM_16M_MAX_SIZE      0x01000000      /* max 16MB SDRAM */
 313 #define CONFIG_SYS_16M_MBMR             0x18802114      /* Mem Periodic Timer Prescaler */
 314
 315 /* For boards with 64M of SDRAM */
 316 #define SDRAM_64M_MAX_SIZE      0x04000000      /* max 64MB SDRAM */
 317 /* TODO - determine real value */
 318 #define CONFIG_SYS_64M_MBMR             0x18802114      /* Mem Period Timer Prescaler */
 319
 320 #define CONFIG_SYS_OR2                  (SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
 321 #define CONFIG_SYS_BR2                  (SDRAM_BASE | 0x000000C1)
 322
 323
 324 /*
 325  * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
 326  * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
 327  * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
 328  * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
 329  * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
 330  *
 331  */
 332
 333 #define CONFIG_SYS_OR3_PRELIM           0xFFC00DF6
 334 #define CONFIG_SYS_BR3_PRELIM           0xD1000401
 335 /* #define CONFIG_SYS_OR3               0xFFC00DF6 */
 336 /* #define CONFIG_SYS_BR3               0xD1000401 */
 337
 338
 339 /*
 340  * BR4 and OR4 (Unused)
 341  * Base address = 0xE000_0000 - 0xE3FF_FFFF
 342  *
 343  */
 344
 345 #define CONFIG_SYS_OR4_PRELIM           0xFF000000
 346 #define CONFIG_SYS_BR4_PRELIM           0xE0000000
 347 /* #define CONFIG_SYS_OR4               0xFF000000 */
 348 /* #define CONFIG_SYS_BR4               0xE0000000 */
 349
 350
 351 /*
 352  * BR5 and OR5 (Expansion bus)
 353  * Base address = 0xE400_0000 - 0xE7FF_FFFF
 354  *
 355  */
 356
 357 #define CONFIG_SYS_OR5_PRELIM           0xFF000000
 358 #define CONFIG_SYS_BR5_PRELIM           0xE4000000
 359 /* #define CONFIG_SYS_OR5               0xFF000000 */
 360 /* #define CONFIG_SYS_BR5               0xE4000000 */
 361
 362
 363 /*
 364  * BR6 and OR6 (Expansion bus)
 365  * Base address = 0xE800_0000 - 0xEBFF_FFFF
 366  *
 367  */
 368
 369 #define CONFIG_SYS_OR6_PRELIM           0xFF000000
 370 #define CONFIG_SYS_BR6_PRELIM           0xE8000000
 371 /* #define CONFIG_SYS_OR6               0xFF000000 */
 372 /* #define CONFIG_SYS_BR6               0xE8000000 */
 373
 374
 375 /*
 376  * BR7 and OR7 (Expansion bus)
 377  * Base address = 0xEC00_0000 - 0xEFFF_FFFF
 378  *
 379  */
 380
 381 #define CONFIG_SYS_OR7_PRELIM           0xFF000000
 382 #define CONFIG_SYS_BR7_PRELIM           0xE8000000
 383 /* #define CONFIG_SYS_OR7               0xFF000000 */
 384 /* #define CONFIG_SYS_BR7               0xE8000000 */
 385
 386 /*
 387  * Sanity checks
 388  */
 389 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 390 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 391 #endif
 392
 393 #endif /* __CONFIG_H */