include/configs/RPXlite_DW.h

   1 /*
   2  * (C) Copyright 2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  14  * U-BOOT port on RPXlite board
  15  */
  16
  17 /*
  18  * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
  19  * U-BOOT port on RPXlite DW version board--RPXlite_DW
  20  * June 8 ,2004
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * High Level Configuration Options
  28  * (easy to change)
  29  */
  30
  31 /* #define DEBUG        1 */
  32 /* #define DEPLOYMENT   1 */
  33
  34 #undef  CONFIG_MPC860
  35 #define CONFIG_MPC823           1       /* This is a MPC823e CPU. */
  36 #define CONFIG_RPXLITE          1       /* RPXlite DW version board */
  37
  38 #define CONFIG_SYS_TEXT_BASE    0xff000000
  39
  40 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  41 #define CONFIG_MPC8XX_LCD
  42 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  43 #endif
  44
  45 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  46 #undef  CONFIG_8xx_CONS_SMC2
  47 #undef  CONFIG_8xx_CONS_NONE
  48 #define CONFIG_BAUDRATE         9600    /* console default baudrate = 9600bps   */
  49
  50 #ifdef DEBUG
  51 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  52 #else
  53 #define CONFIG_BOOTDELAY        6       /* autoboot after 6 seconds     */
  54
  55 #ifdef DEPLOYMENT
  56 #define CONFIG_BOOT_RETRY_TIME          -1
  57 #define CONFIG_AUTOBOOT_KEYED
  58 #define CONFIG_AUTOBOOT_PROMPT          \
  59         "autoboot in %d seconds (stop with 'st')...\n", bootdelay
  60 #define CONFIG_AUTOBOOT_STOP_STR        "st"
  61 #define CONFIG_ZERO_BOOTDELAY_CHECK
  62 #define CONFIG_RESET_TO_RETRY           1
  63 #define CONFIG_BOOT_RETRY_MIN           1
  64 #endif  /* DEPLOYMENT */
  65 #endif  /* DEBUG */
  66
  67 /* pre-boot commands */
  68 #define CONFIG_PREBOOT          "setenv stdout serial;setenv stdin serial"
  69
  70 #undef  CONFIG_BOOTARGS
  71 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  72         "netdev=eth0\0"                                                 \
  73         "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 "      \
  74                 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
  75         "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0"       \
  76         "addip=setenv bootargs ${bootargs} "                            \
  77                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  78                 ":${hostname}:${netdev}:off panic=1\0"                  \
  79         "flash_nfs=run nfsargs addip;"                                  \
  80                 "bootm ${kernel_addr}\0"                                \
  81         "flash_self=run ramargs addip;"                                 \
  82                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  83         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  84         "gatewayip=172.16.115.254\0"                                    \
  85         "netmask=255.255.255.0\0"                                       \
  86         "kernel_addr=ff040000\0"                                        \
  87         "ramdisk_addr=ff200000\0"                                       \
  88         "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} "    \
  89                 "${filesize};md ${kernel_addr};"                        \
  90                 "echo kernel updating finished\0"                       \
  91         "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 "          \
  92                 "${filesize};md ff000000;"                              \
  93                 "echo u-boot updating finished\0"                       \
  94         "eu=protect off 1:6;era 1:6;reset\0"                            \
  95         "lcd=setenv stdout lcd;setenv stdin lcd\0"                      \
  96         "ser=setenv stdout serial;setenv stdin serial\0"                \
  97         "verify=no"
  98
  99 #define CONFIG_BOOTCOMMAND      "run flash_self"
 100
 101 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 102 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 103 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 104 #undef  CONFIG_STATUS_LED               /* disturbs display. Status LED disabled. */
 105
 106 /*
 107  * BOOTP options
 108  */
 109 #define CONFIG_BOOTP_SUBNETMASK
 110 #define CONFIG_BOOTP_GATEWAY
 111 #define CONFIG_BOOTP_HOSTNAME
 112 #define CONFIG_BOOTP_BOOTPATH
 113 #define CONFIG_BOOTP_BOOTFILESIZE
 114
 115
 116 #if 1          /* Enable this stuff could make image enlarge about 25KB. Mask it if you
 117                   don't want the advanced function */
 118
 119
 120 /*
 121  * Command line configuration.
 122  */
 123 #include <config_cmd_default.h>
 124
 125 #define CONFIG_CMD_ASKENV
 126 #define CONFIG_CMD_JFFS2
 127 #define CONFIG_CMD_PING
 128 #define CONFIG_CMD_ELF
 129 #define CONFIG_CMD_REGINFO
 130 #define CONFIG_CMD_DHCP
 131
 132 #ifdef  CONFIG_SPLASH_SCREEN
 133 #define CONFIG_CMD_BMP
 134 #endif
 135
 136
 137 /* test-only */
 138 #define CONFIG_SYS_JFFS2_FIRST_BANK     0           /* use for JFFS2 */
 139 #define CONFIG_SYS_JFFS2_NUM_BANKS      1           /* ! second bank contains U-Boot */
 140
 141 #define CONFIG_NETCONSOLE
 142
 143 #endif  /* 1 */
 144
 145 /*
 146  * Miscellaneous configurable options
 147  */
 148 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 149 #define CONFIG_SYS_PROMPT       "u-boot>"       /* Monitor Command Prompt   */
 150
 151 #if defined(CONFIG_CMD_KGDB)
 152 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 153 #else
 154 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 155 #endif
 156
 157 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 158 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 159 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 160
 161 #define CONFIG_SYS_MEMTEST_START        0x0040000       /* memtest works on     */
 162 #define CONFIG_SYS_MEMTEST_END          0x00C0000       /* 4 ... 12 MB in DRAM  */
 163 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 164
 165 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 166
 167 /*
 168  * Low Level Configuration Settings
 169  * (address mappings, register initial values, etc.)
 170  * You should know what you are doing if you make changes here.
 171  */
 172 /*-----------------------------------------------------------------------
 173  * Internal Memory Mapped Register
 174  */
 175 #define CONFIG_SYS_IMMR         0xFA200000
 176
 177 /*-----------------------------------------------------------------------
 178  * Definitions for initial stack pointer and data area (in DPRAM)
 179  */
 180 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00          /* Size of used area in DPRAM   */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 183 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 184
 185 /*-----------------------------------------------------------------------
 186  * Start addresses for the final memory configuration
 187  * (Set up by the startup code)
 188  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 189  */
 190 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 191 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 192
 193 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 195 #else
 196 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor */
 197 #endif
 198
 199 #define CONFIG_SYS_MONITOR_BASE 0xFF000000
 200 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 201
 202 /*
 203  * For booting Linux, the board info and command line data
 204  * have to be in the first 8 MB of memory, since this is
 205  * the maximum mapped by the Linux kernel during initialization.
 206  */
 207 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 208
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 213 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip    */
 214 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 215 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 216
 217 #ifdef  CONFIG_ENV_IS_IN_NVRAM
 218 #define CONFIG_ENV_ADDR         0xFA000100
 219 #define CONFIG_ENV_SIZE         0x1000
 220 #else
 221 #define CONFIG_ENV_IS_IN_FLASH
 222 #define CONFIG_ENV_OFFSET               0x30000 /* Offset of Environment Sector         */
 223 #define CONFIG_ENV_SIZE         0x8000  /* Total Size of Environment Sector     */
 224 #endif  /* CONFIG_ENV_IS_IN_NVRAM */
 225
 226 #define CONFIG_SYS_RESET_ADDRESS        ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
 227
 228 /*-----------------------------------------------------------------------
 229  * Cache Configuration
 230  */
 231 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 232 #if defined(CONFIG_CMD_KGDB)
 233 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 234 #endif
 235
 236 /*-----------------------------------------------------------------------
 237  * SYPCR - System Protection Control    32-bit                  12-35
 238  * SYPCR can only be written once after reset!
 239  *-----------------------------------------------------------------------
 240  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 241  */
 242 #if defined(CONFIG_WATCHDOG)
 243 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 244                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 245 #else
 246 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 247 #endif  /* We can get SYPCR: 0xFFFF0689. */
 248
 249 /*-----------------------------------------------------------------------
 250  * SIUMCR - SIU Module Configuration    32-bit                   12-30
 251  *-----------------------------------------------------------------------
 252  * PCMCIA config., multi-function pin tri-state
 253  */
 254 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC10)        /* SIUMCR:0x00000800 */
 255
 256 /*---------------------------------------------------------------------
 257  * TBSCR - Time Base Status and Control  16-bit                  12-16
 258  *---------------------------------------------------------------------
 259  * Clear Reference Interrupt Status, Timebase freezing enabled
 260  */
 261 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 262 /* TBSCR: 0x00C3 [SAM] */
 263
 264 /*-----------------------------------------------------------------------
 265  * RTCSC - Real-Time Clock Status and Control Register 16-bit    12-18
 266  *-----------------------------------------------------------------------
 267  * [RTC enabled but not stopped on FRZ]
 268  */
 269 #define CONFIG_SYS_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
 270
 271 /*-----------------------------------------------------------------------
 272  * PISCR - Periodic Interrupt Status and Control 16-bit          12-23
 273  *-----------------------------------------------------------------------
 274  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 275  * [Periodic timer enabled,Periodic timer interrupt disable. ]
 276  */
 277 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083           */
 278
 279 /*-----------------------------------------------------------------------
 280  * PLPRCR - PLL, Low-Power, and Reset Control Register  32-bit   5-7
 281  *-----------------------------------------------------------------------
 282  * Reset PLL lock status sticky bit, timer expired status bit and timer
 283  * interrupt status bit
 284  */
 285 /* up to 64 MHz we use a 1:2 clock */
 286 #if defined(RPXlite_64MHz)
 287 #define CONFIG_SYS_PLPRCR       ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
 288 #else
 289 #define CONFIG_SYS_PLPRCR       ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 290 #endif
 291
 292 /*-----------------------------------------------------------------------
 293  * SCCR - System Clock and reset Control Register               5-3
 294  *-----------------------------------------------------------------------
 295  * Set clock output, timebase and RTC source and divider,
 296  * power management and some other internal clocks
 297  */
 298 #define SCCR_MASK       SCCR_EBDF00
 299 /* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
 300 #if defined(RPXlite_64MHz)
 301 #define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
 302 #else
 303 #define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
 304 #endif
 305
 306 /*-----------------------------------------------------------------------
 307  * PCMCIA stuff
 308  *-----------------------------------------------------------------------
 309  */
 310 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 311 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 312 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 313 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 314 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 315 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 316 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 317 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 318
 319 /*-----------------------------------------------------------------------
 320  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 321  *-----------------------------------------------------------------------
 322  */
 323 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 324 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 325
 326 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 327 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 328 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 329
 330 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 331 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 332
 333 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 334 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 335
 336 /* Offset for data I/O                  */
 337 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 338
 339 /* Offset for normal register accesses  */
 340 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 341
 342 /* Offset for alternate registers       */
 343 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 344
 345 #define         CONFIG_SYS_DER          0
 346
 347 /*
 348  * Init Memory Controller:
 349  *
 350  * BR0 and OR0 (FLASH)
 351  */
 352 #define FLASH_BASE_PRELIM       0xFC000000      /* FLASH base   */
 353 #define CONFIG_SYS_PRELIM_OR_AM 0xFC000000      /* OR addr mask */
 354
 355 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
 356 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
 357 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 358 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 359
 360 /*
 361  * BR1 and OR1 (SDRAM)
 362  *
 363  */
 364 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 365 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB in system */
 366
 367 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 368 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000E00
 369 #define CONFIG_SYS_OR_AM_SDRAM          (-(SDRAM_MAX_SIZE & OR_AM_MSK))
 370 #define CONFIG_SYS_OR1_PRELIM   ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM )
 371 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 372
 373 /* RPXlite mem setting */
 374 #define CONFIG_SYS_BR3_PRELIM   0xFA400001              /* BCSR */
 375 #define CONFIG_SYS_OR3_PRELIM   0xFF7F8900
 376 #define CONFIG_SYS_BR4_PRELIM   0xFA000401              /* NVRAM&SRAM */
 377 #define CONFIG_SYS_OR4_PRELIM   0xFFFE0040
 378
 379 /*
 380  * Memory Periodic Timer Prescaler
 381  */
 382 /* periodic timer for refresh */
 383 #if defined(RPXlite_64MHz)
 384 #define CONFIG_SYS_MAMR_PTA     32
 385 #else
 386 #define CONFIG_SYS_MAMR_PTA     20
 387 #endif
 388
 389 /*
 390  * Refresh clock Prescalar
 391  */
 392 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV2
 393
 394 /*
 395  * MAMR settings for SDRAM
 396  */
 397
 398 /* 9 column SDRAM */
 399 #define CONFIG_SYS_MAMR_9COL  ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 400                         MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
 401 /* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
 402
 403 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 404 /* Configuration variable added by yooth. */
 405 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 406 /*
 407  * BCSRx
 408  *
 409  * Board Status and Control Registers
 410  *
 411  */
 412 #define BCSR0 0xFA400000
 413 #define BCSR1 0xFA400001
 414 #define BCSR2 0xFA400002
 415 #define BCSR3 0xFA400003
 416
 417 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 418 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 419 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 420 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 421 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 422 #define BCSR0_COLTEST   0x20
 423 #define BCSR0_ETHLPBK   0x40
 424 #define BCSR0_ETHEN     0x80
 425
 426 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 427 #define BCSR1_PCVCTL6   0x02
 428 #define BCSR1_PCVCTL5   0x04
 429 #define BCSR1_PCVCTL4   0x08
 430 #define BCSR1_IPB5SEL   0x10
 431
 432 #define BCSR1_SMC1CTS   0x40    /* Added by SAM. */
 433 #define BCSR1_SMC1TRS   0x80    /* Added by SAM. */
 434
 435 #define BCSR2_ENRTCIRQ  0x01    /* Added by SAM. */
 436 #define BCSR2_ENBRG1    0x04    /* Added by SAM. */
 437
 438 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 439 #define BCSR2_ENUSBCLK  0x10
 440 #define BCSR2_USBPWREN  0x20
 441 #define BCSR2_USBSPD    0x40
 442 #define BCSR2_USBSUSP   0x80
 443
 444 #define BCSR3_BWKAPWR   0x01   /* Changed by SAM. Backup battery situation */
 445 #define BCSR3_IRQRTC    0x02   /* Changed by SAM. NVRAM Battery */
 446 #define BCSR3_RDY_BSY   0x04   /* Changed by SAM. Flash Operation */
 447 #define BCSR3_MPLX_LIN  0x08   /* Changed by SAM. Linear or Multiplexed address Mode */
 448
 449 #define BCSR3_D27       0x10      /* Dip Switch settings */
 450 #define BCSR3_D26       0x20
 451 #define BCSR3_D25       0x40
 452 #define BCSR3_D24       0x80
 453
 454 /*
 455  * Environment setting
 456  */
 457 #define CONFIG_ETHADDR  00:10:EC:00:37:5B
 458 #define CONFIG_IPADDR   172.16.115.7
 459 #define CONFIG_SERVERIP 172.16.115.6
 460 #define CONFIG_ROOTPATH "/workspace/myfilesystem/target/"
 461 #define CONFIG_BOOTFILE "uImage.rpxusb"
 462 #define CONFIG_HOSTNAME LITE_H1_DW
 463
 464 #endif  /* __CONFIG_H */