include/configs/SL8245.h

   1 /*
   2  * (C) Copyright 2001 - 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25 /*
  26  * Configuration settings for the SL8245 board.
  27  */
  28
  29 /* ------------------------------------------------------------------------- */
  30
  31 /*
  32  * board/config.h - configuration options, board specific
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42
  43 #define CONFIG_MPC824X          1
  44 #define CONFIG_MPC8245          1
  45 #define CONFIG_SL8245           1
  46
  47
  48 #define CONFIG_CONS_INDEX       1
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  51
  52 #define CONFIG_BOOTDELAY        5
  53
  54 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  55
  56
  57 /*
  58  * BOOTP options
  59  */
  60 #define CONFIG_BOOTP_BOOTFILESIZE
  61 #define CONFIG_BOOTP_BOOTPATH
  62 #define CONFIG_BOOTP_GATEWAY
  63 #define CONFIG_BOOTP_HOSTNAME
  64
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #include <config_cmd_default.h>
  70
  71 #define CONFIG_CMD_PCI
  72
  73
  74 /*
  75  * Miscellaneous configurable options
  76  */
  77 #undef CONFIG_SYS_LONGHELP                      /* undef to save memory         */
  78 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  79 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  80
  81 /* Print Buffer Size
  82  */
  83 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  84 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args   */
  85 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  86 #define CONFIG_SYS_LOAD_ADDR    0x00400000      /* Default load address         */
  87
  88 /*-----------------------------------------------------------------------
  89  * Start addresses for the final memory configuration
  90  * (Set up by the startup code)
  91  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  92  */
  93 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  94
  95 #define CONFIG_SYS_FLASH_BASE0_PRELIM   0xFF800000      /* FLASH bank on RCS#0 */
  96 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH_BASE0_PRELIM
  97 #define CONFIG_SYS_FLASH_BANKS          { CONFIG_SYS_FLASH_BASE0_PRELIM }
  98
  99 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 100
 101 #define CONFIG_SYS_EUMB_ADDR        0xFC000000
 102
 103 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 104 #define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 105 #define CONFIG_SYS_MALLOC_LEN       (128 << 10) /* Reserve 128 kB for malloc()  */
 106
 107 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on             */
 108 #define CONFIG_SYS_MEMTEST_END      0x02000000  /* 0 ... 32 MB in DRAM          */
 109
 110         /* Maximum amount of RAM.
 111          */
 112 #define CONFIG_SYS_MAX_RAM_SIZE    0x10000000   /* 0 .. 256 MB of (S)DRAM */
 113
 114
 115 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 116 #undef CONFIG_SYS_RAMBOOT
 117 #else
 118 #define CONFIG_SYS_RAMBOOT
 119 #endif
 120
 121 /*
 122  * NS16550 Configuration
 123  */
 124 #define CONFIG_SYS_NS16550
 125 #define CONFIG_SYS_NS16550_SERIAL
 126
 127 #define CONFIG_SYS_NS16550_REG_SIZE     1
 128
 129 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 130
 131 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 132
 133 /*-----------------------------------------------------------------------
 134  * Definitions for initial stack pointer and data area
 135  */
 136
 137 #define CONFIG_SYS_GBL_DATA_SIZE      128
 138 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 139 #define CONFIG_SYS_INIT_RAM_END      0x1000
 140 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 141
 142 /*
 143  * Low Level Configuration Settings
 144  * (address mappings, register initial values, etc.)
 145  * You should know what you are doing if you make changes here.
 146  * For the detail description refer to the MPC8240 user's manual.
 147  */
 148
 149 #define CONFIG_SYS_CLK_FREQ  66666666   /* external frequency to pll */
 150 #define CONFIG_SYS_HZ                1000
 151
 152         /* Bit-field values for MCCR1.
 153          */
 154 #define CONFIG_SYS_ROMNAL           0
 155 #define CONFIG_SYS_ROMFAL           7
 156 #define CONFIG_SYS_BANK0_ROW       2
 157
 158         /* Bit-field values for MCCR2.
 159          */
 160 #define CONFIG_SYS_REFINT           0x400           /* Refresh interval FIXME: was 0t430                */
 161
 162         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 163          */
 164 #define CONFIG_SYS_BSTOPRE          192
 165
 166         /* Bit-field values for MCCR3.
 167          */
 168 #define CONFIG_SYS_REFREC           2       /* Refresh to activate interval */
 169
 170         /* Bit-field values for MCCR4.
 171          */
 172 #define CONFIG_SYS_PRETOACT         2       /* Precharge to activate interval */
 173 #define CONFIG_SYS_ACTTOPRE         5       /* Activate to Precharge interval */
 174 #define CONFIG_SYS_ACTORW           3       /* FIXME was 2 */
 175 #define CONFIG_SYS_SDMODE_CAS_LAT  3        /* SDMODE CAS latancy */
 176 #define CONFIG_SYS_SDMODE_WRAP      0       /* SDMODE wrap type */
 177 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 178 #define CONFIG_SYS_EXTROM           1
 179 #define CONFIG_SYS_REGDIMM          0
 180
 181 #define CONFIG_SYS_ODCR         0xff    /* configures line driver impedances,   */
 182                                         /* see 8245 book for bit definitions    */
 183 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8245 retains the        */
 184                                         /* currently accessed page in memory    */
 185                                         /* see 8245 book for details            */
 186
 187 /* Memory bank settings.
 188  * Only bits 20-29 are actually used from these vales to set the
 189  * start/end addresses. The upper two bits will always be 0, and the lower
 190  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 191  * address. Refer to the MPC8240 book.
 192  */
 193
 194 #define CONFIG_SYS_BANK0_START      0x00000000
 195 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 196 #define CONFIG_SYS_BANK0_ENABLE    1
 197 #define CONFIG_SYS_BANK1_START      0x3ff00000
 198 #define CONFIG_SYS_BANK1_END        0x3fffffff
 199 #define CONFIG_SYS_BANK1_ENABLE    0
 200 #define CONFIG_SYS_BANK2_START      0x3ff00000
 201 #define CONFIG_SYS_BANK2_END        0x3fffffff
 202 #define CONFIG_SYS_BANK2_ENABLE    0
 203 #define CONFIG_SYS_BANK3_START      0x3ff00000
 204 #define CONFIG_SYS_BANK3_END        0x3fffffff
 205 #define CONFIG_SYS_BANK3_ENABLE    0
 206 #define CONFIG_SYS_BANK4_START      0x3ff00000
 207 #define CONFIG_SYS_BANK4_END        0x3fffffff
 208 #define CONFIG_SYS_BANK4_ENABLE    0
 209 #define CONFIG_SYS_BANK5_START      0x3ff00000
 210 #define CONFIG_SYS_BANK5_END        0x3fffffff
 211 #define CONFIG_SYS_BANK5_ENABLE    0
 212 #define CONFIG_SYS_BANK6_START      0x3ff00000
 213 #define CONFIG_SYS_BANK6_END        0x3fffffff
 214 #define CONFIG_SYS_BANK6_ENABLE    0
 215 #define CONFIG_SYS_BANK7_START      0x3ff00000
 216 #define CONFIG_SYS_BANK7_END        0x3fffffff
 217 #define CONFIG_SYS_BANK7_ENABLE    0
 218
 219 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 220 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 221
 222 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 223 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 224
 225 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 226 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 227
 228 #define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 229 #define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 230
 231 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 232 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 233 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 234 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 235 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 236 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 237 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 238 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 239
 240 /*
 241  * For booting Linux, the board info and command line data
 242  * have to be in the first 8 MB of memory, since this is
 243  * the maximum mapped by the Linux kernel during initialization.
 244  */
 245 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 246
 247 /*-----------------------------------------------------------------------
 248  * FLASH organization
 249  */
 250 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* Max number of flash banks            */
 251 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* Max number of sectors per flash      */
 252
 253 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 254 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 255
 256
 257         /* Warining: environment is not EMBEDDED in the U-Boot code.
 258          * It's stored in flash separately.
 259          */
 260 #define CONFIG_ENV_IS_IN_FLASH      1
 261 #define CONFIG_ENV_ADDR         0xFFFF0000
 262 #define CONFIG_ENV_SIZE         0x00010000 /* Size of the Environment           */
 263 #define CONFIG_ENV_SECT_SIZE    0x00010000 /* Size of the Environment Sector    */
 264
 265 /*-----------------------------------------------------------------------
 266  * Cache Configuration
 267  */
 268 #define CONFIG_SYS_CACHELINE_SIZE       32
 269 #if defined(CONFIG_CMD_KGDB)
 270 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 271 #endif
 272
 273 /*
 274  * Internal Definitions
 275  *
 276  * Boot Flags
 277  */
 278 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 279 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 280
 281 /*-----------------------------------------------------------------------
 282  * PCI stuff
 283  *-----------------------------------------------------------------------
 284  */
 285 #define CONFIG_PCI
 286 #define CONFIG_PCI_PNP
 287 #undef  CONFIG_PCI_SCAN_SHOW
 288
 289
 290 #define CONFIG_SK98
 291 #define CONFIG_NET_MULTI
 292
 293
 294 #endif  /* __CONFIG_H */