include/configs/SM850.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #undef TQM8xxL_80MHz    /*      1       / * define for 80 MHz CPU only  */
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  39 #define CONFIG_SM850            1       /*...on a MPC850 Service Module */
  40
  41 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  42 #define CONFIG_SYS_SMC_RXBUFLEN 128
  43 #define CONFIG_SYS_MAXIDLE      10
  44 #define CONFIG_BAUDRATE         115200
  45 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  46
  47 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  48
  49 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  50
  51 #undef  CONFIG_BOOTARGS
  52 #define CONFIG_BOOTCOMMAND                                                      \
  53         "bootp; "                                                               \
  54         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  55         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  56         "bootm"
  57
  58 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  59 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  60
  61 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  62
  63 #undef  CONFIG_STATUS_LED               /* Status LED not enabled       */
  64
  65 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_SUBNETMASK
  71 #define CONFIG_BOOTP_GATEWAY
  72 #define CONFIG_BOOTP_HOSTNAME
  73 #define CONFIG_BOOTP_BOOTPATH
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75
  76
  77 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  78
  79
  80 /*
  81  * Command line configuration.
  82  */
  83 #include <config_cmd_default.h>
  84
  85 #define CONFIG_CMD_DHCP
  86 #define CONFIG_CMD_DATE
  87
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  93 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  94 #if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
  95 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  96 #else
  97 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  98 #endif
  99 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 100 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 101 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 102
 103 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 104 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 105
 106 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 107
 108 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 109
 110 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 111
 112 /*
 113  * Low Level Configuration Settings
 114  * (address mappings, register initial values, etc.)
 115  * You should know what you are doing if you make changes here.
 116  */
 117 /*-----------------------------------------------------------------------
 118  * Internal Memory Mapped Register
 119  */
 120 #define CONFIG_SYS_IMMR         0xFFF00000
 121
 122 /*-----------------------------------------------------------------------
 123  * Definitions for initial stack pointer and data area (in DPRAM)
 124  */
 125 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 126 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 127 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 129 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 130
 131 /*-----------------------------------------------------------------------
 132  * Start addresses for the final memory configuration
 133  * (Set up by the startup code)
 134  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 135  */
 136 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 137 #define CONFIG_SYS_FLASH_BASE           0x40000000
 138 #if defined(DEBUG)
 139 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 140 #else
 141 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 142 #endif
 143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 144 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 145
 146 /*
 147  * For booting Linux, the board info and command line data
 148  * have to be in the first 8 MB of memory, since this is
 149  * the maximum mapped by the Linux kernel during initialization.
 150  */
 151 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 152
 153 /*-----------------------------------------------------------------------
 154  * FLASH organization
 155  */
 156 /* use CFI flash driver */
 157 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 158 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 159 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 160 #define CONFIG_SYS_FLASH_EMPTY_INFO
 161 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 162 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 163 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 164
 165 #define CONFIG_ENV_IS_IN_FLASH  1
 166 #define CONFIG_ENV_OFFSET       0x8000  /*   Offset   of Environment Sector     */
 167 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 168
 169 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 170
 171 /*-----------------------------------------------------------------------
 172  * Hardware Information Block
 173  */
 174 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 175 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 176 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 177
 178 /*-----------------------------------------------------------------------
 179  * Cache Configuration
 180  */
 181 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 182 #if defined(CONFIG_CMD_KGDB)
 183 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 184 #endif
 185
 186 /*-----------------------------------------------------------------------
 187  * SYPCR - System Protection Control                            11-9
 188  * SYPCR can only be written once after reset!
 189  *-----------------------------------------------------------------------
 190  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 191  */
 192 #if defined(CONFIG_WATCHDOG)
 193 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 194                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 195 #else
 196 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 197 #endif
 198
 199 /*-----------------------------------------------------------------------
 200  * SIUMCR - SIU Module Configuration                            11-6
 201  *-----------------------------------------------------------------------
 202  * PCMCIA config., multi-function pin tri-state
 203  */
 204 #ifndef CONFIG_CAN_DRIVER
 205 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 206 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 207 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 208 #endif  /* CONFIG_CAN_DRIVER */
 209
 210 /*-----------------------------------------------------------------------
 211  * TBSCR - Time Base Status and Control                         11-26
 212  *-----------------------------------------------------------------------
 213  * Clear Reference Interrupt Status, Timebase freezing enabled
 214  */
 215 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 216
 217 /*-----------------------------------------------------------------------
 218  * RTCSC - Real-Time Clock Status and Control Register          11-27
 219  *-----------------------------------------------------------------------
 220  */
 221 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 222
 223 /*-----------------------------------------------------------------------
 224  * PISCR - Periodic Interrupt Status and Control                11-31
 225  *-----------------------------------------------------------------------
 226  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 227  */
 228 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 229
 230 /*-----------------------------------------------------------------------
 231  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 232  *-----------------------------------------------------------------------
 233  * Reset PLL lock status sticky bit, timer expired status bit and timer
 234  * interrupt status bit
 235  *
 236  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 237  */
 238 #ifdef TQM8xxL_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 239 #define CONFIG_SYS_PLPRCR                                                       \
 240                 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 241 #else
 242 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 243 #endif  /* TQM8xxL_80MHz */
 244
 245 /*-----------------------------------------------------------------------
 246  * SCCR - System Clock and reset Control Register               15-27
 247  *-----------------------------------------------------------------------
 248  * Set clock output, timebase and RTC source and divider,
 249  * power management and some other internal clocks
 250  */
 251 #define SCCR_MASK       SCCR_EBDF11
 252 #ifdef TQM8xxL_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 253 #define CONFIG_SYS_SCCR (/* SCCR_TBS  | */ \
 254                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 255                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 256                          SCCR_DFALCD00)
 257 #else                   /* up to 50 MHz we use a 1:1 clock */
 258 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 259                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 260                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 261                          SCCR_DFALCD00)
 262 #endif  /* TQM8xxL_80MHz */
 263
 264 /*-----------------------------------------------------------------------
 265  * PCMCIA stuff
 266  *-----------------------------------------------------------------------
 267  *
 268  */
 269 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 270 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 271 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 272 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 273 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 274 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 275 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 276 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 277
 278 /*-----------------------------------------------------------------------
 279  *
 280  *-----------------------------------------------------------------------
 281  *
 282  */
 283 #define CONFIG_SYS_DER  0
 284
 285 /*
 286  * Init Memory Controller:
 287  *
 288  * BR0/1 and OR0/1 (FLASH)
 289  */
 290
 291 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 292 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 293
 294 /* used to re-map FLASH both when starting from SRAM or FLASH:
 295  * restrict access enough to keep SRAM working (if any)
 296  * but not too much to meddle with FLASH accesses
 297  */
 298 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 299 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 300
 301 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 302 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 303                                  OR_SCY_5_CLK | OR_EHTR)
 304
 305 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 306 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 307 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 308
 309 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 310 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 311 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 312
 313 /*
 314  * BR2/3 and OR2/3 (SDRAM)
 315  *
 316  */
 317 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 318 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 319 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 320
 321 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 322 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 323
 324 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 325 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 326
 327 #ifndef CONFIG_CAN_DRIVER
 328 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 329 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 330 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 331 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 332 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 333 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 334 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 335                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 336 #endif  /* CONFIG_CAN_DRIVER */
 337
 338 /*
 339  * Memory Periodic Timer Prescaler
 340  */
 341
 342 /* periodic timer for refresh */
 343 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 344
 345 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 346 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 347 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 348
 349 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 350 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 351 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 352
 353 /*
 354  * MAMR settings for SDRAM
 355  */
 356
 357 /* 8 column SDRAM */
 358 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 359                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 360                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 361 /* 9 column SDRAM */
 362 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 363                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 364                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 365
 366
 367 /*
 368  * Internal Definitions
 369  *
 370  * Boot Flags
 371  */
 372 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 373 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 374
 375 /* pass open firmware flat tree */
 376 #define CONFIG_OF_LIBFDT        1
 377 #define CONFIG_OF_BOARD_SETUP   1
 378 #define CONFIG_HWCONFIG         1
 379
 380 #endif  /* __CONFIG_H */