include/configs/Sandpoint8240.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* ------------------------------------------------------------------------- */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MPC8240          1
  23 #define CONFIG_SANDPOINT        1
  24
  25 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  26 #define CONFIG_SYS_LDSCRIPT     "board/sandpoint/u-boot.lds"
  27
  28 #if 0
  29 #define USE_DINK32              1
  30 #else
  31 #undef USE_DINK32
  32 #endif
  33
  34 #define CONFIG_CONS_INDEX       1
  35 #define CONFIG_BAUDRATE         9600
  36
  37 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  38
  39 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  40
  41 #define CONFIG_PREBOOT  "echo;" \
  42         "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
  43         "echo"
  44
  45 #undef  CONFIG_BOOTARGS
  46
  47 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  48         "netdev=eth0\0"                                                 \
  49         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  50                 "nfsroot=${serverip}:${rootpath}\0"                     \
  51         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  52         "addip=setenv bootargs ${bootargs} "                            \
  53                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  54                 ":${hostname}:${netdev}:off panic=1\0"                  \
  55         "net_self=tftp ${kernel_addr} ${bootfile};"                     \
  56                 "tftp ${ramdisk_addr} ${ramdisk};"                      \
  57                 "run ramargs addip;"                                    \
  58                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  59         "net_nfs=tftp ${kernel_addr} ${bootfile};"                      \
  60                 "run nfsargs addip;bootm\0"                             \
  61         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  62         "bootfile=/tftpboot/SP8240/uImage\0"                            \
  63         "ramdisk=/tftpboot/SP8240/uRamdisk\0"                           \
  64         "kernel_addr=200000\0"                                          \
  65         "ramdisk_addr=400000\0"                                         \
  66         ""
  67 #define CONFIG_BOOTCOMMAND      "run flash_self"
  68
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_DHCP
  85 #define CONFIG_CMD_ELF
  86 #define CONFIG_CMD_I2C
  87 #define CONFIG_CMD_SDRAM
  88 #define CONFIG_CMD_EEPROM
  89 #define CONFIG_CMD_NFS
  90 #define CONFIG_CMD_PCI
  91 #define CONFIG_CMD_SNTP
  92
  93
  94 #define CONFIG_DRAM_SPEED       100             /* MHz                          */
  95
  96 /*
  97  * Miscellaneous configurable options
  98  */
  99 #define CONFIG_SYS_LONGHELP             1               /* undef to save memory         */
 100 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 101 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 102 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 103 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 104 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address         */
 105
 106 /*-----------------------------------------------------------------------
 107  * PCI stuff
 108  *-----------------------------------------------------------------------
 109  */
 110 #define CONFIG_PCI                              /* include pci support          */
 111 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 112 #undef CONFIG_PCI_PNP
 113
 114
 115 #define CONFIG_EEPRO100
 116 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 117
 118 #define PCI_ENET0_IOADDR        0x80000000
 119 #define PCI_ENET0_MEMADDR       0x80000000
 120 #define PCI_ENET1_IOADDR        0x81000000
 121 #define PCI_ENET1_MEMADDR       0x81000000
 122
 123
 124 /*-----------------------------------------------------------------------
 125  * Start addresses for the final memory configuration
 126  * (Set up by the startup code)
 127  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 128  */
 129 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 130 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 131
 132 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 133
 134 #if defined (USE_DINK32)
 135 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 136 #define CONFIG_SYS_MONITOR_BASE 0x00090000
 137 #define CONFIG_SYS_RAMBOOT              1
 138 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 139 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 140 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 141 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 142 #else
 143 #undef  CONFIG_SYS_RAMBOOT
 144 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 146
 147
 148 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 149 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 150 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 151
 152 #endif
 153
 154 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
 155 #if 0
 156 #define CONFIG_SYS_FLASH_SIZE           (512 * 1024)    /* sandpoint has tiny eeprom    */
 157 #else
 158 #define CONFIG_SYS_FLASH_SIZE           (1024 * 1024)   /* Unity has onboard 1MByte flash */
 159 #endif
 160 #define CONFIG_ENV_IS_IN_FLASH  1
 161 #define CONFIG_ENV_OFFSET               0x00004000      /* Offset of Environment Sector */
 162 #define CONFIG_ENV_SIZE         0x00002000      /* Total Size of Environment Sector */
 163
 164 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 165
 166 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on             */
 167 #define CONFIG_SYS_MEMTEST_END          0x04000000      /* 0 ... 32 MB in DRAM          */
 168
 169 #define CONFIG_SYS_EUMB_ADDR            0xFC000000
 170
 171 #define CONFIG_SYS_ISA_MEM              0xFD000000
 172 #define CONFIG_SYS_ISA_IO               0xFE000000
 173
 174 #define CONFIG_SYS_FLASH_RANGE_BASE     0xFF000000      /* flash memory address range   */
 175 #define CONFIG_SYS_FLASH_RANGE_SIZE     0x01000000
 176 #define FLASH_BASE0_PRELIM      0xFFF00000      /* sandpoint flash              */
 177 #define FLASH_BASE1_PRELIM      0xFF000000      /* PMC onboard flash            */
 178
 179 /*
 180  * select i2c support configuration
 181  *
 182  * Supported configurations are {none, software, hardware} drivers.
 183  * If the software driver is chosen, there are some additional
 184  * configuration items that the driver uses to drive the port pins.
 185  */
 186 #define CONFIG_HARD_I2C         1               /* To enable I2C support */
 187 #undef  CONFIG_SYS_I2C_SOFT
 188 #define CONFIG_SYS_I2C_SLAVE    0x7F
 189 #define CONFIG_SYS_I2C_SPEED    400000
 190
 191 #ifdef CONFIG_SYS_I2C_SOFT
 192 #error "Soft I2C is not configured properly.  Please review!"
 193 #define CONFIG_SYS_I2C
 194 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 195 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 196 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 197 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 198 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 199 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 200 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 201                                 else    iop->pdat &= ~0x00010000
 202 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 203                                 else    iop->pdat &= ~0x00020000
 204 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 205 #endif /* CONFIG_SYS_I2C_SOFT */
 206
 207
 208 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57            /* EEPROM IS24C02               */
 209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 210 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3       /* write page size              */
 211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec          */
 212
 213
 214 #define CONFIG_SYS_FLASH_BANKS          { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 215
 216 /*-----------------------------------------------------------------------
 217  * Definitions for initial stack pointer and data area (in DPRAM)
 218  */
 219
 220
 221 /* #define CONFIG_WINBOND_83C553        1       / *has a winbond bridge                 */
 222 #define CONFIG_SYS_USE_WINBOND_IDE      0       /*use winbond 83c553 internal IDE ctrlr */
 223 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800   /*pci-isa bridge config addr    */
 224 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900   /*ide config addr               */
 225
 226 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 227 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 228
 229 /*
 230  * NS87308 Configuration
 231  */
 232 #define CONFIG_NS87308                  /* Nat Semi super-io controller on ISA bus */
 233
 234 #define CONFIG_SYS_NS87308_BADDR_10     1
 235
 236 #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1   | \
 237                                   CONFIG_SYS_NS87308_UART2   | \
 238                                   CONFIG_SYS_NS87308_POWRMAN | \
 239                                   CONFIG_SYS_NS87308_RTC_APC )
 240
 241 #undef  CONFIG_SYS_NS87308_PS2MOD
 242
 243 #define CONFIG_SYS_NS87308_CS0_BASE     0x0076
 244 #define CONFIG_SYS_NS87308_CS0_CONF     0x30
 245 #define CONFIG_SYS_NS87308_CS1_BASE     0x0075
 246 #define CONFIG_SYS_NS87308_CS1_CONF     0x30
 247 #define CONFIG_SYS_NS87308_CS2_BASE     0x0074
 248 #define CONFIG_SYS_NS87308_CS2_CONF     0x30
 249
 250 /*
 251  * NS16550 Configuration
 252  */
 253 #define CONFIG_SYS_NS16550
 254 #define CONFIG_SYS_NS16550_SERIAL
 255
 256 #define CONFIG_SYS_NS16550_REG_SIZE     1
 257
 258 #define CONFIG_SYS_NS16550_CLK          1843200
 259
 260 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
 261 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
 262
 263 /*
 264  * Low Level Configuration Settings
 265  * (address mappings, register initial values, etc.)
 266  * You should know what you are doing if you make changes here.
 267  */
 268
 269 #define CONFIG_SYS_CLK_FREQ  33000000   /* external frequency to pll */
 270 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1
 271
 272 #define CONFIG_SYS_ROMNAL               7       /*rom/flash next access time            */
 273 #define CONFIG_SYS_ROMFAL               11      /*rom/flash access time                 */
 274
 275 #define CONFIG_SYS_REFINT       430     /* no of clock cycles between CBR refresh cycles */
 276
 277 /* the following are for SDRAM only*/
 278 #define CONFIG_SYS_BSTOPRE      121     /* Burst To Precharge, sets open page interval */
 279 #define CONFIG_SYS_REFREC               8       /* Refresh to activate interval         */
 280 #define CONFIG_SYS_RDLAT                4       /* data latency from read command       */
 281 #define CONFIG_SYS_PRETOACT             3       /* Precharge to activate interval       */
 282 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 283 #define CONFIG_SYS_ACTORW               3       /* Activate to R/W                      */
 284 #define CONFIG_SYS_SDMODE_CAS_LAT       3       /* SDMODE CAS latency                   */
 285 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 286 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* SDMODE Burst length 2=4, 3=8         */
 287
 288 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 289
 290 /* memory bank settings*/
 291 /*
 292  * only bits 20-29 are actually used from these vales to set the
 293  * start/end address the upper two bits will be 0, and the lower 20
 294  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 295  * end address
 296  */
 297 #define CONFIG_SYS_BANK0_START          0x00000000
 298 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 299 #define CONFIG_SYS_BANK0_ENABLE 1
 300 #define CONFIG_SYS_BANK1_START          0x3ff00000
 301 #define CONFIG_SYS_BANK1_END            0x3fffffff
 302 #define CONFIG_SYS_BANK1_ENABLE 0
 303 #define CONFIG_SYS_BANK2_START          0x3ff00000
 304 #define CONFIG_SYS_BANK2_END            0x3fffffff
 305 #define CONFIG_SYS_BANK2_ENABLE 0
 306 #define CONFIG_SYS_BANK3_START          0x3ff00000
 307 #define CONFIG_SYS_BANK3_END            0x3fffffff
 308 #define CONFIG_SYS_BANK3_ENABLE 0
 309 #define CONFIG_SYS_BANK4_START          0x00000000
 310 #define CONFIG_SYS_BANK4_END            0x00000000
 311 #define CONFIG_SYS_BANK4_ENABLE 0
 312 #define CONFIG_SYS_BANK5_START          0x00000000
 313 #define CONFIG_SYS_BANK5_END            0x00000000
 314 #define CONFIG_SYS_BANK5_ENABLE 0
 315 #define CONFIG_SYS_BANK6_START          0x00000000
 316 #define CONFIG_SYS_BANK6_END            0x00000000
 317 #define CONFIG_SYS_BANK6_ENABLE 0
 318 #define CONFIG_SYS_BANK7_START          0x00000000
 319 #define CONFIG_SYS_BANK7_END            0x00000000
 320 #define CONFIG_SYS_BANK7_ENABLE 0
 321 /*
 322  * Memory bank enable bitmask, specifying which of the banks defined above
 323  are actually present. MSB is for bank #7, LSB is for bank #0.
 324  */
 325 #define CONFIG_SYS_BANK_ENABLE          0x01
 326
 327 #define CONFIG_SYS_ODCR         0xff    /* configures line driver impedances,   */
 328                                         /* see 8240 book for bit definitions    */
 329 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 330                                         /* currently accessed page in memory    */
 331                                         /* see 8240 book for details            */
 332
 333 /* SDRAM 0 - 256MB */
 334 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 335 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 336
 337 /* stack in DCACHE @ 1GB (no backing mem) */
 338 #if defined(USE_DINK32)
 339 #define CONFIG_SYS_IBAT1L       (0x40000000 | BATL_PP_00 )
 340 #define CONFIG_SYS_IBAT1U       (0x40000000 | BATU_BL_128K )
 341 #else
 342 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 343 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 344 #endif
 345
 346 /* PCI memory */
 347 #define CONFIG_SYS_IBAT2L       (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 348 #define CONFIG_SYS_IBAT2U       (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 349
 350 /* Flash, config addrs, etc */
 351 #define CONFIG_SYS_IBAT3L       (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 352 #define CONFIG_SYS_IBAT3U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 353
 354 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 355 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 356 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 357 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 358 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 359 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 360 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 361 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 362
 363 /*
 364  * For booting Linux, the board info and command line data
 365  * have to be in the first 8 MB of memory, since this is
 366  * the maximum mapped by the Linux kernel during initialization.
 367  */
 368 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 369 /*-----------------------------------------------------------------------
 370  * FLASH organization
 371  */
 372 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 373 #define CONFIG_SYS_MAX_FLASH_SECT       20      /* max number of sectors on one chip    */
 374
 375 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 376 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 377
 378 /*-----------------------------------------------------------------------
 379  * Cache Configuration
 380  */
 381 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8240 CPU                      */
 382 #if defined(CONFIG_CMD_KGDB)
 383 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 384 #endif
 385
 386 /* values according to the manual */
 387
 388 #define CONFIG_DRAM_50MHZ       1
 389 #define CONFIG_SDRAM_50MHZ
 390
 391 #undef  NR_8259_INTS
 392 #define NR_8259_INTS            1
 393
 394
 395 #define CONFIG_DISK_SPINUP_TIME 1000000
 396
 397
 398 #endif  /* __CONFIG_H */