include/configs/T102xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_DISPLAY_BOARDINFO
  16 #define CONFIG_BOOKE
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  19 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  20 #define CONFIG_MP                       /* support multiple processors */
  21 #define CONFIG_PHYS_64BIT
  22 #define CONFIG_ENABLE_36BIT_PHYS
  23
  24 #ifdef CONFIG_PHYS_64BIT
  25 #define CONFIG_ADDR_MAP         1
  26 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  27 #endif
  28
  29 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  30 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  31 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  32
  33 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  34 #define CONFIG_ENV_OVERWRITE
  35
  36 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  37
  38 /* support deep sleep */
  39 #ifdef CONFIG_PPC_T1024
  40 #define CONFIG_DEEP_SLEEP
  41 #endif
  42 #if defined(CONFIG_DEEP_SLEEP)
  43 #define CONFIG_SILENT_CONSOLE
  44 #define CONFIG_BOARD_EARLY_INIT_F
  45 #endif
  46
  47 #ifdef CONFIG_RAMBOOT_PBL
  48 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  49 #if defined(CONFIG_T1024RDB)
  50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
  51 #elif defined(CONFIG_T1023RDB)
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
  53 #endif
  54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  55 #define CONFIG_SPL_ENV_SUPPORT
  56 #define CONFIG_SPL_SERIAL_SUPPORT
  57 #define CONFIG_SPL_FLUSH_IMAGE
  58 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  59 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  60 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  61 #define CONFIG_SPL_I2C_SUPPORT
  62 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  63 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  64 #define CONFIG_SYS_TEXT_BASE            0x30001000
  65 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  66 #define CONFIG_SPL_PAD_TO               0x40000
  67 #define CONFIG_SPL_MAX_SIZE             0x28000
  68 #define RESET_VECTOR_OFFSET             0x27FFC
  69 #define BOOT_PAGE_OFFSET                0x27000
  70 #ifdef CONFIG_SPL_BUILD
  71 #define CONFIG_SPL_SKIP_RELOCATE
  72 #define CONFIG_SPL_COMMON_INIT_DDR
  73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  74 #define CONFIG_SYS_NO_FLASH
  75 #endif
  76
  77 #ifdef CONFIG_NAND
  78 #define CONFIG_SPL_NAND_SUPPORT
  79 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  80 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  81 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  82 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  83 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  84 #define CONFIG_SPL_NAND_BOOT
  85 #endif
  86
  87 #ifdef CONFIG_SPIFLASH
  88 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  89 #define CONFIG_SPL_SPI_SUPPORT
  90 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  91 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  96 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  97 #ifndef CONFIG_SPL_BUILD
  98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  99 #endif
 100 #define CONFIG_SPL_SPI_BOOT
 101 #endif
 102
 103 #ifdef CONFIG_SDCARD
 104 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
 105 #define CONFIG_SPL_MMC_SUPPORT
 106 #define CONFIG_SPL_MMC_MINIMAL
 107 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 108 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 109 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 110 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 111 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 112 #ifndef CONFIG_SPL_BUILD
 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 114 #endif
 115 #define CONFIG_SPL_MMC_BOOT
 116 #endif
 117
 118 #endif /* CONFIG_RAMBOOT_PBL */
 119
 120 #ifndef CONFIG_SYS_TEXT_BASE
 121 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 122 #endif
 123
 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 125 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 126 #endif
 127
 128 #ifndef CONFIG_SYS_NO_FLASH
 129 #define CONFIG_FLASH_CFI_DRIVER
 130 #define CONFIG_SYS_FLASH_CFI
 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 132 #endif
 133
 134 /* PCIe Boot - Master */
 135 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 136 /*
 137  * for slave u-boot IMAGE instored in master memory space,
 138  * PHYS must be aligned based on the SIZE
 139  */
 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 144 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 145 #else
 146 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 147 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 148 #endif
 149 /*
 150  * for slave UCODE and ENV instored in master memory space,
 151  * PHYS must be aligned based on the SIZE
 152  */
 153 #ifdef CONFIG_PHYS_64BIT
 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 155 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 156 #else
 157 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 158 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 159 #endif
 160 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 161 /* slave core release by master*/
 162 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 163 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 164
 165 /* PCIe Boot - Slave */
 166 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 167 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 168 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 169                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 170 /* Set 1M boot space for PCIe boot */
 171 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 172 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 173                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 174 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 175 #define CONFIG_SYS_NO_FLASH
 176 #endif
 177
 178 #if defined(CONFIG_SPIFLASH)
 179 #define CONFIG_SYS_EXTRA_ENV_RELOC
 180 #define CONFIG_ENV_IS_IN_SPI_FLASH
 181 #define CONFIG_ENV_SPI_BUS              0
 182 #define CONFIG_ENV_SPI_CS               0
 183 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 184 #define CONFIG_ENV_SPI_MODE             0
 185 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 186 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 187 #if defined(CONFIG_T1024RDB)
 188 #define CONFIG_ENV_SECT_SIZE            0x10000
 189 #elif defined(CONFIG_T1023RDB)
 190 #define CONFIG_ENV_SECT_SIZE            0x40000
 191 #endif
 192 #elif defined(CONFIG_SDCARD)
 193 #define CONFIG_SYS_EXTRA_ENV_RELOC
 194 #define CONFIG_ENV_IS_IN_MMC
 195 #define CONFIG_SYS_MMC_ENV_DEV          0
 196 #define CONFIG_ENV_SIZE                 0x2000
 197 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 198 #elif defined(CONFIG_NAND)
 199 #define CONFIG_SYS_EXTRA_ENV_RELOC
 200 #define CONFIG_ENV_IS_IN_NAND
 201 #define CONFIG_ENV_SIZE                 0x2000
 202 #if defined(CONFIG_T1024RDB)
 203 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 204 #elif defined(CONFIG_T1023RDB)
 205 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 206 #endif
 207 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 208 #define CONFIG_ENV_IS_IN_REMOTE
 209 #define CONFIG_ENV_ADDR         0xffe20000
 210 #define CONFIG_ENV_SIZE         0x2000
 211 #elif defined(CONFIG_ENV_IS_NOWHERE)
 212 #define CONFIG_ENV_SIZE         0x2000
 213 #else
 214 #define CONFIG_ENV_IS_IN_FLASH
 215 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 216 #define CONFIG_ENV_SIZE         0x2000
 217 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 218 #endif
 219
 220
 221 #ifndef __ASSEMBLY__
 222 unsigned long get_board_sys_clk(void);
 223 unsigned long get_board_ddr_clk(void);
 224 #endif
 225
 226 #define CONFIG_SYS_CLK_FREQ     100000000
 227 #define CONFIG_DDR_CLK_FREQ     100000000
 228
 229 /*
 230  * These can be toggled for performance analysis, otherwise use default.
 231  */
 232 #define CONFIG_SYS_CACHE_STASHING
 233 #define CONFIG_BACKSIDE_L2_CACHE
 234 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 235 #define CONFIG_BTB                      /* toggle branch predition */
 236 #define CONFIG_DDR_ECC
 237 #ifdef CONFIG_DDR_ECC
 238 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 239 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 240 #endif
 241
 242 #define CONFIG_CMD_MEMTEST
 243 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 244 #define CONFIG_SYS_MEMTEST_END          0x00400000
 245 #define CONFIG_SYS_ALT_MEMTEST
 246 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 247
 248 /*
 249  *  Config the L3 Cache as L3 SRAM
 250  */
 251 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 252 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 253 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 254 #ifdef CONFIG_RAMBOOT_PBL
 255 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 256 #endif
 257 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 258 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 259 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 260 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 261
 262 #ifdef CONFIG_PHYS_64BIT
 263 #define CONFIG_SYS_DCSRBAR              0xf0000000
 264 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 265 #endif
 266
 267 /* EEPROM */
 268 #define CONFIG_ID_EEPROM
 269 #define CONFIG_SYS_I2C_EEPROM_NXID
 270 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 271 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 272 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 274 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 275
 276 /*
 277  * DDR Setup
 278  */
 279 #define CONFIG_VERY_BIG_RAM
 280 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 281 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 282 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 283 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 284 #define CONFIG_FSL_DDR_INTERACTIVE
 285 #if defined(CONFIG_T1024RDB)
 286 #define CONFIG_DDR_SPD
 287 #define CONFIG_SYS_FSL_DDR3
 288 #define CONFIG_SYS_SPD_BUS_NUM  0
 289 #define SPD_EEPROM_ADDRESS      0x51
 290 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 291 #elif defined(CONFIG_T1023RDB)
 292 #define CONFIG_SYS_FSL_DDR4
 293 #define CONFIG_SYS_DDR_RAW_TIMING
 294 #define CONFIG_SYS_SDRAM_SIZE   2048
 295 #endif
 296
 297 /*
 298  * IFC Definitions
 299  */
 300 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 301 #ifdef CONFIG_PHYS_64BIT
 302 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 303 #else
 304 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 305 #endif
 306
 307 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 308 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 309                                 CSPR_PORT_SIZE_16 | \
 310                                 CSPR_MSEL_NOR | \
 311                                 CSPR_V)
 312 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 313
 314 /* NOR Flash Timing Params */
 315 #if defined(CONFIG_T1024RDB)
 316 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 317 #elif defined(CONFIG_T1023RDB)
 318 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 319                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 320 #endif
 321 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 322                                 FTIM0_NOR_TEADC(0x5) | \
 323                                 FTIM0_NOR_TEAHC(0x5))
 324 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 325                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 326                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 327 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 328                                 FTIM2_NOR_TCH(0x4) | \
 329                                 FTIM2_NOR_TWPH(0x0E) | \
 330                                 FTIM2_NOR_TWP(0x1c))
 331 #define CONFIG_SYS_NOR_FTIM3    0x0
 332
 333 #define CONFIG_SYS_FLASH_QUIET_TEST
 334 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 335
 336 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 337 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 338 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 339 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 340
 341 #define CONFIG_SYS_FLASH_EMPTY_INFO
 342 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 343
 344 #ifdef CONFIG_T1024RDB
 345 /* CPLD on IFC */
 346 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 347 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 348 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 349 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 350                                                 | CSPR_PORT_SIZE_8 \
 351                                                 | CSPR_MSEL_GPCM \
 352                                                 | CSPR_V)
 353 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 354 #define CONFIG_SYS_CSOR2                0x0
 355
 356 /* CPLD Timing parameters for IFC CS2 */
 357 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 358                                                 FTIM0_GPCM_TEADC(0x0e) | \
 359                                                 FTIM0_GPCM_TEAHC(0x0e))
 360 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 361                                                 FTIM1_GPCM_TRAD(0x1f))
 362 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 363                                                 FTIM2_GPCM_TCH(0x8) | \
 364                                                 FTIM2_GPCM_TWP(0x1f))
 365 #define CONFIG_SYS_CS2_FTIM3            0x0
 366 #endif
 367
 368 /* NAND Flash on IFC */
 369 #define CONFIG_NAND_FSL_IFC
 370 #define CONFIG_SYS_NAND_BASE            0xff800000
 371 #ifdef CONFIG_PHYS_64BIT
 372 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 373 #else
 374 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 375 #endif
 376 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 377 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 378                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 379                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 380                                 | CSPR_V)
 381 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 382
 383 #if defined(CONFIG_T1024RDB)
 384 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 385                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 386                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 387                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 388                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 389                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 390                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 391 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 392 #elif defined(CONFIG_T1023RDB)
 393 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 394                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 395                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 396                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 397                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 398                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 399                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 400 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 401 #endif
 402
 403 #define CONFIG_SYS_NAND_ONFI_DETECTION
 404 /* ONFI NAND Flash mode0 Timing Params */
 405 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 406                                         FTIM0_NAND_TWP(0x18)   | \
 407                                         FTIM0_NAND_TWCHT(0x07) | \
 408                                         FTIM0_NAND_TWH(0x0a))
 409 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 410                                         FTIM1_NAND_TWBE(0x39)  | \
 411                                         FTIM1_NAND_TRR(0x0e)   | \
 412                                         FTIM1_NAND_TRP(0x18))
 413 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 414                                         FTIM2_NAND_TREH(0x0a) | \
 415                                         FTIM2_NAND_TWHRE(0x1e))
 416 #define CONFIG_SYS_NAND_FTIM3           0x0
 417
 418 #define CONFIG_SYS_NAND_DDR_LAW         11
 419 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 420 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 421 #define CONFIG_CMD_NAND
 422
 423 #if defined(CONFIG_NAND)
 424 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 425 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 426 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 427 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 428 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 429 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 430 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 431 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 432 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 433 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 434 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 435 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 436 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 437 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 438 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 439 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 440 #else
 441 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 442 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 443 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 444 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 445 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 446 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 447 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 448 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 449 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 450 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 451 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 452 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 453 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 454 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 455 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 456 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 457 #endif
 458
 459 #ifdef CONFIG_SPL_BUILD
 460 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 461 #else
 462 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 463 #endif
 464
 465 #if defined(CONFIG_RAMBOOT_PBL)
 466 #define CONFIG_SYS_RAMBOOT
 467 #endif
 468
 469 #define CONFIG_BOARD_EARLY_INIT_R
 470 #define CONFIG_MISC_INIT_R
 471
 472 #define CONFIG_HWCONFIG
 473
 474 /* define to use L1 as initial stack */
 475 #define CONFIG_L1_INIT_RAM
 476 #define CONFIG_SYS_INIT_RAM_LOCK
 477 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 478 #ifdef CONFIG_PHYS_64BIT
 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 481 /* The assembler doesn't like typecast */
 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 483         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 484           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 485 #else
 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 489 #endif
 490 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 491
 492 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 493                                         GENERATED_GBL_DATA_SIZE)
 494 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 495
 496 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 497 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 498
 499 /* Serial Port */
 500 #define CONFIG_CONS_INDEX       1
 501 #define CONFIG_SYS_NS16550_SERIAL
 502 #define CONFIG_SYS_NS16550_REG_SIZE     1
 503 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 504
 505 #define CONFIG_SYS_BAUDRATE_TABLE       \
 506         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 507
 508 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 509 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 510 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 511 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 512 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 513
 514 /* Video */
 515 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 516 #ifdef CONFIG_FSL_DIU_FB
 517 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 518 #define CONFIG_VIDEO
 519 #define CONFIG_CMD_BMP
 520 #define CONFIG_CFB_CONSOLE
 521 #define CONFIG_VIDEO_SW_CURSOR
 522 #define CONFIG_VGA_AS_SINGLE_DEVICE
 523 #define CONFIG_VIDEO_LOGO
 524 #define CONFIG_VIDEO_BMP_LOGO
 525 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 526 /*
 527  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 528  * disable empty flash sector detection, which is I/O-intensive.
 529  */
 530 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 531 #endif
 532
 533 /* I2C */
 534 #define CONFIG_SYS_I2C
 535 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 536 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 537 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 538 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 539 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 540 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 541 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 542
 543 #define I2C_PCA6408_BUS_NUM             1
 544 #define I2C_PCA6408_ADDR                0x20
 545
 546 /* I2C bus multiplexer */
 547 #define I2C_MUX_CH_DEFAULT      0x8
 548
 549 /*
 550  * RTC configuration
 551  */
 552 #define RTC
 553 #define CONFIG_RTC_DS1337       1
 554 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 555
 556 /*
 557  * eSPI - Enhanced SPI
 558  */
 559 #if defined(CONFIG_T1024RDB)
 560 #elif defined(CONFIG_T1023RDB)
 561 #endif
 562 #define CONFIG_CMD_SF
 563 #define CONFIG_SPI_FLASH_BAR
 564 #define CONFIG_SF_DEFAULT_SPEED 10000000
 565 #define CONFIG_SF_DEFAULT_MODE  0
 566
 567 /*
 568  * General PCIe
 569  * Memory space is mapped 1-1, but I/O space must start from 0.
 570  */
 571 #define CONFIG_PCI              /* Enable PCI/PCIE */
 572 #define CONFIG_PCIE1            /* PCIE controler 1 */
 573 #define CONFIG_PCIE2            /* PCIE controler 2 */
 574 #define CONFIG_PCIE3            /* PCIE controler 3 */
 575 #ifdef CONFIG_PPC_T1040
 576 #define CONFIG_PCIE4            /* PCIE controler 4 */
 577 #endif
 578 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 579 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 580 #define CONFIG_PCI_INDIRECT_BRIDGE
 581
 582 #ifdef CONFIG_PCI
 583 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 584 #ifdef CONFIG_PCIE1
 585 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 586 #ifdef CONFIG_PHYS_64BIT
 587 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 588 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 589 #else
 590 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 591 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 592 #endif
 593 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 594 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 595 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 596 #ifdef CONFIG_PHYS_64BIT
 597 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 598 #else
 599 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 600 #endif
 601 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 602 #endif
 603
 604 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 605 #ifdef CONFIG_PCIE2
 606 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 607 #ifdef CONFIG_PHYS_64BIT
 608 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 609 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 610 #else
 611 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 612 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 613 #endif
 614 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 615 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 616 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 617 #ifdef CONFIG_PHYS_64BIT
 618 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 619 #else
 620 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 621 #endif
 622 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 623 #endif
 624
 625 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 626 #ifdef CONFIG_PCIE3
 627 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 628 #ifdef CONFIG_PHYS_64BIT
 629 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 630 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 631 #else
 632 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 633 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 634 #endif
 635 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 636 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 637 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 638 #ifdef CONFIG_PHYS_64BIT
 639 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 640 #else
 641 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 642 #endif
 643 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 644 #endif
 645
 646 /* controller 4, Base address 203000, to be removed */
 647 #ifdef CONFIG_PCIE4
 648 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 649 #ifdef CONFIG_PHYS_64BIT
 650 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 651 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 652 #else
 653 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 654 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 655 #endif
 656 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 657 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 658 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 659 #ifdef CONFIG_PHYS_64BIT
 660 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 661 #else
 662 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 663 #endif
 664 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 665 #endif
 666
 667 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 668 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 669 #define CONFIG_DOS_PARTITION
 670 #endif  /* CONFIG_PCI */
 671
 672 /*
 673  * USB
 674  */
 675 #define CONFIG_HAS_FSL_DR_USB
 676
 677 #ifdef CONFIG_HAS_FSL_DR_USB
 678 #define CONFIG_USB_EHCI
 679 #define CONFIG_CMD_USB
 680 #define CONFIG_USB_STORAGE
 681 #define CONFIG_USB_EHCI_FSL
 682 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 683 #define CONFIG_CMD_EXT2
 684 #endif
 685
 686 /*
 687  * SDHC
 688  */
 689 #define CONFIG_MMC
 690 #ifdef CONFIG_MMC
 691 #define CONFIG_FSL_ESDHC
 692 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 693 #define CONFIG_CMD_MMC
 694 #define CONFIG_GENERIC_MMC
 695 #define CONFIG_CMD_EXT2
 696 #define CONFIG_CMD_FAT
 697 #define CONFIG_DOS_PARTITION
 698 #endif
 699
 700 /* Qman/Bman */
 701 #ifndef CONFIG_NOBQFMAN
 702 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 703 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 704 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 705 #ifdef CONFIG_PHYS_64BIT
 706 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 707 #else
 708 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 709 #endif
 710 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 711 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 712 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 713 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 714 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 715 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 716                                         CONFIG_SYS_BMAN_CENA_SIZE)
 717 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 718 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 719 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 720 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 721 #ifdef CONFIG_PHYS_64BIT
 722 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 723 #else
 724 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 725 #endif
 726 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 727 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 728 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 729 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 730 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 731 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 732                                         CONFIG_SYS_QMAN_CENA_SIZE)
 733 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 734 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 735
 736 #define CONFIG_SYS_DPAA_FMAN
 737
 738 #ifdef CONFIG_T1024RDB
 739 #define CONFIG_QE
 740 #define CONFIG_U_QE
 741 #endif
 742 /* Default address of microcode for the Linux FMan driver */
 743 #if defined(CONFIG_SPIFLASH)
 744 /*
 745  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 746  * env, so we got 0x110000.
 747  */
 748 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 749 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 750 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 751 #elif defined(CONFIG_SDCARD)
 752 /*
 753  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 754  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 755  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 756  */
 757 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 758 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 759 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 760 #elif defined(CONFIG_NAND)
 761 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 762 #if defined(CONFIG_T1024RDB)
 763 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 764 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 765 #elif defined(CONFIG_T1023RDB)
 766 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 767 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 768 #endif
 769 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 770 /*
 771  * Slave has no ucode locally, it can fetch this from remote. When implementing
 772  * in two corenet boards, slave's ucode could be stored in master's memory
 773  * space, the address can be mapped from slave TLB->slave LAW->
 774  * slave SRIO or PCIE outbound window->master inbound window->
 775  * master LAW->the ucode address in master's memory space.
 776  */
 777 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 778 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 779 #else
 780 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 781 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 782 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 783 #endif
 784 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 785 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 786 #endif /* CONFIG_NOBQFMAN */
 787
 788 #ifdef CONFIG_SYS_DPAA_FMAN
 789 #define CONFIG_FMAN_ENET
 790 #define CONFIG_PHYLIB_10G
 791 #define CONFIG_PHY_REALTEK
 792 #define CONFIG_PHY_AQUANTIA
 793 #if defined(CONFIG_T1024RDB)
 794 #define RGMII_PHY1_ADDR         0x2
 795 #define RGMII_PHY2_ADDR         0x6
 796 #define SGMII_AQR_PHY_ADDR      0x2
 797 #define FM1_10GEC1_PHY_ADDR     0x1
 798 #elif defined(CONFIG_T1023RDB)
 799 #define RGMII_PHY1_ADDR         0x1
 800 #define SGMII_RTK_PHY_ADDR      0x3
 801 #define SGMII_AQR_PHY_ADDR      0x2
 802 #endif
 803 #endif
 804
 805 #ifdef CONFIG_FMAN_ENET
 806 #define CONFIG_MII              /* MII PHY management */
 807 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 808 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 809 #endif
 810
 811 /*
 812  * Dynamic MTD Partition support with mtdparts
 813  */
 814 #ifndef CONFIG_SYS_NO_FLASH
 815 #define CONFIG_MTD_DEVICE
 816 #define CONFIG_MTD_PARTITIONS
 817 #define CONFIG_CMD_MTDPARTS
 818 #define CONFIG_FLASH_CFI_MTD
 819 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 820                         "spi0=spife110000.1"
 821 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 822                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 823                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
 824                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 825 #endif
 826
 827 /*
 828  * Environment
 829  */
 830 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 831 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 832
 833 /*
 834  * Command line configuration.
 835  */
 836 #define CONFIG_CMD_DATE
 837 #define CONFIG_CMD_DHCP
 838 #define CONFIG_CMD_EEPROM
 839 #define CONFIG_CMD_ERRATA
 840 #define CONFIG_CMD_GREPENV
 841 #define CONFIG_CMD_IRQ
 842 #define CONFIG_CMD_I2C
 843 #define CONFIG_CMD_MII
 844 #define CONFIG_CMD_PING
 845 #define CONFIG_CMD_REGINFO
 846
 847 #ifdef CONFIG_PCI
 848 #define CONFIG_CMD_PCI
 849 #endif
 850
 851 /*
 852  * Miscellaneous configurable options
 853  */
 854 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 855 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 856 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 857 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 858 #ifdef CONFIG_CMD_KGDB
 859 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 860 #else
 861 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 862 #endif
 863 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 864 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 865 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 866
 867 /*
 868  * For booting Linux, the board info and command line data
 869  * have to be in the first 64 MB of memory, since this is
 870  * the maximum mapped by the Linux kernel during initialization.
 871  */
 872 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 873 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 874
 875 #ifdef CONFIG_CMD_KGDB
 876 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 877 #endif
 878
 879 /*
 880  * Environment Configuration
 881  */
 882 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 883 #define CONFIG_BOOTFILE         "uImage"
 884 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 885 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 886 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 887 #define CONFIG_BAUDRATE         115200
 888 #define __USB_PHY_TYPE          utmi
 889
 890 #ifdef CONFIG_PPC_T1024
 891 #define CONFIG_BOARDNAME t1024rdb
 892 #define BANK_INTLV cs0_cs1
 893 #else
 894 #define CONFIG_BOARDNAME t1023rdb
 895 #define BANK_INTLV  null
 896 #endif
 897
 898 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 899         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 900         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 901         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 902         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 903         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 904         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 905         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 906         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 907         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 908         "netdev=eth0\0"                                         \
 909         "tftpflash=tftpboot $loadaddr $uboot && "               \
 910         "protect off $ubootaddr +$filesize && "                 \
 911         "erase $ubootaddr +$filesize && "                       \
 912         "cp.b $loadaddr $ubootaddr $filesize && "               \
 913         "protect on $ubootaddr +$filesize && "                  \
 914         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 915         "consoledev=ttyS0\0"                                    \
 916         "ramdiskaddr=2000000\0"                                 \
 917         "fdtaddr=c00000\0"                                      \
 918         "bdev=sda3\0"
 919
 920 #define CONFIG_LINUX                                    \
 921         "setenv bootargs root=/dev/ram rw "             \
 922         "console=$consoledev,$baudrate $othbootargs;"   \
 923         "setenv ramdiskaddr 0x02000000;"                \
 924         "setenv fdtaddr 0x00c00000;"                    \
 925         "setenv loadaddr 0x1000000;"                    \
 926         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 927
 928
 929 #define CONFIG_NFSBOOTCOMMAND                   \
 930         "setenv bootargs root=/dev/nfs rw "     \
 931         "nfsroot=$serverip:$rootpath "          \
 932         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 933         "console=$consoledev,$baudrate $othbootargs;"   \
 934         "tftp $loadaddr $bootfile;"             \
 935         "tftp $fdtaddr $fdtfile;"               \
 936         "bootm $loadaddr - $fdtaddr"
 937
 938 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 939
 940 /* Hash command with SHA acceleration supported in hardware */
 941 #ifdef CONFIG_FSL_CAAM
 942 #define CONFIG_CMD_HASH
 943 #define CONFIG_SHA_HW_ACCEL
 944 #endif
 945
 946 #include <asm/fsl_secure_boot.h>
 947
 948 #endif  /* __T1024RDB_H */