include/configs/T1040QDS.h

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * T1040 QDS board configuration file
  28  */
  29
  30 #ifdef CONFIG_RAMBOOT_PBL
  31 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  35 #endif
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  39 #define CONFIG_MP                       /* support multiple processors */
  40
  41 /* support deep sleep */
  42 #define CONFIG_DEEP_SLEEP
  43
  44 #ifndef CONFIG_SYS_TEXT_BASE
  45 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  46 #endif
  47
  48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  50 #endif
  51
  52 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  53 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  54 #define CONFIG_PCI_INDIRECT_BRIDGE
  55 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  56 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  57 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  58 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  59
  60 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  61 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  62
  63 #define CONFIG_ENV_OVERWRITE
  64
  65 #ifndef CONFIG_MTD_NOR_FLASH
  66 #else
  67 #define CONFIG_FLASH_CFI_DRIVER
  68 #define CONFIG_SYS_FLASH_CFI
  69 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  70 #endif
  71
  72 #ifdef CONFIG_MTD_NOR_FLASH
  73 #if defined(CONFIG_SPIFLASH)
  74 #define CONFIG_SYS_EXTRA_ENV_RELOC
  75 #define CONFIG_ENV_SPI_BUS              0
  76 #define CONFIG_ENV_SPI_CS               0
  77 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  78 #define CONFIG_ENV_SPI_MODE             0
  79 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  80 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  81 #define CONFIG_ENV_SECT_SIZE            0x10000
  82 #elif defined(CONFIG_SDCARD)
  83 #define CONFIG_SYS_EXTRA_ENV_RELOC
  84 #define CONFIG_SYS_MMC_ENV_DEV          0
  85 #define CONFIG_ENV_SIZE                 0x2000
  86 #define CONFIG_ENV_OFFSET               (512 * 1658)
  87 #elif defined(CONFIG_NAND)
  88 #define CONFIG_SYS_EXTRA_ENV_RELOC
  89 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  90 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  91 #else
  92 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  93 #define CONFIG_ENV_SIZE         0x2000
  94 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  95 #endif
  96 #else /* CONFIG_MTD_NOR_FLASH */
  97 #define CONFIG_ENV_SIZE                0x2000
  98 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
  99 #endif
 100
 101 #ifndef __ASSEMBLY__
 102 unsigned long get_board_sys_clk(void);
 103 unsigned long get_board_ddr_clk(void);
 104 #endif
 105
 106 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 107 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 108
 109 /*
 110  * These can be toggled for performance analysis, otherwise use default.
 111  */
 112 #define CONFIG_SYS_CACHE_STASHING
 113 #define CONFIG_BACKSIDE_L2_CACHE
 114 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 115 #define CONFIG_BTB                      /* toggle branch predition */
 116 #define CONFIG_DDR_ECC
 117 #ifdef CONFIG_DDR_ECC
 118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 119 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 120 #endif
 121
 122 #define CONFIG_ENABLE_36BIT_PHYS
 123
 124 #define CONFIG_ADDR_MAP
 125 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 126
 127 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 128 #define CONFIG_SYS_MEMTEST_END          0x00400000
 129 #define CONFIG_SYS_ALT_MEMTEST
 130 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 131
 132 /*
 133  *  Config the L3 Cache as L3 SRAM
 134  */
 135 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 136
 137 #define CONFIG_SYS_DCSRBAR              0xf0000000
 138 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 139
 140 /* EEPROM */
 141 #define CONFIG_ID_EEPROM
 142 #define CONFIG_SYS_I2C_EEPROM_NXID
 143 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 144 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 145 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 146 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 147 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 148
 149 /*
 150  * DDR Setup
 151  */
 152 #define CONFIG_VERY_BIG_RAM
 153 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 154 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 155
 156 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 157 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 158
 159 #define CONFIG_DDR_SPD
 160 #define CONFIG_FSL_DDR_INTERACTIVE
 161
 162 #define CONFIG_SYS_SPD_BUS_NUM  0
 163 #define SPD_EEPROM_ADDRESS      0x51
 164
 165 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 166
 167 /*
 168  * IFC Definitions
 169  */
 170 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 171 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 172
 173 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 174 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 175                                 + 0x8000000) | \
 176                                 CSPR_PORT_SIZE_16 | \
 177                                 CSPR_MSEL_NOR | \
 178                                 CSPR_V)
 179 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 180 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 181                                 CSPR_PORT_SIZE_16 | \
 182                                 CSPR_MSEL_NOR | \
 183                                 CSPR_V)
 184 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 185
 186 /*
 187  * TDM Definition
 188  */
 189 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 190
 191 /* NOR Flash Timing Params */
 192 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 193 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 194                                 FTIM0_NOR_TEADC(0x5) | \
 195                                 FTIM0_NOR_TEAHC(0x5))
 196 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 197                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 198                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 199 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 200                                 FTIM2_NOR_TCH(0x4) | \
 201                                 FTIM2_NOR_TWPH(0x0E) | \
 202                                 FTIM2_NOR_TWP(0x1c))
 203 #define CONFIG_SYS_NOR_FTIM3    0x0
 204
 205 #define CONFIG_SYS_FLASH_QUIET_TEST
 206 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 207
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 212
 213 #define CONFIG_SYS_FLASH_EMPTY_INFO
 214 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 215                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 216 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 217 #define QIXIS_BASE              0xffdf0000
 218 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 219 #define QIXIS_LBMAP_SWITCH              0x06
 220 #define QIXIS_LBMAP_MASK                0x0f
 221 #define QIXIS_LBMAP_SHIFT               0
 222 #define QIXIS_LBMAP_DFLTBANK            0x00
 223 #define QIXIS_LBMAP_ALTBANK             0x04
 224 #define QIXIS_RST_CTL_RESET             0x31
 225 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 226 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 227 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 228 #define QIXIS_RST_FORCE_MEM             0x01
 229
 230 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 231 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 232                                 | CSPR_PORT_SIZE_8 \
 233                                 | CSPR_MSEL_GPCM \
 234                                 | CSPR_V)
 235 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 236 #define CONFIG_SYS_CSOR3        0x0
 237 /* QIXIS Timing parameters for IFC CS3 */
 238 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 239                                         FTIM0_GPCM_TEADC(0x0e) | \
 240                                         FTIM0_GPCM_TEAHC(0x0e))
 241 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 242                                         FTIM1_GPCM_TRAD(0x3f))
 243 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 244                                         FTIM2_GPCM_TCH(0x8) | \
 245                                         FTIM2_GPCM_TWP(0x1f))
 246 #define CONFIG_SYS_CS3_FTIM3            0x0
 247
 248 #define CONFIG_NAND_FSL_IFC
 249 #define CONFIG_SYS_NAND_BASE            0xff800000
 250 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 251
 252 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 253 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 254                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 255                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 256                                 | CSPR_V)
 257 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 258
 259 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 260                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 261                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 262                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 263                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 264                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 265                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 266
 267 #define CONFIG_SYS_NAND_ONFI_DETECTION
 268
 269 /* ONFI NAND Flash mode0 Timing Params */
 270 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 271                                         FTIM0_NAND_TWP(0x18)   | \
 272                                         FTIM0_NAND_TWCHT(0x07) | \
 273                                         FTIM0_NAND_TWH(0x0a))
 274 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 275                                         FTIM1_NAND_TWBE(0x39)  | \
 276                                         FTIM1_NAND_TRR(0x0e)   | \
 277                                         FTIM1_NAND_TRP(0x18))
 278 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 279                                         FTIM2_NAND_TREH(0x0a) | \
 280                                         FTIM2_NAND_TWHRE(0x1e))
 281 #define CONFIG_SYS_NAND_FTIM3           0x0
 282
 283 #define CONFIG_SYS_NAND_DDR_LAW         11
 284 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 285 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 286
 287 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 288
 289 #if defined(CONFIG_NAND)
 290 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 291 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 292 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 293 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 294 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 295 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 296 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 297 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 298 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 299 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 300 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 301 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 302 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 303 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 304 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 305 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 306 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 307 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 308 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 309 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 310 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 311 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 312 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 313 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 314 #else
 315 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 316 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 317 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 318 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 319 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 320 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 321 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 322 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 323 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 324 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 325 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 326 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 327 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 328 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 329 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 330 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 331 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 332 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 333 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 334 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 335 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 336 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 337 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 338 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 339 #endif
 340
 341 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 342
 343 #if defined(CONFIG_RAMBOOT_PBL)
 344 #define CONFIG_SYS_RAMBOOT
 345 #endif
 346
 347 #define CONFIG_BOARD_EARLY_INIT_R
 348 #define CONFIG_MISC_INIT_R
 349
 350 #define CONFIG_HWCONFIG
 351
 352 /* define to use L1 as initial stack */
 353 #define CONFIG_L1_INIT_RAM
 354 #define CONFIG_SYS_INIT_RAM_LOCK
 355 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 357 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 358 /* The assembler doesn't like typecast */
 359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 360         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 361           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 362 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 363
 364 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 365                                         GENERATED_GBL_DATA_SIZE)
 366 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 367
 368 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 369 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 370
 371 /* Serial Port - controlled on board with jumper J8
 372  * open - index 2
 373  * shorted - index 1
 374  */
 375 #define CONFIG_CONS_INDEX       1
 376 #define CONFIG_SYS_NS16550_SERIAL
 377 #define CONFIG_SYS_NS16550_REG_SIZE     1
 378 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 379
 380 #define CONFIG_SYS_BAUDRATE_TABLE       \
 381         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 382
 383 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 384 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 385 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 386 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 387
 388 /* Video */
 389 #define CONFIG_FSL_DIU_FB
 390 #ifdef CONFIG_FSL_DIU_FB
 391 #define CONFIG_FSL_DIU_CH7301
 392 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 393 #define CONFIG_VIDEO_LOGO
 394 #define CONFIG_VIDEO_BMP_LOGO
 395 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 396 /*
 397  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 398  * disable empty flash sector detection, which is I/O-intensive.
 399  */
 400 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 401 #endif
 402
 403 /* I2C */
 404 #define CONFIG_SYS_I2C
 405 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 406 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 407 #define CONFIG_SYS_FSL_I2C2_SPEED       50000
 408 #define CONFIG_SYS_FSL_I2C3_SPEED       50000
 409 #define CONFIG_SYS_FSL_I2C4_SPEED       50000
 410 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 411 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 412 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 413 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 414 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 415 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 416 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 417 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 418
 419 #define I2C_MUX_PCA_ADDR                0x77
 420 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 421
 422 /* I2C bus multiplexer */
 423 #define I2C_MUX_CH_DEFAULT      0x8
 424 #define I2C_MUX_CH_DIU          0xC
 425
 426 /* LDI/DVI Encoder for display */
 427 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 428 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 429
 430 /*
 431  * RTC configuration
 432  */
 433 #define RTC
 434 #define CONFIG_RTC_DS3231               1
 435 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 436
 437 /*
 438  * eSPI - Enhanced SPI
 439  */
 440 #define CONFIG_SF_DEFAULT_SPEED         10000000
 441 #define CONFIG_SF_DEFAULT_MODE          0
 442
 443 /*
 444  * General PCI
 445  * Memory space is mapped 1-1, but I/O space must start from 0.
 446  */
 447
 448 #ifdef CONFIG_PCI
 449 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 450 #ifdef CONFIG_PCIE1
 451 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 452 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 453 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 454 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 455 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 456 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 457 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 458 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 459 #endif
 460
 461 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 462 #ifdef CONFIG_PCIE2
 463 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 464 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 465 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 466 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 467 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 468 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 469 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 470 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 471 #endif
 472
 473 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 474 #ifdef CONFIG_PCIE3
 475 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 476 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 477 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 478 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 479 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 480 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 481 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 482 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 483 #endif
 484
 485 /* controller 4, Base address 203000 */
 486 #ifdef CONFIG_PCIE4
 487 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 488 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 489 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 490 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 491 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 492 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 493 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 494 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 495 #endif
 496
 497 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 498 #endif  /* CONFIG_PCI */
 499
 500 /* SATA */
 501 #define CONFIG_FSL_SATA_V2
 502 #ifdef CONFIG_FSL_SATA_V2
 503 #define CONFIG_LIBATA
 504 #define CONFIG_FSL_SATA
 505
 506 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 507 #define CONFIG_SATA1
 508 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 509 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 510 #define CONFIG_SATA2
 511 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 512 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 513
 514 #define CONFIG_LBA48
 515 #endif
 516
 517 /*
 518 * USB
 519 */
 520 #define CONFIG_HAS_FSL_DR_USB
 521
 522 #ifdef CONFIG_HAS_FSL_DR_USB
 523 #ifdef CONFIG_USB_EHCI_HCD
 524 #define CONFIG_USB_EHCI_FSL
 525 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 526 #endif
 527 #endif
 528
 529 #ifdef CONFIG_MMC
 530 #define CONFIG_FSL_ESDHC
 531 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 532 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 533 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 534 #endif
 535
 536 /* Qman/Bman */
 537 #ifndef CONFIG_NOBQFMAN
 538 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 539 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 540 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 541 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 542 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 543 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 544 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 545 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 546 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 547 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 548                                         CONFIG_SYS_BMAN_CENA_SIZE)
 549 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 550 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 551 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 552 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 553 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 554 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 555 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 556 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 557 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 558 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 559 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 560                                         CONFIG_SYS_QMAN_CENA_SIZE)
 561 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 562 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 563
 564 #define CONFIG_SYS_DPAA_FMAN
 565 #define CONFIG_SYS_DPAA_PME
 566
 567 #define CONFIG_QE
 568 #define CONFIG_U_QE
 569 /* Default address of microcode for the Linux Fman driver */
 570 #if defined(CONFIG_SPIFLASH)
 571 /*
 572  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 573  * env, so we got 0x110000.
 574  */
 575 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 576 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 577 #elif defined(CONFIG_SDCARD)
 578 /*
 579  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 580  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 581  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 582  */
 583 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 584 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 585 #elif defined(CONFIG_NAND)
 586 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 587 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 588 #else
 589 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 590 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 591 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 592 #endif
 593 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 594 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 595 #endif /* CONFIG_NOBQFMAN */
 596
 597 #ifdef CONFIG_SYS_DPAA_FMAN
 598 #define CONFIG_FMAN_ENET
 599 #define CONFIG_PHYLIB_10G
 600 #define CONFIG_PHY_VITESSE
 601 #define CONFIG_PHY_REALTEK
 602 #define CONFIG_PHY_TERANETICS
 603 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 604 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 605 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 606 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 607 #endif
 608
 609 #ifdef CONFIG_FMAN_ENET
 610 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
 611 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
 612
 613 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 614 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 615 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 616 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 617
 618 #define CONFIG_MII              /* MII PHY management */
 619 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 620 #endif
 621
 622 /* Enable VSC9953 L2 Switch driver */
 623 #define CONFIG_VSC9953
 624 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x14
 625 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x18
 626
 627 /*
 628  * Dynamic MTD Partition support with mtdparts
 629  */
 630 #ifdef CONFIG_MTD_NOR_FLASH
 631 #define CONFIG_MTD_DEVICE
 632 #define CONFIG_MTD_PARTITIONS
 633 #define CONFIG_FLASH_CFI_MTD
 634 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 635                         "spi0=spife110000.0"
 636 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 637                                 "128k(dtb),96m(fs),-(user);"\
 638                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 639                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 640                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 641 #endif
 642
 643 /*
 644  * Environment
 645  */
 646 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 647 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 648
 649 /*
 650  * Miscellaneous configurable options
 651  */
 652 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 653 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 654 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 655 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 656 #ifdef CONFIG_CMD_KGDB
 657 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 658 #else
 659 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 660 #endif
 661 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 662 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 663 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 664
 665 /*
 666  * For booting Linux, the board info and command line data
 667  * have to be in the first 64 MB of memory, since this is
 668  * the maximum mapped by the Linux kernel during initialization.
 669  */
 670 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 671 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 672
 673 #ifdef CONFIG_CMD_KGDB
 674 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 675 #endif
 676
 677 /*
 678  * Environment Configuration
 679  */
 680 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 681 #define CONFIG_BOOTFILE         "uImage"
 682 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 683
 684 /* default location for tftp and bootm */
 685 #define CONFIG_LOADADDR         1000000
 686
 687 #define __USB_PHY_TYPE  utmi
 688
 689 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 690         "hwconfig=fsl_ddr:bank_intlv=auto;"                     \
 691         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 692         "netdev=eth0\0"                                         \
 693         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 694         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 695         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 696         "tftpflash=tftpboot $loadaddr $uboot && "               \
 697         "protect off $ubootaddr +$filesize && "                 \
 698         "erase $ubootaddr +$filesize && "                       \
 699         "cp.b $loadaddr $ubootaddr $filesize && "               \
 700         "protect on $ubootaddr +$filesize && "                  \
 701         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 702         "consoledev=ttyS0\0"                                    \
 703         "ramdiskaddr=2000000\0"                                 \
 704         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
 705         "fdtaddr=1e00000\0"                                     \
 706         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
 707         "bdev=sda3\0"
 708
 709 #define CONFIG_LINUX                       \
 710         "setenv bootargs root=/dev/ram rw "            \
 711         "console=$consoledev,$baudrate $othbootargs;"  \
 712         "setenv ramdiskaddr 0x02000000;"               \
 713         "setenv fdtaddr 0x00c00000;"                   \
 714         "setenv loadaddr 0x1000000;"                   \
 715         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 716
 717 #define CONFIG_HDBOOT                                   \
 718         "setenv bootargs root=/dev/$bdev rw "           \
 719         "console=$consoledev,$baudrate $othbootargs;"   \
 720         "tftp $loadaddr $bootfile;"                     \
 721         "tftp $fdtaddr $fdtfile;"                       \
 722         "bootm $loadaddr - $fdtaddr"
 723
 724 #define CONFIG_NFSBOOTCOMMAND                   \
 725         "setenv bootargs root=/dev/nfs rw "     \
 726         "nfsroot=$serverip:$rootpath "          \
 727         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 728         "console=$consoledev,$baudrate $othbootargs;"   \
 729         "tftp $loadaddr $bootfile;"             \
 730         "tftp $fdtaddr $fdtfile;"               \
 731         "bootm $loadaddr - $fdtaddr"
 732
 733 #define CONFIG_RAMBOOTCOMMAND                           \
 734         "setenv bootargs root=/dev/ram rw "             \
 735         "console=$consoledev,$baudrate $othbootargs;"   \
 736         "tftp $ramdiskaddr $ramdiskfile;"               \
 737         "tftp $loadaddr $bootfile;"                     \
 738         "tftp $fdtaddr $fdtfile;"                       \
 739         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 740
 741 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 742
 743 #include <asm/fsl_secure_boot.h>
 744
 745 #endif  /* __CONFIG_H */