include/configs/T1040QDS.h

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * T1040 QDS board configuration file
  28  */
  29
  30 #ifdef CONFIG_RAMBOOT_PBL
  31 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  35 #endif
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  39 #define CONFIG_MP                       /* support multiple processors */
  40
  41 /* support deep sleep */
  42 #define CONFIG_DEEP_SLEEP
  43
  44 #ifndef CONFIG_SYS_TEXT_BASE
  45 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  46 #endif
  47
  48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  50 #endif
  51
  52 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  53 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  54 #define CONFIG_PCI_INDIRECT_BRIDGE
  55 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  56 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  57 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  58 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  59
  60 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  61 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  62
  63 #define CONFIG_ENV_OVERWRITE
  64
  65 #ifndef CONFIG_MTD_NOR_FLASH
  66 #else
  67 #define CONFIG_FLASH_CFI_DRIVER
  68 #define CONFIG_SYS_FLASH_CFI
  69 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  70 #endif
  71
  72 #ifdef CONFIG_MTD_NOR_FLASH
  73 #if defined(CONFIG_SPIFLASH)
  74 #define CONFIG_SYS_EXTRA_ENV_RELOC
  75 #define CONFIG_ENV_IS_IN_SPI_FLASH
  76 #define CONFIG_ENV_SPI_BUS              0
  77 #define CONFIG_ENV_SPI_CS               0
  78 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  79 #define CONFIG_ENV_SPI_MODE             0
  80 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  81 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  82 #define CONFIG_ENV_SECT_SIZE            0x10000
  83 #elif defined(CONFIG_SDCARD)
  84 #define CONFIG_SYS_EXTRA_ENV_RELOC
  85 #define CONFIG_SYS_MMC_ENV_DEV          0
  86 #define CONFIG_ENV_SIZE                 0x2000
  87 #define CONFIG_ENV_OFFSET               (512 * 1658)
  88 #elif defined(CONFIG_NAND)
  89 #define CONFIG_SYS_EXTRA_ENV_RELOC
  90 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  91 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  92 #else
  93 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  94 #define CONFIG_ENV_SIZE         0x2000
  95 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  96 #endif
  97 #else /* CONFIG_MTD_NOR_FLASH */
  98 #define CONFIG_ENV_SIZE                0x2000
  99 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 100 #endif
 101
 102 #ifndef __ASSEMBLY__
 103 unsigned long get_board_sys_clk(void);
 104 unsigned long get_board_ddr_clk(void);
 105 #endif
 106
 107 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 108 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 109
 110 /*
 111  * These can be toggled for performance analysis, otherwise use default.
 112  */
 113 #define CONFIG_SYS_CACHE_STASHING
 114 #define CONFIG_BACKSIDE_L2_CACHE
 115 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 116 #define CONFIG_BTB                      /* toggle branch predition */
 117 #define CONFIG_DDR_ECC
 118 #ifdef CONFIG_DDR_ECC
 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 120 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 121 #endif
 122
 123 #define CONFIG_ENABLE_36BIT_PHYS
 124
 125 #define CONFIG_ADDR_MAP
 126 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 127
 128 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 129 #define CONFIG_SYS_MEMTEST_END          0x00400000
 130 #define CONFIG_SYS_ALT_MEMTEST
 131 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 132
 133 /*
 134  *  Config the L3 Cache as L3 SRAM
 135  */
 136 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 137
 138 #define CONFIG_SYS_DCSRBAR              0xf0000000
 139 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 140
 141 /* EEPROM */
 142 #define CONFIG_ID_EEPROM
 143 #define CONFIG_SYS_I2C_EEPROM_NXID
 144 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 145 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 147 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 149
 150 /*
 151  * DDR Setup
 152  */
 153 #define CONFIG_VERY_BIG_RAM
 154 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 155 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 156
 157 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 158 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 159
 160 #define CONFIG_DDR_SPD
 161 #define CONFIG_FSL_DDR_INTERACTIVE
 162
 163 #define CONFIG_SYS_SPD_BUS_NUM  0
 164 #define SPD_EEPROM_ADDRESS      0x51
 165
 166 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 167
 168 /*
 169  * IFC Definitions
 170  */
 171 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 172 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 173
 174 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 175 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 176                                 + 0x8000000) | \
 177                                 CSPR_PORT_SIZE_16 | \
 178                                 CSPR_MSEL_NOR | \
 179                                 CSPR_V)
 180 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 181 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 182                                 CSPR_PORT_SIZE_16 | \
 183                                 CSPR_MSEL_NOR | \
 184                                 CSPR_V)
 185 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 186
 187 /*
 188  * TDM Definition
 189  */
 190 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 191
 192 /* NOR Flash Timing Params */
 193 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 194 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 195                                 FTIM0_NOR_TEADC(0x5) | \
 196                                 FTIM0_NOR_TEAHC(0x5))
 197 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 198                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 199                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 200 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 201                                 FTIM2_NOR_TCH(0x4) | \
 202                                 FTIM2_NOR_TWPH(0x0E) | \
 203                                 FTIM2_NOR_TWP(0x1c))
 204 #define CONFIG_SYS_NOR_FTIM3    0x0
 205
 206 #define CONFIG_SYS_FLASH_QUIET_TEST
 207 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 208
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 210 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 211 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 212 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 213
 214 #define CONFIG_SYS_FLASH_EMPTY_INFO
 215 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 216                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 217 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 218 #define QIXIS_BASE              0xffdf0000
 219 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 220 #define QIXIS_LBMAP_SWITCH              0x06
 221 #define QIXIS_LBMAP_MASK                0x0f
 222 #define QIXIS_LBMAP_SHIFT               0
 223 #define QIXIS_LBMAP_DFLTBANK            0x00
 224 #define QIXIS_LBMAP_ALTBANK             0x04
 225 #define QIXIS_RST_CTL_RESET             0x31
 226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 227 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 229 #define QIXIS_RST_FORCE_MEM             0x01
 230
 231 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 232 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 233                                 | CSPR_PORT_SIZE_8 \
 234                                 | CSPR_MSEL_GPCM \
 235                                 | CSPR_V)
 236 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 237 #define CONFIG_SYS_CSOR3        0x0
 238 /* QIXIS Timing parameters for IFC CS3 */
 239 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 240                                         FTIM0_GPCM_TEADC(0x0e) | \
 241                                         FTIM0_GPCM_TEAHC(0x0e))
 242 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 243                                         FTIM1_GPCM_TRAD(0x3f))
 244 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 245                                         FTIM2_GPCM_TCH(0x8) | \
 246                                         FTIM2_GPCM_TWP(0x1f))
 247 #define CONFIG_SYS_CS3_FTIM3            0x0
 248
 249 #define CONFIG_NAND_FSL_IFC
 250 #define CONFIG_SYS_NAND_BASE            0xff800000
 251 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 252
 253 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 254 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 255                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 256                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 257                                 | CSPR_V)
 258 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 259
 260 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 261                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 262                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 263                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 264                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 265                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 266                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 267
 268 #define CONFIG_SYS_NAND_ONFI_DETECTION
 269
 270 /* ONFI NAND Flash mode0 Timing Params */
 271 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 272                                         FTIM0_NAND_TWP(0x18)   | \
 273                                         FTIM0_NAND_TWCHT(0x07) | \
 274                                         FTIM0_NAND_TWH(0x0a))
 275 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 276                                         FTIM1_NAND_TWBE(0x39)  | \
 277                                         FTIM1_NAND_TRR(0x0e)   | \
 278                                         FTIM1_NAND_TRP(0x18))
 279 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 280                                         FTIM2_NAND_TREH(0x0a) | \
 281                                         FTIM2_NAND_TWHRE(0x1e))
 282 #define CONFIG_SYS_NAND_FTIM3           0x0
 283
 284 #define CONFIG_SYS_NAND_DDR_LAW         11
 285 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 286 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 287 #define CONFIG_CMD_NAND
 288
 289 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 290
 291 #if defined(CONFIG_NAND)
 292 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 293 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 294 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 295 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 296 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 297 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 298 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 299 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 300 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 301 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 302 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 303 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 304 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 305 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 306 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 307 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 308 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 309 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 310 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 311 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 312 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 313 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 314 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 315 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 316 #else
 317 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 318 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 319 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 320 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 321 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 322 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 323 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 324 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 325 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 326 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 327 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 328 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 329 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 330 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 331 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 332 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 333 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 334 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 335 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 336 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 337 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 338 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 339 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 340 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 341 #endif
 342
 343 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 344
 345 #if defined(CONFIG_RAMBOOT_PBL)
 346 #define CONFIG_SYS_RAMBOOT
 347 #endif
 348
 349 #define CONFIG_BOARD_EARLY_INIT_R
 350 #define CONFIG_MISC_INIT_R
 351
 352 #define CONFIG_HWCONFIG
 353
 354 /* define to use L1 as initial stack */
 355 #define CONFIG_L1_INIT_RAM
 356 #define CONFIG_SYS_INIT_RAM_LOCK
 357 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 358 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 360 /* The assembler doesn't like typecast */
 361 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 362         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 363           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 364 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 365
 366 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 367                                         GENERATED_GBL_DATA_SIZE)
 368 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 369
 370 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 371 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 372
 373 /* Serial Port - controlled on board with jumper J8
 374  * open - index 2
 375  * shorted - index 1
 376  */
 377 #define CONFIG_CONS_INDEX       1
 378 #define CONFIG_SYS_NS16550_SERIAL
 379 #define CONFIG_SYS_NS16550_REG_SIZE     1
 380 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 381
 382 #define CONFIG_SYS_BAUDRATE_TABLE       \
 383         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 384
 385 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 386 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 387 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 388 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 389
 390 /* Video */
 391 #define CONFIG_FSL_DIU_FB
 392 #ifdef CONFIG_FSL_DIU_FB
 393 #define CONFIG_FSL_DIU_CH7301
 394 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 395 #define CONFIG_VIDEO_LOGO
 396 #define CONFIG_VIDEO_BMP_LOGO
 397 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 398 /*
 399  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 400  * disable empty flash sector detection, which is I/O-intensive.
 401  */
 402 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 403 #endif
 404
 405 /* I2C */
 406 #define CONFIG_SYS_I2C
 407 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 408 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 409 #define CONFIG_SYS_FSL_I2C2_SPEED       50000
 410 #define CONFIG_SYS_FSL_I2C3_SPEED       50000
 411 #define CONFIG_SYS_FSL_I2C4_SPEED       50000
 412 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 413 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 414 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 415 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 416 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 417 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 418 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 419 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 420
 421 #define I2C_MUX_PCA_ADDR                0x77
 422 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 423
 424 /* I2C bus multiplexer */
 425 #define I2C_MUX_CH_DEFAULT      0x8
 426 #define I2C_MUX_CH_DIU          0xC
 427
 428 /* LDI/DVI Encoder for display */
 429 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 430 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 431
 432 /*
 433  * RTC configuration
 434  */
 435 #define RTC
 436 #define CONFIG_RTC_DS3231               1
 437 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 438
 439 /*
 440  * eSPI - Enhanced SPI
 441  */
 442 #define CONFIG_SF_DEFAULT_SPEED         10000000
 443 #define CONFIG_SF_DEFAULT_MODE          0
 444
 445 /*
 446  * General PCI
 447  * Memory space is mapped 1-1, but I/O space must start from 0.
 448  */
 449
 450 #ifdef CONFIG_PCI
 451 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 452 #ifdef CONFIG_PCIE1
 453 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 454 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 455 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 456 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 457 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 458 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 459 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 460 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 461 #endif
 462
 463 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 464 #ifdef CONFIG_PCIE2
 465 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 466 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 467 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 468 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 469 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 470 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 471 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 472 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 473 #endif
 474
 475 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 476 #ifdef CONFIG_PCIE3
 477 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 478 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 479 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 480 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 481 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 482 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 483 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 484 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 485 #endif
 486
 487 /* controller 4, Base address 203000 */
 488 #ifdef CONFIG_PCIE4
 489 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 490 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 491 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 492 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 493 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 494 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 495 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 496 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 497 #endif
 498
 499 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 500 #endif  /* CONFIG_PCI */
 501
 502 /* SATA */
 503 #define CONFIG_FSL_SATA_V2
 504 #ifdef CONFIG_FSL_SATA_V2
 505 #define CONFIG_LIBATA
 506 #define CONFIG_FSL_SATA
 507
 508 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 509 #define CONFIG_SATA1
 510 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 511 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 512 #define CONFIG_SATA2
 513 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 514 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 515
 516 #define CONFIG_LBA48
 517 #endif
 518
 519 /*
 520 * USB
 521 */
 522 #define CONFIG_HAS_FSL_DR_USB
 523
 524 #ifdef CONFIG_HAS_FSL_DR_USB
 525 #ifdef CONFIG_USB_EHCI_HCD
 526 #define CONFIG_USB_EHCI_FSL
 527 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 528 #endif
 529 #endif
 530
 531 #ifdef CONFIG_MMC
 532 #define CONFIG_FSL_ESDHC
 533 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 534 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 535 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 536 #endif
 537
 538 /* Qman/Bman */
 539 #ifndef CONFIG_NOBQFMAN
 540 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 541 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 542 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 543 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 544 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 545 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 546 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 547 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 548 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 549 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 550                                         CONFIG_SYS_BMAN_CENA_SIZE)
 551 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 552 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 553 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 554 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 555 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 556 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 557 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 558 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 559 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 560 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 561 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 562                                         CONFIG_SYS_QMAN_CENA_SIZE)
 563 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 564 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 565
 566 #define CONFIG_SYS_DPAA_FMAN
 567 #define CONFIG_SYS_DPAA_PME
 568
 569 #define CONFIG_QE
 570 #define CONFIG_U_QE
 571 /* Default address of microcode for the Linux Fman driver */
 572 #if defined(CONFIG_SPIFLASH)
 573 /*
 574  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 575  * env, so we got 0x110000.
 576  */
 577 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 578 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 579 #elif defined(CONFIG_SDCARD)
 580 /*
 581  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 582  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 583  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 584  */
 585 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 586 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 587 #elif defined(CONFIG_NAND)
 588 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 589 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 590 #else
 591 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 592 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 593 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 594 #endif
 595 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 596 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 597 #endif /* CONFIG_NOBQFMAN */
 598
 599 #ifdef CONFIG_SYS_DPAA_FMAN
 600 #define CONFIG_FMAN_ENET
 601 #define CONFIG_PHYLIB_10G
 602 #define CONFIG_PHY_VITESSE
 603 #define CONFIG_PHY_REALTEK
 604 #define CONFIG_PHY_TERANETICS
 605 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 606 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 607 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 608 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 609 #endif
 610
 611 #ifdef CONFIG_FMAN_ENET
 612 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
 613 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
 614
 615 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 616 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 617 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 618 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 619
 620 #define CONFIG_MII              /* MII PHY management */
 621 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 622 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 623 #endif
 624
 625 /* Enable VSC9953 L2 Switch driver */
 626 #define CONFIG_VSC9953
 627 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x14
 628 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x18
 629
 630 /*
 631  * Dynamic MTD Partition support with mtdparts
 632  */
 633 #ifdef CONFIG_MTD_NOR_FLASH
 634 #define CONFIG_MTD_DEVICE
 635 #define CONFIG_MTD_PARTITIONS
 636 #define CONFIG_FLASH_CFI_MTD
 637 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 638                         "spi0=spife110000.0"
 639 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 640                                 "128k(dtb),96m(fs),-(user);"\
 641                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 642                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 643                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 644 #endif
 645
 646 /*
 647  * Environment
 648  */
 649 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 650 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 651
 652 /*
 653  * Command line configuration.
 654  */
 655 #define CONFIG_CMD_REGINFO
 656
 657 #ifdef CONFIG_PCI
 658 #define CONFIG_CMD_PCI
 659 #endif
 660
 661 /*
 662  * Miscellaneous configurable options
 663  */
 664 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 665 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 666 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 667 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 668 #ifdef CONFIG_CMD_KGDB
 669 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 670 #else
 671 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 672 #endif
 673 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 674 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 675 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 676
 677 /*
 678  * For booting Linux, the board info and command line data
 679  * have to be in the first 64 MB of memory, since this is
 680  * the maximum mapped by the Linux kernel during initialization.
 681  */
 682 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 683 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 684
 685 #ifdef CONFIG_CMD_KGDB
 686 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 687 #endif
 688
 689 /*
 690  * Environment Configuration
 691  */
 692 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 693 #define CONFIG_BOOTFILE         "uImage"
 694 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 695
 696 /* default location for tftp and bootm */
 697 #define CONFIG_LOADADDR         1000000
 698
 699 #define __USB_PHY_TYPE  utmi
 700
 701 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 702         "hwconfig=fsl_ddr:bank_intlv=auto;"                     \
 703         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 704         "netdev=eth0\0"                                         \
 705         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 706         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 707         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 708         "tftpflash=tftpboot $loadaddr $uboot && "               \
 709         "protect off $ubootaddr +$filesize && "                 \
 710         "erase $ubootaddr +$filesize && "                       \
 711         "cp.b $loadaddr $ubootaddr $filesize && "               \
 712         "protect on $ubootaddr +$filesize && "                  \
 713         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 714         "consoledev=ttyS0\0"                                    \
 715         "ramdiskaddr=2000000\0"                                 \
 716         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
 717         "fdtaddr=1e00000\0"                                     \
 718         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
 719         "bdev=sda3\0"
 720
 721 #define CONFIG_LINUX                       \
 722         "setenv bootargs root=/dev/ram rw "            \
 723         "console=$consoledev,$baudrate $othbootargs;"  \
 724         "setenv ramdiskaddr 0x02000000;"               \
 725         "setenv fdtaddr 0x00c00000;"                   \
 726         "setenv loadaddr 0x1000000;"                   \
 727         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 728
 729 #define CONFIG_HDBOOT                                   \
 730         "setenv bootargs root=/dev/$bdev rw "           \
 731         "console=$consoledev,$baudrate $othbootargs;"   \
 732         "tftp $loadaddr $bootfile;"                     \
 733         "tftp $fdtaddr $fdtfile;"                       \
 734         "bootm $loadaddr - $fdtaddr"
 735
 736 #define CONFIG_NFSBOOTCOMMAND                   \
 737         "setenv bootargs root=/dev/nfs rw "     \
 738         "nfsroot=$serverip:$rootpath "          \
 739         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 740         "console=$consoledev,$baudrate $othbootargs;"   \
 741         "tftp $loadaddr $bootfile;"             \
 742         "tftp $fdtaddr $fdtfile;"               \
 743         "bootm $loadaddr - $fdtaddr"
 744
 745 #define CONFIG_RAMBOOTCOMMAND                           \
 746         "setenv bootargs root=/dev/ram rw "             \
 747         "console=$consoledev,$baudrate $othbootargs;"   \
 748         "tftp $ramdiskaddr $ramdiskfile;"               \
 749         "tftp $loadaddr $bootfile;"                     \
 750         "tftp $fdtaddr $fdtfile;"                       \
 751         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 752
 753 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 754
 755 #include <asm/fsl_secure_boot.h>
 756
 757 #endif  /* __CONFIG_H */