include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14 #define CONFIG_PHYS_64BIT
  15 #define CONFIG_DISPLAY_BOARDINFO
  16
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #include <asm/config_mpc85xx.h>
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  22 #ifdef CONFIG_T1040RDB
  23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  24 #endif
  25 #ifdef CONFIG_T1042RDB_PI
  26 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
  27 #endif
  28 #ifdef CONFIG_T1042RDB
  29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  30 #endif
  31 #ifdef CONFIG_T1040D4RDB
  32 #define CONFIG_SYS_FSL_PBL_RCW \
  33 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
  34 #endif
  35 #ifdef CONFIG_T1042D4RDB
  36 #define CONFIG_SYS_FSL_PBL_RCW \
  37 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
  38 #endif
  39
  40 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  41 #define CONFIG_SPL_ENV_SUPPORT
  42 #define CONFIG_SPL_SERIAL_SUPPORT
  43 #define CONFIG_SPL_FLUSH_IMAGE
  44 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  45 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  46 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  47 #define CONFIG_SPL_I2C_SUPPORT
  48 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  49 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  50 #define CONFIG_SYS_TEXT_BASE            0x30001000
  51 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  52 #define CONFIG_SPL_PAD_TO               0x40000
  53 #define CONFIG_SPL_MAX_SIZE             0x28000
  54 #ifdef CONFIG_SPL_BUILD
  55 #define CONFIG_SPL_SKIP_RELOCATE
  56 #define CONFIG_SPL_COMMON_INIT_DDR
  57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  58 #define CONFIG_SYS_NO_FLASH
  59 #endif
  60 #define RESET_VECTOR_OFFSET             0x27FFC
  61 #define BOOT_PAGE_OFFSET                0x27000
  62
  63 #ifdef CONFIG_NAND
  64 #define CONFIG_SPL_NAND_SUPPORT
  65 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  66 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  67 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  68 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  69 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  70 #define CONFIG_SPL_NAND_BOOT
  71 #endif
  72
  73 #ifdef CONFIG_SPIFLASH
  74 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  75 #define CONFIG_SPL_SPI_SUPPORT
  76 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  77 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  82 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  83 #ifndef CONFIG_SPL_BUILD
  84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  85 #endif
  86 #define CONFIG_SPL_SPI_BOOT
  87 #endif
  88
  89 #ifdef CONFIG_SDCARD
  90 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  91 #define CONFIG_SPL_MMC_SUPPORT
  92 #define CONFIG_SPL_MMC_MINIMAL
  93 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  94 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  95 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  96 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  97 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  98 #ifndef CONFIG_SPL_BUILD
  99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 100 #endif
 101 #define CONFIG_SPL_MMC_BOOT
 102 #endif
 103
 104 #endif
 105
 106 /* High Level Configuration Options */
 107 #define CONFIG_BOOKE
 108 #define CONFIG_E500MC                   /* BOOKE e500mc family */
 109 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 110 #define CONFIG_MP                       /* support multiple processors */
 111
 112 /* support deep sleep */
 113 #define CONFIG_DEEP_SLEEP
 114 #if defined(CONFIG_DEEP_SLEEP)
 115 #define CONFIG_BOARD_EARLY_INIT_F
 116 #define CONFIG_SILENT_CONSOLE
 117 #endif
 118
 119 #ifndef CONFIG_SYS_TEXT_BASE
 120 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 121 #endif
 122
 123 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 124 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 125 #endif
 126
 127 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 128 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 129 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 130 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 131 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 132 #define CONFIG_PCI_INDIRECT_BRIDGE
 133 #define CONFIG_PCIE1                    /* PCIE controler 1 */
 134 #define CONFIG_PCIE2                    /* PCIE controler 2 */
 135 #define CONFIG_PCIE3                    /* PCIE controler 3 */
 136 #define CONFIG_PCIE4                    /* PCIE controler 4 */
 137
 138 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 139 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 140
 141 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 142
 143 #define CONFIG_ENV_OVERWRITE
 144
 145 #ifndef CONFIG_SYS_NO_FLASH
 146 #define CONFIG_FLASH_CFI_DRIVER
 147 #define CONFIG_SYS_FLASH_CFI
 148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 149 #endif
 150
 151 #if defined(CONFIG_SPIFLASH)
 152 #define CONFIG_SYS_EXTRA_ENV_RELOC
 153 #define CONFIG_ENV_IS_IN_SPI_FLASH
 154 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 155 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 156 #define CONFIG_ENV_SECT_SIZE            0x10000
 157 #elif defined(CONFIG_SDCARD)
 158 #define CONFIG_SYS_EXTRA_ENV_RELOC
 159 #define CONFIG_ENV_IS_IN_MMC
 160 #define CONFIG_SYS_MMC_ENV_DEV          0
 161 #define CONFIG_ENV_SIZE                 0x2000
 162 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 163 #elif defined(CONFIG_NAND)
 164 #define CONFIG_SYS_EXTRA_ENV_RELOC
 165 #define CONFIG_ENV_IS_IN_NAND
 166 #define CONFIG_ENV_SIZE                 0x2000
 167 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 168 #else
 169 #define CONFIG_ENV_IS_IN_FLASH
 170 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 171 #define CONFIG_ENV_SIZE         0x2000
 172 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 173 #endif
 174
 175 #define CONFIG_SYS_CLK_FREQ     100000000
 176 #define CONFIG_DDR_CLK_FREQ     66666666
 177
 178 /*
 179  * These can be toggled for performance analysis, otherwise use default.
 180  */
 181 #define CONFIG_SYS_CACHE_STASHING
 182 #define CONFIG_BACKSIDE_L2_CACHE
 183 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 184 #define CONFIG_BTB                      /* toggle branch predition */
 185 #define CONFIG_DDR_ECC
 186 #ifdef CONFIG_DDR_ECC
 187 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 188 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 189 #endif
 190
 191 #define CONFIG_ENABLE_36BIT_PHYS
 192
 193 #define CONFIG_ADDR_MAP
 194 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 195
 196 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 197 #define CONFIG_SYS_MEMTEST_END          0x00400000
 198 #define CONFIG_SYS_ALT_MEMTEST
 199 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 200
 201 /*
 202  *  Config the L3 Cache as L3 SRAM
 203  */
 204 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 205 #define CONFIG_SYS_L3_SIZE              256 << 10
 206 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 207 #ifdef CONFIG_RAMBOOT_PBL
 208 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 209 #endif
 210 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 211 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 212 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 213 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 214
 215 #define CONFIG_SYS_DCSRBAR              0xf0000000
 216 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 217
 218 /*
 219  * DDR Setup
 220  */
 221 #define CONFIG_VERY_BIG_RAM
 222 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 223 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 224
 225 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 226 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 227 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 228
 229 #define CONFIG_DDR_SPD
 230 #ifndef CONFIG_SYS_FSL_DDR4
 231 #define CONFIG_SYS_FSL_DDR3
 232 #endif
 233
 234 #define CONFIG_SYS_SPD_BUS_NUM  0
 235 #define SPD_EEPROM_ADDRESS      0x51
 236
 237 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 238
 239 /*
 240  * IFC Definitions
 241  */
 242 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 243 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 244
 245 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 246 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 247                                 CSPR_PORT_SIZE_16 | \
 248                                 CSPR_MSEL_NOR | \
 249                                 CSPR_V)
 250 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 251
 252 /*
 253  * TDM Definition
 254  */
 255 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 256
 257 /* NOR Flash Timing Params */
 258 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 259 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 260                                 FTIM0_NOR_TEADC(0x5) | \
 261                                 FTIM0_NOR_TEAHC(0x5))
 262 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 263                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 264                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 265 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 266                                 FTIM2_NOR_TCH(0x4) | \
 267                                 FTIM2_NOR_TWPH(0x0E) | \
 268                                 FTIM2_NOR_TWP(0x1c))
 269 #define CONFIG_SYS_NOR_FTIM3    0x0
 270
 271 #define CONFIG_SYS_FLASH_QUIET_TEST
 272 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 273
 274 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 275 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 276 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 277 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 278
 279 #define CONFIG_SYS_FLASH_EMPTY_INFO
 280 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 281
 282 /* CPLD on IFC */
 283 #define CPLD_LBMAP_MASK                 0x3F
 284 #define CPLD_BANK_SEL_MASK              0x07
 285 #define CPLD_BANK_OVERRIDE              0x40
 286 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 287 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 288 #define CPLD_LBMAP_RESET                0xFF
 289 #define CPLD_LBMAP_SHIFT                0x03
 290
 291 #if defined(CONFIG_T1042RDB_PI)
 292 #define CPLD_DIU_SEL_DFP                0x80
 293 #elif defined(CONFIG_T1042D4RDB)
 294 #define CPLD_DIU_SEL_DFP                0xc0
 295 #endif
 296
 297 #if defined(CONFIG_T1040D4RDB)
 298 #define CPLD_INT_MASK_ALL               0xFF
 299 #define CPLD_INT_MASK_THERM             0x80
 300 #define CPLD_INT_MASK_DVI_DFP           0x40
 301 #define CPLD_INT_MASK_QSGMII1           0x20
 302 #define CPLD_INT_MASK_QSGMII2           0x10
 303 #define CPLD_INT_MASK_SGMI1             0x08
 304 #define CPLD_INT_MASK_SGMI2             0x04
 305 #define CPLD_INT_MASK_TDMR1             0x02
 306 #define CPLD_INT_MASK_TDMR2             0x01
 307 #endif
 308
 309 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 310 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 311 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 312 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 313                                 | CSPR_PORT_SIZE_8 \
 314                                 | CSPR_MSEL_GPCM \
 315                                 | CSPR_V)
 316 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 317 #define CONFIG_SYS_CSOR2        0x0
 318 /* CPLD Timing parameters for IFC CS2 */
 319 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 320                                         FTIM0_GPCM_TEADC(0x0e) | \
 321                                         FTIM0_GPCM_TEAHC(0x0e))
 322 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 323                                         FTIM1_GPCM_TRAD(0x1f))
 324 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 325                                         FTIM2_GPCM_TCH(0x8) | \
 326                                         FTIM2_GPCM_TWP(0x1f))
 327 #define CONFIG_SYS_CS2_FTIM3            0x0
 328
 329 /* NAND Flash on IFC */
 330 #define CONFIG_NAND_FSL_IFC
 331 #define CONFIG_SYS_NAND_BASE            0xff800000
 332 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 333
 334 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 335 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 336                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 337                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 338                                 | CSPR_V)
 339 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 340
 341 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 342                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 343                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 344                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 345                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 346                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 347                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 348
 349 #define CONFIG_SYS_NAND_ONFI_DETECTION
 350
 351 /* ONFI NAND Flash mode0 Timing Params */
 352 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 353                                         FTIM0_NAND_TWP(0x18)   | \
 354                                         FTIM0_NAND_TWCHT(0x07) | \
 355                                         FTIM0_NAND_TWH(0x0a))
 356 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 357                                         FTIM1_NAND_TWBE(0x39)  | \
 358                                         FTIM1_NAND_TRR(0x0e)   | \
 359                                         FTIM1_NAND_TRP(0x18))
 360 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 361                                         FTIM2_NAND_TREH(0x0a) | \
 362                                         FTIM2_NAND_TWHRE(0x1e))
 363 #define CONFIG_SYS_NAND_FTIM3           0x0
 364
 365 #define CONFIG_SYS_NAND_DDR_LAW         11
 366 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 367 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 368 #define CONFIG_CMD_NAND
 369
 370 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 371
 372 #if defined(CONFIG_NAND)
 373 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 374 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 375 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 376 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 377 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 378 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 379 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 380 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 381 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 382 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 383 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 384 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 385 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 386 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 387 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 388 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 389 #else
 390 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 391 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 392 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 393 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 394 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 395 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 396 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 397 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 398 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 399 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 400 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 401 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 402 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 403 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 404 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 405 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 406 #endif
 407
 408 #ifdef CONFIG_SPL_BUILD
 409 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 410 #else
 411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 412 #endif
 413
 414 #if defined(CONFIG_RAMBOOT_PBL)
 415 #define CONFIG_SYS_RAMBOOT
 416 #endif
 417
 418 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 419 #if defined(CONFIG_NAND)
 420 #define CONFIG_A008044_WORKAROUND
 421 #endif
 422 #endif
 423
 424 #define CONFIG_BOARD_EARLY_INIT_R
 425 #define CONFIG_MISC_INIT_R
 426
 427 #define CONFIG_HWCONFIG
 428
 429 /* define to use L1 as initial stack */
 430 #define CONFIG_L1_INIT_RAM
 431 #define CONFIG_SYS_INIT_RAM_LOCK
 432 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 435 /* The assembler doesn't like typecast */
 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 437         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 438           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 439 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 440
 441 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 442                                         GENERATED_GBL_DATA_SIZE)
 443 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 444
 445 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 446 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 447
 448 /* Serial Port - controlled on board with jumper J8
 449  * open - index 2
 450  * shorted - index 1
 451  */
 452 #define CONFIG_CONS_INDEX       1
 453 #define CONFIG_SYS_NS16550_SERIAL
 454 #define CONFIG_SYS_NS16550_REG_SIZE     1
 455 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 456
 457 #define CONFIG_SYS_BAUDRATE_TABLE       \
 458         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 459
 460 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 461 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 462 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 463 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 464 #ifndef CONFIG_SPL_BUILD
 465 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 466 #endif
 467
 468 /* Use the HUSH parser */
 469 #define CONFIG_SYS_HUSH_PARSER
 470 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 471
 472 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
 473 /* Video */
 474 #define CONFIG_FSL_DIU_FB
 475
 476 #ifdef CONFIG_FSL_DIU_FB
 477 #define CONFIG_FSL_DIU_CH7301
 478 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 479 #define CONFIG_VIDEO
 480 #define CONFIG_CMD_BMP
 481 #define CONFIG_CFB_CONSOLE
 482 #define CONFIG_CFB_CONSOLE_ANSI
 483 #define CONFIG_VIDEO_SW_CURSOR
 484 #define CONFIG_VGA_AS_SINGLE_DEVICE
 485 #define CONFIG_VIDEO_LOGO
 486 #define CONFIG_VIDEO_BMP_LOGO
 487 #endif
 488 #endif
 489
 490 /* pass open firmware flat tree */
 491 #define CONFIG_OF_LIBFDT
 492 #define CONFIG_OF_BOARD_SETUP
 493 #define CONFIG_OF_STDOUT_VIA_ALIAS
 494
 495 /* new uImage format support */
 496 #define CONFIG_FIT
 497 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 498
 499 /* I2C */
 500 #define CONFIG_SYS_I2C
 501 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 502 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 503 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 504 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 505 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 506 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 507 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 508 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 509 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 510 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 511 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 512 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 513 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 514
 515 /* I2C bus multiplexer */
 516 #define I2C_MUX_PCA_ADDR                0x70
 517 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 518 #define I2C_MUX_CH_DEFAULT      0x8
 519 #endif
 520
 521 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
 522 /* LDI/DVI Encoder for display */
 523 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 524 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 525
 526 /*
 527  * RTC configuration
 528  */
 529 #define RTC
 530 #define CONFIG_RTC_DS1337               1
 531 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 532
 533 /*DVI encoder*/
 534 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 535 #endif
 536
 537 /*
 538  * eSPI - Enhanced SPI
 539  */
 540 #define CONFIG_FSL_ESPI
 541 #define CONFIG_SPI_FLASH_STMICRO
 542 #define CONFIG_SPI_FLASH_BAR
 543 #define CONFIG_CMD_SF
 544 #define CONFIG_SF_DEFAULT_SPEED         10000000
 545 #define CONFIG_SF_DEFAULT_MODE          0
 546 #define CONFIG_ENV_SPI_BUS              0
 547 #define CONFIG_ENV_SPI_CS               0
 548 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 549 #define CONFIG_ENV_SPI_MODE             0
 550
 551 /*
 552  * General PCI
 553  * Memory space is mapped 1-1, but I/O space must start from 0.
 554  */
 555
 556 #ifdef CONFIG_PCI
 557 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 558 #ifdef CONFIG_PCIE1
 559 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 560 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 561 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 562 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 563 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 564 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 565 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 566 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 567 #endif
 568
 569 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 570 #ifdef CONFIG_PCIE2
 571 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 572 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 573 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 574 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 575 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 576 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 577 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 578 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 579 #endif
 580
 581 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 582 #ifdef CONFIG_PCIE3
 583 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 584 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 585 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 586 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 587 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 588 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 589 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 590 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 591 #endif
 592
 593 /* controller 4, Base address 203000 */
 594 #ifdef CONFIG_PCIE4
 595 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 596 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 597 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 598 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 599 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 600 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 601 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 602 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 603 #endif
 604
 605 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 606
 607 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 608 #define CONFIG_DOS_PARTITION
 609 #endif  /* CONFIG_PCI */
 610
 611 /* SATA */
 612 #define CONFIG_FSL_SATA_V2
 613 #ifdef CONFIG_FSL_SATA_V2
 614 #define CONFIG_LIBATA
 615 #define CONFIG_FSL_SATA
 616
 617 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 618 #define CONFIG_SATA1
 619 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 620 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 621
 622 #define CONFIG_LBA48
 623 #define CONFIG_CMD_SATA
 624 #define CONFIG_DOS_PARTITION
 625 #define CONFIG_CMD_EXT2
 626 #endif
 627
 628 /*
 629 * USB
 630 */
 631 #define CONFIG_HAS_FSL_DR_USB
 632
 633 #ifdef CONFIG_HAS_FSL_DR_USB
 634 #define CONFIG_USB_EHCI
 635
 636 #ifdef CONFIG_USB_EHCI
 637 #define CONFIG_CMD_USB
 638 #define CONFIG_USB_STORAGE
 639 #define CONFIG_USB_EHCI_FSL
 640 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 641 #define CONFIG_CMD_EXT2
 642 #endif
 643 #endif
 644
 645 #define CONFIG_MMC
 646
 647 #ifdef CONFIG_MMC
 648 #define CONFIG_FSL_ESDHC
 649 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 650 #define CONFIG_CMD_MMC
 651 #define CONFIG_GENERIC_MMC
 652 #define CONFIG_CMD_EXT2
 653 #define CONFIG_CMD_FAT
 654 #define CONFIG_DOS_PARTITION
 655 #endif
 656
 657 /* Qman/Bman */
 658 #ifndef CONFIG_NOBQFMAN
 659 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 660 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 661 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 662 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 663 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 664 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 665 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 666 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 667 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 668 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 669                                         CONFIG_SYS_BMAN_CENA_SIZE)
 670 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 671 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 672 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 673 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 674 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 675 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 676 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 677 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 678 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 679 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 680 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 681                                         CONFIG_SYS_QMAN_CENA_SIZE)
 682 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 683 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 684
 685 #define CONFIG_SYS_DPAA_FMAN
 686 #define CONFIG_SYS_DPAA_PME
 687
 688 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 689 #define CONFIG_QE
 690 #define CONFIG_U_QE
 691 #endif
 692
 693 /* Default address of microcode for the Linux Fman driver */
 694 #if defined(CONFIG_SPIFLASH)
 695 /*
 696  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 697  * env, so we got 0x110000.
 698  */
 699 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 700 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 701 #elif defined(CONFIG_SDCARD)
 702 /*
 703  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 704  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 705  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 706  */
 707 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 708 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 709 #elif defined(CONFIG_NAND)
 710 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 711 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 712 #else
 713 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 714 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 715 #endif
 716
 717 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 718 #if defined(CONFIG_SPIFLASH)
 719 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 720 #elif defined(CONFIG_SDCARD)
 721 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 722 #elif defined(CONFIG_NAND)
 723 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 724 #else
 725 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 726 #endif
 727 #endif
 728
 729
 730 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 731 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 732 #endif /* CONFIG_NOBQFMAN */
 733
 734 #ifdef CONFIG_SYS_DPAA_FMAN
 735 #define CONFIG_FMAN_ENET
 736 #define CONFIG_PHY_VITESSE
 737 #define CONFIG_PHY_REALTEK
 738 #endif
 739
 740 #ifdef CONFIG_FMAN_ENET
 741 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 742 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 743 #elif defined(CONFIG_T1040D4RDB)
 744 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 745 #elif defined(CONFIG_T1042D4RDB)
 746 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 747 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 748 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 749 #endif
 750
 751 #ifdef CONFIG_T104XD4RDB
 752 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 753 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 754 #else
 755 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 756 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 757 #endif
 758
 759 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 760 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 761 #define CONFIG_VSC9953
 762 #define CONFIG_CMD_ETHSW
 763 #ifdef CONFIG_T1040RDB
 764 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 765 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 766 #else
 767 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 768 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 769 #endif
 770 #endif
 771
 772 #define CONFIG_MII              /* MII PHY management */
 773 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 774 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 775 #endif
 776
 777 /*
 778  * Environment
 779  */
 780 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 781 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 782
 783 /*
 784  * Command line configuration.
 785  */
 786 #ifdef CONFIG_T1042RDB_PI
 787 #define CONFIG_CMD_DATE
 788 #endif
 789 #define CONFIG_CMD_DHCP
 790 #define CONFIG_CMD_ERRATA
 791 #define CONFIG_CMD_GREPENV
 792 #define CONFIG_CMD_IRQ
 793 #define CONFIG_CMD_I2C
 794 #define CONFIG_CMD_MII
 795 #define CONFIG_CMD_PING
 796 #define CONFIG_CMD_REGINFO
 797
 798 #ifdef CONFIG_PCI
 799 #define CONFIG_CMD_PCI
 800 #endif
 801
 802 /* Hash command with SHA acceleration supported in hardware */
 803 #ifdef CONFIG_FSL_CAAM
 804 #define CONFIG_CMD_HASH
 805 #define CONFIG_SHA_HW_ACCEL
 806 #endif
 807
 808 /*
 809  * Miscellaneous configurable options
 810  */
 811 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 812 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 813 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 814 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 815 #ifdef CONFIG_CMD_KGDB
 816 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 817 #else
 818 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 819 #endif
 820 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 821 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 822 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 823
 824 /*
 825  * For booting Linux, the board info and command line data
 826  * have to be in the first 64 MB of memory, since this is
 827  * the maximum mapped by the Linux kernel during initialization.
 828  */
 829 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 830 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 831
 832 #ifdef CONFIG_CMD_KGDB
 833 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 834 #endif
 835
 836 /*
 837  * Dynamic MTD Partition support with mtdparts
 838  */
 839 #ifndef CONFIG_SYS_NO_FLASH
 840 #define CONFIG_MTD_DEVICE
 841 #define CONFIG_MTD_PARTITIONS
 842 #define CONFIG_CMD_MTDPARTS
 843 #define CONFIG_FLASH_CFI_MTD
 844 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 845                         "spi0=spife110000.0"
 846 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 847                                 "128k(dtb),96m(fs),-(user);"\
 848                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 849                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 850                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 851 #endif
 852
 853 /*
 854  * Environment Configuration
 855  */
 856 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 857 #define CONFIG_BOOTFILE         "uImage"
 858 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 859
 860 /* default location for tftp and bootm */
 861 #define CONFIG_LOADADDR         1000000
 862
 863 #define CONFIG_BOOTDELAY        10      /*-1 disables auto-boot*/
 864
 865 #define CONFIG_BAUDRATE 115200
 866
 867 #define __USB_PHY_TYPE  utmi
 868 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 869
 870 #ifdef CONFIG_T1040RDB
 871 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 872 #elif defined(CONFIG_T1042RDB_PI)
 873 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 874 #elif defined(CONFIG_T1042RDB)
 875 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 876 #elif defined(CONFIG_T1040D4RDB)
 877 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 878 #elif defined(CONFIG_T1042D4RDB)
 879 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 880 #endif
 881
 882 #ifdef CONFIG_FSL_DIU_FB
 883 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 884 #else
 885 #define DIU_ENVIRONMENT
 886 #endif
 887
 888 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 889         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 890         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 891         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 892         "netdev=eth0\0"                                         \
 893         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 894         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 895         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 896         "tftpflash=tftpboot $loadaddr $uboot && "               \
 897         "protect off $ubootaddr +$filesize && "                 \
 898         "erase $ubootaddr +$filesize && "                       \
 899         "cp.b $loadaddr $ubootaddr $filesize && "               \
 900         "protect on $ubootaddr +$filesize && "                  \
 901         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 902         "consoledev=ttyS0\0"                                    \
 903         "ramdiskaddr=2000000\0"                                 \
 904         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 905         "fdtaddr=c00000\0"                                      \
 906         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 907         "bdev=sda3\0"
 908
 909 #define CONFIG_LINUX                       \
 910         "setenv bootargs root=/dev/ram rw "            \
 911         "console=$consoledev,$baudrate $othbootargs;"  \
 912         "setenv ramdiskaddr 0x02000000;"               \
 913         "setenv fdtaddr 0x00c00000;"                   \
 914         "setenv loadaddr 0x1000000;"                   \
 915         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 916
 917 #define CONFIG_HDBOOT                                   \
 918         "setenv bootargs root=/dev/$bdev rw "           \
 919         "console=$consoledev,$baudrate $othbootargs;"   \
 920         "tftp $loadaddr $bootfile;"                     \
 921         "tftp $fdtaddr $fdtfile;"                       \
 922         "bootm $loadaddr - $fdtaddr"
 923
 924 #define CONFIG_NFSBOOTCOMMAND                   \
 925         "setenv bootargs root=/dev/nfs rw "     \
 926         "nfsroot=$serverip:$rootpath "          \
 927         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 928         "console=$consoledev,$baudrate $othbootargs;"   \
 929         "tftp $loadaddr $bootfile;"             \
 930         "tftp $fdtaddr $fdtfile;"               \
 931         "bootm $loadaddr - $fdtaddr"
 932
 933 #define CONFIG_RAMBOOTCOMMAND                           \
 934         "setenv bootargs root=/dev/ram rw "             \
 935         "console=$consoledev,$baudrate $othbootargs;"   \
 936         "tftp $ramdiskaddr $ramdiskfile;"               \
 937         "tftp $loadaddr $bootfile;"                     \
 938         "tftp $fdtaddr $fdtfile;"                       \
 939         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 940
 941 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 942
 943 #ifdef CONFIG_SECURE_BOOT
 944 #include <asm/fsl_secure_boot.h>
 945 #define CONFIG_CMD_BLOB
 946 #endif
 947
 948 #endif  /* __CONFIG_H */