include/configs/T208xQDS.h

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #if defined(CONFIG_ARCH_T2080)
  16 #define CONFIG_FSL_SATA_V2
  17 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  18 #define CONFIG_SRIO1            /* SRIO port 1 */
  19 #define CONFIG_SRIO2            /* SRIO port 2 */
  20 #elif defined(CONFIG_ARCH_T2081)
  21 #endif
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  25 #define CONFIG_MP               /* support multiple processors */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #ifdef CONFIG_PHYS_64BIT
  29 #define CONFIG_ADDR_MAP 1
  30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  31 #endif
  32
  33 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  34 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  35 #define CONFIG_ENV_OVERWRITE
  36
  37 #ifdef CONFIG_RAMBOOT_PBL
  38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  39
  40 #define CONFIG_SPL_FLUSH_IMAGE
  41 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  42 #define CONFIG_SYS_TEXT_BASE            0x00201000
  43 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  44 #define CONFIG_SPL_PAD_TO               0x40000
  45 #define CONFIG_SPL_MAX_SIZE             0x28000
  46 #define RESET_VECTOR_OFFSET             0x27FFC
  47 #define BOOT_PAGE_OFFSET                0x27000
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_SKIP_RELOCATE
  50 #define CONFIG_SPL_COMMON_INIT_DDR
  51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  52 #endif
  53
  54 #ifdef CONFIG_NAND
  55 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  56 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  57 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  58 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  59 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  60 #if defined(CONFIG_ARCH_T2080)
  61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  62 #elif defined(CONFIG_ARCH_T2081)
  63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  64 #endif
  65 #define CONFIG_SPL_NAND_BOOT
  66 #endif
  67
  68 #ifdef CONFIG_SPIFLASH
  69 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  70 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  75 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #if defined(CONFIG_ARCH_T2080)
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  81 #elif defined(CONFIG_ARCH_T2081)
  82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  83 #endif
  84 #define CONFIG_SPL_SPI_BOOT
  85 #endif
  86
  87 #ifdef CONFIG_SDCARD
  88 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  89 #define CONFIG_SPL_MMC_MINIMAL
  90 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  91 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  92 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  93 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  94 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  95 #ifndef CONFIG_SPL_BUILD
  96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  97 #endif
  98 #if defined(CONFIG_ARCH_T2080)
  99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
 100 #elif defined(CONFIG_ARCH_T2081)
 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
 102 #endif
 103 #define CONFIG_SPL_MMC_BOOT
 104 #endif
 105
 106 #endif /* CONFIG_RAMBOOT_PBL */
 107
 108 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 109 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 110 /* Set 1M boot space */
 111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 113                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 115 #endif
 116
 117 #ifndef CONFIG_SYS_TEXT_BASE
 118 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 119 #endif
 120
 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 122 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 123 #endif
 124
 125 /*
 126  * These can be toggled for performance analysis, otherwise use default.
 127  */
 128 #define CONFIG_SYS_CACHE_STASHING
 129 #define CONFIG_BTB              /* toggle branch predition */
 130 #define CONFIG_DDR_ECC
 131 #ifdef CONFIG_DDR_ECC
 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 133 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 134 #endif
 135
 136 #ifdef CONFIG_MTD_NOR_FLASH
 137 #define CONFIG_FLASH_CFI_DRIVER
 138 #define CONFIG_SYS_FLASH_CFI
 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 140 #endif
 141
 142 #if defined(CONFIG_SPIFLASH)
 143 #define CONFIG_SYS_EXTRA_ENV_RELOC
 144 #define CONFIG_ENV_SPI_BUS      0
 145 #define CONFIG_ENV_SPI_CS       0
 146 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 147 #define CONFIG_ENV_SPI_MODE     0
 148 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 149 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 150 #define CONFIG_ENV_SECT_SIZE    0x10000
 151 #elif defined(CONFIG_SDCARD)
 152 #define CONFIG_SYS_EXTRA_ENV_RELOC
 153 #define CONFIG_SYS_MMC_ENV_DEV  0
 154 #define CONFIG_ENV_SIZE         0x2000
 155 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 156 #elif defined(CONFIG_NAND)
 157 #define CONFIG_SYS_EXTRA_ENV_RELOC
 158 #define CONFIG_ENV_SIZE         0x2000
 159 #define CONFIG_ENV_OFFSET       (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 160 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 161 #define CONFIG_ENV_IS_IN_REMOTE
 162 #define CONFIG_ENV_ADDR         0xffe20000
 163 #define CONFIG_ENV_SIZE         0x2000
 164 #elif defined(CONFIG_ENV_IS_NOWHERE)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #else
 167 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 168 #define CONFIG_ENV_SIZE         0x2000
 169 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 170 #endif
 171
 172 #ifndef __ASSEMBLY__
 173 unsigned long get_board_sys_clk(void);
 174 unsigned long get_board_ddr_clk(void);
 175 #endif
 176
 177 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 178 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 179
 180 /*
 181  * Config the L3 Cache as L3 SRAM
 182  */
 183 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 184 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 185 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 186 #ifdef CONFIG_RAMBOOT_PBL
 187 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 188 #endif
 189 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 190 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 191 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 192 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 193
 194 #define CONFIG_SYS_DCSRBAR      0xf0000000
 195 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 196
 197 /* EEPROM */
 198 #define CONFIG_ID_EEPROM
 199 #define CONFIG_SYS_I2C_EEPROM_NXID
 200 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 201 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 202 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 203
 204 /*
 205  * DDR Setup
 206  */
 207 #define CONFIG_VERY_BIG_RAM
 208 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 209 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 210 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 211 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 212 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 213 #define CONFIG_DDR_SPD
 214 #define CONFIG_FSL_DDR_INTERACTIVE
 215 #define CONFIG_SYS_SPD_BUS_NUM  0
 216 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 217 #define SPD_EEPROM_ADDRESS1     0x51
 218 #define SPD_EEPROM_ADDRESS2     0x52
 219 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 220 #define CTRL_INTLV_PREFERED     cacheline
 221
 222 /*
 223  * IFC Definitions
 224  */
 225 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 226 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 227 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 228 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 229                                 + 0x8000000) | \
 230                                 CSPR_PORT_SIZE_16 | \
 231                                 CSPR_MSEL_NOR | \
 232                                 CSPR_V)
 233 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 234 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 235                                 CSPR_PORT_SIZE_16 | \
 236                                 CSPR_MSEL_NOR | \
 237                                 CSPR_V)
 238 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 239 /* NOR Flash Timing Params */
 240 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 241
 242 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 243                                 FTIM0_NOR_TEADC(0x5) | \
 244                                 FTIM0_NOR_TEAHC(0x5))
 245 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 246                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 247                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 248 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 249                                 FTIM2_NOR_TCH(0x4) | \
 250                                 FTIM2_NOR_TWPH(0x0E) | \
 251                                 FTIM2_NOR_TWP(0x1c))
 252 #define CONFIG_SYS_NOR_FTIM3    0x0
 253
 254 #define CONFIG_SYS_FLASH_QUIET_TEST
 255 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 256
 257 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 258 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 259 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 260 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 261
 262 #define CONFIG_SYS_FLASH_EMPTY_INFO
 263 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 264                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 265
 266 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 267 #define QIXIS_BASE                      0xffdf0000
 268 #define QIXIS_LBMAP_SWITCH              6
 269 #define QIXIS_LBMAP_MASK                0x0f
 270 #define QIXIS_LBMAP_SHIFT               0
 271 #define QIXIS_LBMAP_DFLTBANK            0x00
 272 #define QIXIS_LBMAP_ALTBANK             0x04
 273 #define QIXIS_LBMAP_NAND                0x09
 274 #define QIXIS_LBMAP_SD                  0x00
 275 #define QIXIS_RCW_SRC_NAND              0x104
 276 #define QIXIS_RCW_SRC_SD                0x040
 277 #define QIXIS_RST_CTL_RESET             0x83
 278 #define QIXIS_RST_FORCE_MEM             0x1
 279 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 280 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 281 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 282 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 283
 284 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 285 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 286                                 | CSPR_PORT_SIZE_8 \
 287                                 | CSPR_MSEL_GPCM \
 288                                 | CSPR_V)
 289 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 290 #define CONFIG_SYS_CSOR3        0x0
 291 /* QIXIS Timing parameters for IFC CS3 */
 292 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 293                                         FTIM0_GPCM_TEADC(0x0e) | \
 294                                         FTIM0_GPCM_TEAHC(0x0e))
 295 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 296                                         FTIM1_GPCM_TRAD(0x3f))
 297 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 298                                         FTIM2_GPCM_TCH(0x8) | \
 299                                         FTIM2_GPCM_TWP(0x1f))
 300 #define CONFIG_SYS_CS3_FTIM3            0x0
 301
 302 /* NAND Flash on IFC */
 303 #define CONFIG_NAND_FSL_IFC
 304 #define CONFIG_SYS_NAND_BASE            0xff800000
 305 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 306
 307 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 308 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 309                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 310                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 311                                 | CSPR_V)
 312 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 313
 314 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 315                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 316                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 317                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 318                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 319                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 320                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 321
 322 #define CONFIG_SYS_NAND_ONFI_DETECTION
 323
 324 /* ONFI NAND Flash mode0 Timing Params */
 325 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 326                                         FTIM0_NAND_TWP(0x18)    | \
 327                                         FTIM0_NAND_TWCHT(0x07)  | \
 328                                         FTIM0_NAND_TWH(0x0a))
 329 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 330                                         FTIM1_NAND_TWBE(0x39)   | \
 331                                         FTIM1_NAND_TRR(0x0e)    | \
 332                                         FTIM1_NAND_TRP(0x18))
 333 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 334                                         FTIM2_NAND_TREH(0x0a)   | \
 335                                         FTIM2_NAND_TWHRE(0x1e))
 336 #define CONFIG_SYS_NAND_FTIM3           0x0
 337
 338 #define CONFIG_SYS_NAND_DDR_LAW         11
 339 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 340 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 341 #define CONFIG_CMD_NAND
 342 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 343
 344 #if defined(CONFIG_NAND)
 345 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 346 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 347 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 348 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 349 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 350 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 351 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 352 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 353 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 354 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 355 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 356 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 357 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 358 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 359 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 360 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 361 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 362 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 363 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 364 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 365 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 366 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 367 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 368 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 369 #else
 370 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 371 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 372 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 373 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 374 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 375 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 376 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 377 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 378 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 379 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 380 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 381 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 382 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 383 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 384 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 385 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 386 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 387 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 388 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 389 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 390 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 391 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 392 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 393 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 394 #endif
 395
 396 #if defined(CONFIG_RAMBOOT_PBL)
 397 #define CONFIG_SYS_RAMBOOT
 398 #endif
 399
 400 #ifdef CONFIG_SPL_BUILD
 401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 402 #else
 403 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 404 #endif
 405
 406 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 407 #define CONFIG_MISC_INIT_R
 408 #define CONFIG_HWCONFIG
 409
 410 /* define to use L1 as initial stack */
 411 #define CONFIG_L1_INIT_RAM
 412 #define CONFIG_SYS_INIT_RAM_LOCK
 413 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 416 /* The assembler doesn't like typecast */
 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 418                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 419                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 420 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 421 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 422                                                 GENERATED_GBL_DATA_SIZE)
 423 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 424 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 425 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 426
 427 /*
 428  * Serial Port
 429  */
 430 #define CONFIG_CONS_INDEX               1
 431 #define CONFIG_SYS_NS16550_SERIAL
 432 #define CONFIG_SYS_NS16550_REG_SIZE     1
 433 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 434 #define CONFIG_SYS_BAUDRATE_TABLE       \
 435         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 436 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 437 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 438 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 439 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 440
 441 /*
 442  * I2C
 443  */
 444 #define CONFIG_SYS_I2C
 445 #define CONFIG_SYS_I2C_FSL
 446 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 447 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 448 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 449 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 450 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 451 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 452 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 453 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 454 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 455 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 456 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 457 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 458 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 459 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 460 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 461 #define I2C_MUX_CH_DEFAULT      0x8
 462
 463 #define I2C_MUX_CH_VOL_MONITOR 0xa
 464
 465 /* Voltage monitor on channel 2*/
 466 #define I2C_VOL_MONITOR_ADDR           0x40
 467 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 468 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 469 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 470
 471 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 472 #ifndef CONFIG_SPL_BUILD
 473 #define CONFIG_VID
 474 #endif
 475 #define CONFIG_VOL_MONITOR_IR36021_SET
 476 #define CONFIG_VOL_MONITOR_IR36021_READ
 477 /* The lowest and highest voltage allowed for T208xQDS */
 478 #define VDD_MV_MIN                      819
 479 #define VDD_MV_MAX                      1212
 480
 481 /*
 482  * RapidIO
 483  */
 484 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 485 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 486 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 487 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 488 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 489 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 490 /*
 491  * for slave u-boot IMAGE instored in master memory space,
 492  * PHYS must be aligned based on the SIZE
 493  */
 494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 496 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 498 /*
 499  * for slave UCODE and ENV instored in master memory space,
 500  * PHYS must be aligned based on the SIZE
 501  */
 502 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 503 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 504 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 505
 506 /* slave core release by master*/
 507 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 508 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 509
 510 /*
 511  * SRIO_PCIE_BOOT - SLAVE
 512  */
 513 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 514 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 515 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 516                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 517 #endif
 518
 519 /*
 520  * eSPI - Enhanced SPI
 521  */
 522 #ifdef CONFIG_SPI_FLASH
 523 #ifndef CONFIG_SPL_BUILD
 524 #endif
 525
 526 #define CONFIG_SPI_FLASH_BAR
 527 #define CONFIG_SF_DEFAULT_SPEED  10000000
 528 #define CONFIG_SF_DEFAULT_MODE    0
 529 #endif
 530
 531 /*
 532  * General PCI
 533  * Memory space is mapped 1-1, but I/O space must start from 0.
 534  */
 535 #define CONFIG_PCIE1            /* PCIE controller 1 */
 536 #define CONFIG_PCIE2            /* PCIE controller 2 */
 537 #define CONFIG_PCIE3            /* PCIE controller 3 */
 538 #define CONFIG_PCIE4            /* PCIE controller 4 */
 539 #define CONFIG_FSL_PCIE_RESET
 540 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 541 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 542 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 543 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 544 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 545 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 546 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 547 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 548 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 549 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 550 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 551
 552 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 553 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 554 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 555 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 556 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 557 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 558 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 559 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 560 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 561
 562 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 563 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 564 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 565 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 566 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 567 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 568 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 569 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 570 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 571
 572 /* controller 4, Base address 203000 */
 573 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 574 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 575 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 576 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 577 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 578 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 579 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 580
 581 #ifdef CONFIG_PCI
 582 #define CONFIG_PCI_INDIRECT_BRIDGE
 583 #define CONFIG_FSL_PCIE_RESET      /* need PCIe reset errata */
 584 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 585 #endif
 586
 587 /* Qman/Bman */
 588 #ifndef CONFIG_NOBQFMAN
 589 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 590 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 591 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 592 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 593 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 594 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 595 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 596 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 597 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 598 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 599                                         CONFIG_SYS_BMAN_CENA_SIZE)
 600 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 601 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 602 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 603 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 604 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 605 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 606 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 607 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 608 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 609 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 610 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 611                                         CONFIG_SYS_QMAN_CENA_SIZE)
 612 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 613 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 614
 615 #define CONFIG_SYS_DPAA_FMAN
 616 #define CONFIG_SYS_DPAA_PME
 617 #define CONFIG_SYS_PMAN
 618 #define CONFIG_SYS_DPAA_DCE
 619 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 620 #define CONFIG_SYS_INTERLAKEN
 621
 622 /* Default address of microcode for the Linux Fman driver */
 623 #if defined(CONFIG_SPIFLASH)
 624 /*
 625  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 626  * env, so we got 0x110000.
 627  */
 628 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 629 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 630 #elif defined(CONFIG_SDCARD)
 631 /*
 632  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 633  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 634  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 635  */
 636 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 637 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 638 #elif defined(CONFIG_NAND)
 639 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 640 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 641 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 642 /*
 643  * Slave has no ucode locally, it can fetch this from remote. When implementing
 644  * in two corenet boards, slave's ucode could be stored in master's memory
 645  * space, the address can be mapped from slave TLB->slave LAW->
 646  * slave SRIO or PCIE outbound window->master inbound window->
 647  * master LAW->the ucode address in master's memory space.
 648  */
 649 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 650 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 651 #else
 652 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 653 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 654 #endif
 655 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 656 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 657 #endif /* CONFIG_NOBQFMAN */
 658
 659 #ifdef CONFIG_SYS_DPAA_FMAN
 660 #define CONFIG_FMAN_ENET
 661 #define CONFIG_PHYLIB_10G
 662 #define CONFIG_PHY_VITESSE
 663 #define CONFIG_PHY_REALTEK
 664 #define CONFIG_PHY_TERANETICS
 665 #define RGMII_PHY1_ADDR 0x1
 666 #define RGMII_PHY2_ADDR 0x2
 667 #define FM1_10GEC1_PHY_ADDR       0x3
 668 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 669 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 670 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 671 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 672 #endif
 673
 674 #ifdef CONFIG_FMAN_ENET
 675 #define CONFIG_MII              /* MII PHY management */
 676 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 677 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 678 #endif
 679
 680 /*
 681  * SATA
 682  */
 683 #ifdef CONFIG_FSL_SATA_V2
 684 #define CONFIG_LIBATA
 685 #define CONFIG_FSL_SATA
 686 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 687 #define CONFIG_SATA1
 688 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 689 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 690 #define CONFIG_SATA2
 691 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 692 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 693 #define CONFIG_LBA48
 694 #endif
 695
 696 /*
 697  * USB
 698  */
 699 #ifdef CONFIG_USB_EHCI_HCD
 700 #define CONFIG_USB_EHCI_FSL
 701 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 702 #define CONFIG_HAS_FSL_DR_USB
 703 #endif
 704
 705 /*
 706  * SDHC
 707  */
 708 #ifdef CONFIG_MMC
 709 #define CONFIG_FSL_ESDHC
 710 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 711 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 712 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 713 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 714 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 715 #endif
 716
 717 /*
 718  * Dynamic MTD Partition support with mtdparts
 719  */
 720 #ifdef CONFIG_MTD_NOR_FLASH
 721 #define CONFIG_MTD_DEVICE
 722 #define CONFIG_MTD_PARTITIONS
 723 #define CONFIG_FLASH_CFI_MTD
 724 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 725                         "spi0=spife110000.0"
 726 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 727                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 728                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
 729                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 730 #endif
 731
 732 /*
 733  * Environment
 734  */
 735 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 736 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 737
 738 /*
 739  * Command line configuration.
 740  */
 741 #define CONFIG_CMD_REGINFO
 742
 743 #ifdef CONFIG_PCI
 744 #define CONFIG_CMD_PCI
 745 #endif
 746
 747 /*
 748  * Miscellaneous configurable options
 749  */
 750 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 751 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 752 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 753 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 754 #ifdef CONFIG_CMD_KGDB
 755 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 756 #else
 757 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 758 #endif
 759 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 760 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 761 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 762
 763 /*
 764  * For booting Linux, the board info and command line data
 765  * have to be in the first 64 MB of memory, since this is
 766  * the maximum mapped by the Linux kernel during initialization.
 767  */
 768 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 769 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 770
 771 #ifdef CONFIG_CMD_KGDB
 772 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 773 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 774 #endif
 775
 776 /*
 777  * Environment Configuration
 778  */
 779 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 780 #define CONFIG_BOOTFILE  "uImage"
 781 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 782
 783 /* default location for tftp and bootm */
 784 #define CONFIG_LOADADDR         1000000
 785 #define __USB_PHY_TYPE          utmi
 786
 787 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 788         "hwconfig=fsl_ddr:"                                     \
 789         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 790         "bank_intlv=auto;"                                      \
 791         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 792         "netdev=eth0\0"                                         \
 793         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 794         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 795         "tftpflash=tftpboot $loadaddr $uboot && "               \
 796         "protect off $ubootaddr +$filesize && "                 \
 797         "erase $ubootaddr +$filesize && "                       \
 798         "cp.b $loadaddr $ubootaddr $filesize && "               \
 799         "protect on $ubootaddr +$filesize && "                  \
 800         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 801         "consoledev=ttyS0\0"                                    \
 802         "ramdiskaddr=2000000\0"                                 \
 803         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 804         "fdtaddr=1e00000\0"                                     \
 805         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 806         "bdev=sda3\0"
 807
 808 /*
 809  * For emulation this causes u-boot to jump to the start of the
 810  * proof point app code automatically
 811  */
 812 #define CONFIG_PROOF_POINTS                             \
 813         "setenv bootargs root=/dev/$bdev rw "           \
 814         "console=$consoledev,$baudrate $othbootargs;"   \
 815         "cpu 1 release 0x29000000 - - -;"               \
 816         "cpu 2 release 0x29000000 - - -;"               \
 817         "cpu 3 release 0x29000000 - - -;"               \
 818         "cpu 4 release 0x29000000 - - -;"               \
 819         "cpu 5 release 0x29000000 - - -;"               \
 820         "cpu 6 release 0x29000000 - - -;"               \
 821         "cpu 7 release 0x29000000 - - -;"               \
 822         "go 0x29000000"
 823
 824 #define CONFIG_HVBOOT                           \
 825         "setenv bootargs config-addr=0x60000000; "      \
 826         "bootm 0x01000000 - 0x00f00000"
 827
 828 #define CONFIG_ALU                              \
 829         "setenv bootargs root=/dev/$bdev rw "           \
 830         "console=$consoledev,$baudrate $othbootargs;"   \
 831         "cpu 1 release 0x01000000 - - -;"               \
 832         "cpu 2 release 0x01000000 - - -;"               \
 833         "cpu 3 release 0x01000000 - - -;"               \
 834         "cpu 4 release 0x01000000 - - -;"               \
 835         "cpu 5 release 0x01000000 - - -;"               \
 836         "cpu 6 release 0x01000000 - - -;"               \
 837         "cpu 7 release 0x01000000 - - -;"               \
 838         "go 0x01000000"
 839
 840 #define CONFIG_LINUX                            \
 841         "setenv bootargs root=/dev/ram rw "             \
 842         "console=$consoledev,$baudrate $othbootargs;"   \
 843         "setenv ramdiskaddr 0x02000000;"                \
 844         "setenv fdtaddr 0x00c00000;"                    \
 845         "setenv loadaddr 0x1000000;"                    \
 846         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 847
 848 #define CONFIG_HDBOOT                                   \
 849         "setenv bootargs root=/dev/$bdev rw "           \
 850         "console=$consoledev,$baudrate $othbootargs;"   \
 851         "tftp $loadaddr $bootfile;"                     \
 852         "tftp $fdtaddr $fdtfile;"                       \
 853         "bootm $loadaddr - $fdtaddr"
 854
 855 #define CONFIG_NFSBOOTCOMMAND                   \
 856         "setenv bootargs root=/dev/nfs rw "     \
 857         "nfsroot=$serverip:$rootpath "          \
 858         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 859         "console=$consoledev,$baudrate $othbootargs;"   \
 860         "tftp $loadaddr $bootfile;"             \
 861         "tftp $fdtaddr $fdtfile;"               \
 862         "bootm $loadaddr - $fdtaddr"
 863
 864 #define CONFIG_RAMBOOTCOMMAND                           \
 865         "setenv bootargs root=/dev/ram rw "             \
 866         "console=$consoledev,$baudrate $othbootargs;"   \
 867         "tftp $ramdiskaddr $ramdiskfile;"               \
 868         "tftp $loadaddr $bootfile;"                     \
 869         "tftp $fdtaddr $fdtfile;"                       \
 870         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 871
 872 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 873
 874 #include <asm/fsl_secure_boot.h>
 875
 876 #endif  /* __T208xQDS_H */