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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/T208xQDS.h
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080/T2081 QDS board configuration file
14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
15 #define CONFIG_USB_EHCI
16 #if defined(CONFIG_ARCH_T2080)
17 #define CONFIG_T2080QDS
18 #define CONFIG_FSL_SATA_V2
19 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
20 #define CONFIG_SRIO1 /* SRIO port 1 */
21 #define CONFIG_SRIO2 /* SRIO port 2 */
22 #elif defined(CONFIG_ARCH_T2081)
23 #define CONFIG_T2081QDS
26 /* High Level Configuration Options */
28 #define CONFIG_E500 /* BOOKE e500 family */
29 #define CONFIG_E500MC /* BOOKE e500mc family */
30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
31 #define CONFIG_MP /* support multiple processors */
32 #define CONFIG_ENABLE_36BIT_PHYS
34 #ifdef CONFIG_PHYS_64BIT
35 #define CONFIG_ADDR_MAP 1
36 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
39 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
40 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
41 #define CONFIG_FSL_IFC /* Enable IFC Support */
42 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
43 #define CONFIG_ENV_OVERWRITE
45 #ifdef CONFIG_RAMBOOT_PBL
46 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
48 #define CONFIG_SPL_FLUSH_IMAGE
49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
50 #define CONFIG_SYS_TEXT_BASE 0x00201000
51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
52 #define CONFIG_SPL_PAD_TO 0x40000
53 #define CONFIG_SPL_MAX_SIZE 0x28000
54 #define RESET_VECTOR_OFFSET 0x27FFC
55 #define BOOT_PAGE_OFFSET 0x27000
56 #ifdef CONFIG_SPL_BUILD
57 #define CONFIG_SPL_SKIP_RELOCATE
58 #define CONFIG_SPL_COMMON_INIT_DDR
59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
60 #define CONFIG_SYS_NO_FLASH
64 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
65 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
66 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
67 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
69 #if defined(CONFIG_ARCH_T2080)
70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
71 #elif defined(CONFIG_ARCH_T2081)
72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
74 #define CONFIG_SPL_NAND_BOOT
77 #ifdef CONFIG_SPIFLASH
78 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
79 #define CONFIG_SPL_SPI_FLASH_MINIMAL
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
85 #ifndef CONFIG_SPL_BUILD
86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
88 #if defined(CONFIG_ARCH_T2080)
89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
90 #elif defined(CONFIG_ARCH_T2081)
91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
93 #define CONFIG_SPL_SPI_BOOT
97 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
98 #define CONFIG_SPL_MMC_MINIMAL
99 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
100 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
101 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
102 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
103 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
104 #ifndef CONFIG_SPL_BUILD
105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
107 #if defined(CONFIG_ARCH_T2080)
108 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
109 #elif defined(CONFIG_ARCH_T2081)
110 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
112 #define CONFIG_SPL_MMC_BOOT
115 #endif /* CONFIG_RAMBOOT_PBL */
117 #define CONFIG_SRIO_PCIE_BOOT_MASTER
118 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
119 /* Set 1M boot space */
120 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
121 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
122 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
123 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
124 #define CONFIG_SYS_NO_FLASH
127 #ifndef CONFIG_SYS_TEXT_BASE
128 #define CONFIG_SYS_TEXT_BASE 0xeff40000
131 #ifndef CONFIG_RESET_VECTOR_ADDRESS
132 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
136 * These can be toggled for performance analysis, otherwise use default.
138 #define CONFIG_SYS_CACHE_STASHING
139 #define CONFIG_BTB /* toggle branch predition */
140 #define CONFIG_DDR_ECC
141 #ifdef CONFIG_DDR_ECC
142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
143 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
146 #ifndef CONFIG_SYS_NO_FLASH
147 #define CONFIG_FLASH_CFI_DRIVER
148 #define CONFIG_SYS_FLASH_CFI
149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
152 #if defined(CONFIG_SPIFLASH)
153 #define CONFIG_SYS_EXTRA_ENV_RELOC
154 #define CONFIG_ENV_IS_IN_SPI_FLASH
155 #define CONFIG_ENV_SPI_BUS 0
156 #define CONFIG_ENV_SPI_CS 0
157 #define CONFIG_ENV_SPI_MAX_HZ 10000000
158 #define CONFIG_ENV_SPI_MODE 0
159 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
160 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
161 #define CONFIG_ENV_SECT_SIZE 0x10000
162 #elif defined(CONFIG_SDCARD)
163 #define CONFIG_SYS_EXTRA_ENV_RELOC
164 #define CONFIG_ENV_IS_IN_MMC
165 #define CONFIG_SYS_MMC_ENV_DEV 0
166 #define CONFIG_ENV_SIZE 0x2000
167 #define CONFIG_ENV_OFFSET (512 * 0x800)
168 #elif defined(CONFIG_NAND)
169 #define CONFIG_SYS_EXTRA_ENV_RELOC
170 #define CONFIG_ENV_IS_IN_NAND
171 #define CONFIG_ENV_SIZE 0x2000
172 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
173 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
174 #define CONFIG_ENV_IS_IN_REMOTE
175 #define CONFIG_ENV_ADDR 0xffe20000
176 #define CONFIG_ENV_SIZE 0x2000
177 #elif defined(CONFIG_ENV_IS_NOWHERE)
178 #define CONFIG_ENV_SIZE 0x2000
180 #define CONFIG_ENV_IS_IN_FLASH
181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
182 #define CONFIG_ENV_SIZE 0x2000
183 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
187 unsigned long get_board_sys_clk(void);
188 unsigned long get_board_ddr_clk(void);
191 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
192 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
195 * Config the L3 Cache as L3 SRAM
197 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
198 #define CONFIG_SYS_L3_SIZE (512 << 10)
199 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
200 #ifdef CONFIG_RAMBOOT_PBL
201 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
203 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
204 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
205 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
206 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
208 #define CONFIG_SYS_DCSRBAR 0xf0000000
209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
212 #define CONFIG_ID_EEPROM
213 #define CONFIG_SYS_I2C_EEPROM_NXID
214 #define CONFIG_SYS_EEPROM_BUS_NUM 0
215 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
221 #define CONFIG_VERY_BIG_RAM
222 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
223 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
224 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
225 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
226 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
227 #define CONFIG_DDR_SPD
228 #define CONFIG_SYS_FSL_DDR3
229 #define CONFIG_FSL_DDR_INTERACTIVE
230 #define CONFIG_SYS_SPD_BUS_NUM 0
231 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
232 #define SPD_EEPROM_ADDRESS1 0x51
233 #define SPD_EEPROM_ADDRESS2 0x52
234 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
235 #define CTRL_INTLV_PREFERED cacheline
240 #define CONFIG_SYS_FLASH_BASE 0xe0000000
241 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
242 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
243 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
245 CSPR_PORT_SIZE_16 | \
248 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
249 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
250 CSPR_PORT_SIZE_16 | \
253 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
254 /* NOR Flash Timing Params */
255 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
257 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
258 FTIM0_NOR_TEADC(0x5) | \
259 FTIM0_NOR_TEAHC(0x5))
260 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
261 FTIM1_NOR_TRAD_NOR(0x1A) |\
262 FTIM1_NOR_TSEQRAD_NOR(0x13))
263 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
264 FTIM2_NOR_TCH(0x4) | \
265 FTIM2_NOR_TWPH(0x0E) | \
267 #define CONFIG_SYS_NOR_FTIM3 0x0
269 #define CONFIG_SYS_FLASH_QUIET_TEST
270 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
272 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
273 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
274 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
275 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
277 #define CONFIG_SYS_FLASH_EMPTY_INFO
278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
279 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
281 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
282 #define QIXIS_BASE 0xffdf0000
283 #define QIXIS_LBMAP_SWITCH 6
284 #define QIXIS_LBMAP_MASK 0x0f
285 #define QIXIS_LBMAP_SHIFT 0
286 #define QIXIS_LBMAP_DFLTBANK 0x00
287 #define QIXIS_LBMAP_ALTBANK 0x04
288 #define QIXIS_LBMAP_NAND 0x09
289 #define QIXIS_LBMAP_SD 0x00
290 #define QIXIS_RCW_SRC_NAND 0x104
291 #define QIXIS_RCW_SRC_SD 0x040
292 #define QIXIS_RST_CTL_RESET 0x83
293 #define QIXIS_RST_FORCE_MEM 0x1
294 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
295 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
296 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
297 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
299 #define CONFIG_SYS_CSPR3_EXT (0xf)
300 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
304 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
305 #define CONFIG_SYS_CSOR3 0x0
306 /* QIXIS Timing parameters for IFC CS3 */
307 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
308 FTIM0_GPCM_TEADC(0x0e) | \
309 FTIM0_GPCM_TEAHC(0x0e))
310 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
311 FTIM1_GPCM_TRAD(0x3f))
312 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
313 FTIM2_GPCM_TCH(0x8) | \
314 FTIM2_GPCM_TWP(0x1f))
315 #define CONFIG_SYS_CS3_FTIM3 0x0
317 /* NAND Flash on IFC */
318 #define CONFIG_NAND_FSL_IFC
319 #define CONFIG_SYS_NAND_BASE 0xff800000
320 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
322 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
323 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
324 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
325 | CSPR_MSEL_NAND /* MSEL = NAND */ \
327 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
329 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
330 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
331 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
332 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
333 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
334 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
335 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
337 #define CONFIG_SYS_NAND_ONFI_DETECTION
339 /* ONFI NAND Flash mode0 Timing Params */
340 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
341 FTIM0_NAND_TWP(0x18) | \
342 FTIM0_NAND_TWCHT(0x07) | \
343 FTIM0_NAND_TWH(0x0a))
344 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
345 FTIM1_NAND_TWBE(0x39) | \
346 FTIM1_NAND_TRR(0x0e) | \
347 FTIM1_NAND_TRP(0x18))
348 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
349 FTIM2_NAND_TREH(0x0a) | \
350 FTIM2_NAND_TWHRE(0x1e))
351 #define CONFIG_SYS_NAND_FTIM3 0x0
353 #define CONFIG_SYS_NAND_DDR_LAW 11
354 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
355 #define CONFIG_SYS_MAX_NAND_DEVICE 1
356 #define CONFIG_CMD_NAND
357 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
359 #if defined(CONFIG_NAND)
360 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
361 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
362 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
363 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
364 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
365 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
366 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
367 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
368 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
369 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
370 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
371 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
372 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
373 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
374 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
375 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
376 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
377 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
378 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
379 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
380 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
381 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
382 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
383 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
385 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
386 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
387 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
388 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
389 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
390 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
391 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
392 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
393 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
394 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
395 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
396 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
397 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
398 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
399 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
400 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
401 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
402 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
403 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
404 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
405 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
406 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
407 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
408 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
411 #if defined(CONFIG_RAMBOOT_PBL)
412 #define CONFIG_SYS_RAMBOOT
415 #ifdef CONFIG_SPL_BUILD
416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
421 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
422 #define CONFIG_MISC_INIT_R
423 #define CONFIG_HWCONFIG
425 /* define to use L1 as initial stack */
426 #define CONFIG_L1_INIT_RAM
427 #define CONFIG_SYS_INIT_RAM_LOCK
428 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
431 /* The assembler doesn't like typecast */
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
433 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
434 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
435 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
436 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
437 GENERATED_GBL_DATA_SIZE)
438 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
439 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
440 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
445 #define CONFIG_CONS_INDEX 1
446 #define CONFIG_SYS_NS16550_SERIAL
447 #define CONFIG_SYS_NS16550_REG_SIZE 1
448 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
449 #define CONFIG_SYS_BAUDRATE_TABLE \
450 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
451 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
452 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
453 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
454 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
459 #define CONFIG_SYS_I2C
460 #define CONFIG_SYS_I2C_FSL
461 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
462 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
463 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
464 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
465 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
466 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
467 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
468 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
469 #define CONFIG_SYS_FSL_I2C_SPEED 100000
470 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
471 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
472 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
473 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
474 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
475 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
476 #define I2C_MUX_CH_DEFAULT 0x8
478 #define I2C_MUX_CH_VOL_MONITOR 0xa
480 /* Voltage monitor on channel 2*/
481 #define I2C_VOL_MONITOR_ADDR 0x40
482 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
483 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
484 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
486 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
487 #ifndef CONFIG_SPL_BUILD
490 #define CONFIG_VOL_MONITOR_IR36021_SET
491 #define CONFIG_VOL_MONITOR_IR36021_READ
492 /* The lowest and highest voltage allowed for T208xQDS */
493 #define VDD_MV_MIN 819
494 #define VDD_MV_MAX 1212
499 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
500 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
501 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
502 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
503 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
504 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
506 * for slave u-boot IMAGE instored in master memory space,
507 * PHYS must be aligned based on the SIZE
509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
514 * for slave UCODE and ENV instored in master memory space,
515 * PHYS must be aligned based on the SIZE
517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
521 /* slave core release by master*/
522 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
523 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
526 * SRIO_PCIE_BOOT - SLAVE
528 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
529 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
530 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
531 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
535 * eSPI - Enhanced SPI
537 #ifdef CONFIG_SPI_FLASH
538 #ifndef CONFIG_SPL_BUILD
541 #define CONFIG_SPI_FLASH_BAR
542 #define CONFIG_SF_DEFAULT_SPEED 10000000
543 #define CONFIG_SF_DEFAULT_MODE 0
548 * Memory space is mapped 1-1, but I/O space must start from 0.
550 #define CONFIG_PCIE1 /* PCIE controller 1 */
551 #define CONFIG_PCIE2 /* PCIE controller 2 */
552 #define CONFIG_PCIE3 /* PCIE controller 3 */
553 #define CONFIG_PCIE4 /* PCIE controller 4 */
554 #define CONFIG_FSL_PCIE_RESET
555 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
556 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
557 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
558 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
559 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
560 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
561 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
562 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
563 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
564 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
565 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
567 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
568 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
569 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
570 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
571 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
572 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
573 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
574 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
575 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
577 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
578 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
579 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
580 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
581 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
582 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
583 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
584 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
585 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
587 /* controller 4, Base address 203000 */
588 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
589 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
590 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
591 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
592 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
593 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
594 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
597 #define CONFIG_PCI_INDIRECT_BRIDGE
598 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
599 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
600 #define CONFIG_DOS_PARTITION
604 #ifndef CONFIG_NOBQFMAN
605 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
606 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
607 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
608 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
609 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
610 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
611 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
612 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
613 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
614 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
615 CONFIG_SYS_BMAN_CENA_SIZE)
616 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
617 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
618 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
619 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
620 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
621 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
622 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
623 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
624 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
625 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
626 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
627 CONFIG_SYS_QMAN_CENA_SIZE)
628 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
629 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
631 #define CONFIG_SYS_DPAA_FMAN
632 #define CONFIG_SYS_DPAA_PME
633 #define CONFIG_SYS_PMAN
634 #define CONFIG_SYS_DPAA_DCE
635 #define CONFIG_SYS_DPAA_RMAN /* RMan */
636 #define CONFIG_SYS_INTERLAKEN
638 /* Default address of microcode for the Linux Fman driver */
639 #if defined(CONFIG_SPIFLASH)
641 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
642 * env, so we got 0x110000.
644 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
645 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
646 #elif defined(CONFIG_SDCARD)
648 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
649 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
650 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
652 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
653 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
654 #elif defined(CONFIG_NAND)
655 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
656 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
657 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
659 * Slave has no ucode locally, it can fetch this from remote. When implementing
660 * in two corenet boards, slave's ucode could be stored in master's memory
661 * space, the address can be mapped from slave TLB->slave LAW->
662 * slave SRIO or PCIE outbound window->master inbound window->
663 * master LAW->the ucode address in master's memory space.
665 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
666 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
668 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
669 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
671 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
672 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
673 #endif /* CONFIG_NOBQFMAN */
675 #ifdef CONFIG_SYS_DPAA_FMAN
676 #define CONFIG_FMAN_ENET
677 #define CONFIG_PHYLIB_10G
678 #define CONFIG_PHY_VITESSE
679 #define CONFIG_PHY_REALTEK
680 #define CONFIG_PHY_TERANETICS
681 #define RGMII_PHY1_ADDR 0x1
682 #define RGMII_PHY2_ADDR 0x2
683 #define FM1_10GEC1_PHY_ADDR 0x3
684 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
685 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
686 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
687 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
690 #ifdef CONFIG_FMAN_ENET
691 #define CONFIG_MII /* MII PHY management */
692 #define CONFIG_ETHPRIME "FM1@DTSEC3"
693 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
699 #ifdef CONFIG_FSL_SATA_V2
700 #define CONFIG_LIBATA
701 #define CONFIG_FSL_SATA
702 #define CONFIG_SYS_SATA_MAX_DEVICE 2
704 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
705 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
707 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
708 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
710 #define CONFIG_CMD_SATA
711 #define CONFIG_DOS_PARTITION
717 #ifdef CONFIG_USB_EHCI
718 #define CONFIG_USB_EHCI_FSL
719 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
720 #define CONFIG_HAS_FSL_DR_USB
727 #define CONFIG_FSL_ESDHC
728 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
729 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
730 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
731 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
732 #define CONFIG_GENERIC_MMC
733 #define CONFIG_DOS_PARTITION
734 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
738 * Dynamic MTD Partition support with mtdparts
740 #ifndef CONFIG_SYS_NO_FLASH
741 #define CONFIG_MTD_DEVICE
742 #define CONFIG_MTD_PARTITIONS
743 #define CONFIG_CMD_MTDPARTS
744 #define CONFIG_FLASH_CFI_MTD
745 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
747 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
748 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
749 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
750 "1m(uboot),5m(kernel),128k(dtb),-(user)"
756 #define CONFIG_LOADS_ECHO /* echo on for serial download */
757 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
760 * Command line configuration.
762 #define CONFIG_CMD_ERRATA
763 #define CONFIG_CMD_IRQ
764 #define CONFIG_CMD_REGINFO
767 #define CONFIG_CMD_PCI
770 /* Hash command with SHA acceleration supported in hardware */
771 #ifdef CONFIG_FSL_CAAM
772 #define CONFIG_CMD_HASH
773 #define CONFIG_SHA_HW_ACCEL
777 * Miscellaneous configurable options
779 #define CONFIG_SYS_LONGHELP /* undef to save memory */
780 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
781 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
782 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
783 #ifdef CONFIG_CMD_KGDB
784 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
786 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
788 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
789 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
790 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
793 * For booting Linux, the board info and command line data
794 * have to be in the first 64 MB of memory, since this is
795 * the maximum mapped by the Linux kernel during initialization.
797 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
798 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
800 #ifdef CONFIG_CMD_KGDB
801 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
802 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
806 * Environment Configuration
808 #define CONFIG_ROOTPATH "/opt/nfsroot"
809 #define CONFIG_BOOTFILE "uImage"
810 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
812 /* default location for tftp and bootm */
813 #define CONFIG_LOADADDR 1000000
814 #define CONFIG_BAUDRATE 115200
815 #define __USB_PHY_TYPE utmi
817 #define CONFIG_EXTRA_ENV_SETTINGS \
818 "hwconfig=fsl_ddr:" \
819 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
821 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
823 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
824 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
825 "tftpflash=tftpboot $loadaddr $uboot && " \
826 "protect off $ubootaddr +$filesize && " \
827 "erase $ubootaddr +$filesize && " \
828 "cp.b $loadaddr $ubootaddr $filesize && " \
829 "protect on $ubootaddr +$filesize && " \
830 "cmp.b $loadaddr $ubootaddr $filesize\0" \
831 "consoledev=ttyS0\0" \
832 "ramdiskaddr=2000000\0" \
833 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
834 "fdtaddr=1e00000\0" \
835 "fdtfile=t2080qds/t2080qds.dtb\0" \
839 * For emulation this causes u-boot to jump to the start of the
840 * proof point app code automatically
842 #define CONFIG_PROOF_POINTS \
843 "setenv bootargs root=/dev/$bdev rw " \
844 "console=$consoledev,$baudrate $othbootargs;" \
845 "cpu 1 release 0x29000000 - - -;" \
846 "cpu 2 release 0x29000000 - - -;" \
847 "cpu 3 release 0x29000000 - - -;" \
848 "cpu 4 release 0x29000000 - - -;" \
849 "cpu 5 release 0x29000000 - - -;" \
850 "cpu 6 release 0x29000000 - - -;" \
851 "cpu 7 release 0x29000000 - - -;" \
854 #define CONFIG_HVBOOT \
855 "setenv bootargs config-addr=0x60000000; " \
856 "bootm 0x01000000 - 0x00f00000"
859 "setenv bootargs root=/dev/$bdev rw " \
860 "console=$consoledev,$baudrate $othbootargs;" \
861 "cpu 1 release 0x01000000 - - -;" \
862 "cpu 2 release 0x01000000 - - -;" \
863 "cpu 3 release 0x01000000 - - -;" \
864 "cpu 4 release 0x01000000 - - -;" \
865 "cpu 5 release 0x01000000 - - -;" \
866 "cpu 6 release 0x01000000 - - -;" \
867 "cpu 7 release 0x01000000 - - -;" \
870 #define CONFIG_LINUX \
871 "setenv bootargs root=/dev/ram rw " \
872 "console=$consoledev,$baudrate $othbootargs;" \
873 "setenv ramdiskaddr 0x02000000;" \
874 "setenv fdtaddr 0x00c00000;" \
875 "setenv loadaddr 0x1000000;" \
876 "bootm $loadaddr $ramdiskaddr $fdtaddr"
878 #define CONFIG_HDBOOT \
879 "setenv bootargs root=/dev/$bdev rw " \
880 "console=$consoledev,$baudrate $othbootargs;" \
881 "tftp $loadaddr $bootfile;" \
882 "tftp $fdtaddr $fdtfile;" \
883 "bootm $loadaddr - $fdtaddr"
885 #define CONFIG_NFSBOOTCOMMAND \
886 "setenv bootargs root=/dev/nfs rw " \
887 "nfsroot=$serverip:$rootpath " \
888 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
889 "console=$consoledev,$baudrate $othbootargs;" \
890 "tftp $loadaddr $bootfile;" \
891 "tftp $fdtaddr $fdtfile;" \
892 "bootm $loadaddr - $fdtaddr"
894 #define CONFIG_RAMBOOTCOMMAND \
895 "setenv bootargs root=/dev/ram rw " \
896 "console=$consoledev,$baudrate $othbootargs;" \
897 "tftp $ramdiskaddr $ramdiskfile;" \
898 "tftp $loadaddr $bootfile;" \
899 "tftp $fdtaddr $fdtfile;" \
900 "bootm $loadaddr $ramdiskaddr $fdtaddr"
902 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
904 #include <asm/fsl_secure_boot.h>
906 #endif /* __T208xQDS_H */