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[people/ms/u-boot.git] / include / configs / T208xQDS.h
1 /*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * T2080/T2081 QDS board configuration file
9 */
10
11 #ifndef __T208xQDS_H
12 #define __T208xQDS_H
13
14 #define CONFIG_SYS_GENERIC_BOARD
15 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_MMC
18 #define CONFIG_SPI_FLASH
19 #define CONFIG_USB_EHCI
20 #if defined(CONFIG_PPC_T2080)
21 #define CONFIG_T2080QDS
22 #define CONFIG_FSL_SATA_V2
23 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
24 #define CONFIG_SRIO1 /* SRIO port 1 */
25 #define CONFIG_SRIO2 /* SRIO port 2 */
26 #elif defined(CONFIG_PPC_T2081)
27 #define CONFIG_T2081QDS
28 #endif
29
30 /* High Level Configuration Options */
31 #define CONFIG_PHYS_64BIT
32 #define CONFIG_BOOKE
33 #define CONFIG_E500 /* BOOKE e500 family */
34 #define CONFIG_E500MC /* BOOKE e500mc family */
35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
36 #define CONFIG_MP /* support multiple processors */
37 #define CONFIG_ENABLE_36BIT_PHYS
38
39 #ifdef CONFIG_PHYS_64BIT
40 #define CONFIG_ADDR_MAP 1
41 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
42 #endif
43
44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
45 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
46 #define CONFIG_FSL_IFC /* Enable IFC Support */
47 #define CONFIG_FSL_LAW /* Use common FSL init code */
48 #define CONFIG_ENV_OVERWRITE
49
50 #ifdef CONFIG_RAMBOOT_PBL
51 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
52 #if defined(CONFIG_PPC_T2080)
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
54 #elif defined(CONFIG_PPC_T2081)
55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
56 #endif
57
58 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
59 #define CONFIG_SPL_ENV_SUPPORT
60 #define CONFIG_SPL_SERIAL_SUPPORT
61 #define CONFIG_SPL_FLUSH_IMAGE
62 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
63 #define CONFIG_SPL_LIBGENERIC_SUPPORT
64 #define CONFIG_SPL_LIBCOMMON_SUPPORT
65 #define CONFIG_SPL_I2C_SUPPORT
66 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
67 #define CONFIG_FSL_LAW /* Use common FSL init code */
68 #define CONFIG_SYS_TEXT_BASE 0x00201000
69 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
70 #define CONFIG_SPL_PAD_TO 0x40000
71 #define CONFIG_SPL_MAX_SIZE 0x28000
72 #define RESET_VECTOR_OFFSET 0x27FFC
73 #define BOOT_PAGE_OFFSET 0x27000
74 #ifdef CONFIG_SPL_BUILD
75 #define CONFIG_SPL_SKIP_RELOCATE
76 #define CONFIG_SPL_COMMON_INIT_DDR
77 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
78 #define CONFIG_SYS_NO_FLASH
79 #endif
80
81 #ifdef CONFIG_NAND
82 #define CONFIG_SPL_NAND_SUPPORT
83 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
84 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
85 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
86 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
88 #define CONFIG_SPL_NAND_BOOT
89 #endif
90
91 #ifdef CONFIG_SPIFLASH
92 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
93 #define CONFIG_SPL_SPI_SUPPORT
94 #define CONFIG_SPL_SPI_FLASH_SUPPORT
95 #define CONFIG_SPL_SPI_FLASH_MINIMAL
96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
99 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
101 #ifndef CONFIG_SPL_BUILD
102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
103 #endif
104 #define CONFIG_SPL_SPI_BOOT
105 #endif
106
107 #ifdef CONFIG_SDCARD
108 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
109 #define CONFIG_SPL_MMC_SUPPORT
110 #define CONFIG_SPL_MMC_MINIMAL
111 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
112 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
113 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
114 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
115 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
116 #ifndef CONFIG_SPL_BUILD
117 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
118 #endif
119 #define CONFIG_SPL_MMC_BOOT
120 #endif
121
122 #endif /* CONFIG_RAMBOOT_PBL */
123
124 #define CONFIG_SRIO_PCIE_BOOT_MASTER
125 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
126 /* Set 1M boot space */
127 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
128 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
129 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
130 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
131 #define CONFIG_SYS_NO_FLASH
132 #endif
133
134 #ifndef CONFIG_SYS_TEXT_BASE
135 #define CONFIG_SYS_TEXT_BASE 0xeff40000
136 #endif
137
138 #ifndef CONFIG_RESET_VECTOR_ADDRESS
139 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
140 #endif
141
142 /*
143 * These can be toggled for performance analysis, otherwise use default.
144 */
145 #define CONFIG_SYS_CACHE_STASHING
146 #define CONFIG_BTB /* toggle branch predition */
147 #define CONFIG_DDR_ECC
148 #ifdef CONFIG_DDR_ECC
149 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
150 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
151 #endif
152
153 #ifndef CONFIG_SYS_NO_FLASH
154 #define CONFIG_FLASH_CFI_DRIVER
155 #define CONFIG_SYS_FLASH_CFI
156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
157 #endif
158
159 #if defined(CONFIG_SPIFLASH)
160 #define CONFIG_SYS_EXTRA_ENV_RELOC
161 #define CONFIG_ENV_IS_IN_SPI_FLASH
162 #define CONFIG_ENV_SPI_BUS 0
163 #define CONFIG_ENV_SPI_CS 0
164 #define CONFIG_ENV_SPI_MAX_HZ 10000000
165 #define CONFIG_ENV_SPI_MODE 0
166 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
167 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
168 #define CONFIG_ENV_SECT_SIZE 0x10000
169 #elif defined(CONFIG_SDCARD)
170 #define CONFIG_SYS_EXTRA_ENV_RELOC
171 #define CONFIG_ENV_IS_IN_MMC
172 #define CONFIG_SYS_MMC_ENV_DEV 0
173 #define CONFIG_ENV_SIZE 0x2000
174 #define CONFIG_ENV_OFFSET (512 * 0x800)
175 #elif defined(CONFIG_NAND)
176 #define CONFIG_SYS_EXTRA_ENV_RELOC
177 #define CONFIG_ENV_IS_IN_NAND
178 #define CONFIG_ENV_SIZE 0x2000
179 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
180 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
181 #define CONFIG_ENV_IS_IN_REMOTE
182 #define CONFIG_ENV_ADDR 0xffe20000
183 #define CONFIG_ENV_SIZE 0x2000
184 #elif defined(CONFIG_ENV_IS_NOWHERE)
185 #define CONFIG_ENV_SIZE 0x2000
186 #else
187 #define CONFIG_ENV_IS_IN_FLASH
188 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
189 #define CONFIG_ENV_SIZE 0x2000
190 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
191 #endif
192
193 #ifndef __ASSEMBLY__
194 unsigned long get_board_sys_clk(void);
195 unsigned long get_board_ddr_clk(void);
196 #endif
197
198 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
199 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
200
201 /*
202 * Config the L3 Cache as L3 SRAM
203 */
204 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
205 #define CONFIG_SYS_L3_SIZE (512 << 10)
206 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
207 #ifdef CONFIG_RAMBOOT_PBL
208 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
209 #endif
210 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
211 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
212 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
213 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
214
215 #define CONFIG_SYS_DCSRBAR 0xf0000000
216 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
217
218 /* EEPROM */
219 #define CONFIG_ID_EEPROM
220 #define CONFIG_SYS_I2C_EEPROM_NXID
221 #define CONFIG_SYS_EEPROM_BUS_NUM 0
222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
224
225 /*
226 * DDR Setup
227 */
228 #define CONFIG_VERY_BIG_RAM
229 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
230 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
231 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
232 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
233 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
234 #define CONFIG_DDR_SPD
235 #define CONFIG_SYS_FSL_DDR3
236 #undef CONFIG_FSL_DDR_INTERACTIVE
237 #define CONFIG_SYS_SPD_BUS_NUM 0
238 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
239 #define SPD_EEPROM_ADDRESS1 0x51
240 #define SPD_EEPROM_ADDRESS2 0x52
241 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
242 #define CTRL_INTLV_PREFERED cacheline
243
244 /*
245 * IFC Definitions
246 */
247 #define CONFIG_SYS_FLASH_BASE 0xe0000000
248 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
249 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
250 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
251 + 0x8000000) | \
252 CSPR_PORT_SIZE_16 | \
253 CSPR_MSEL_NOR | \
254 CSPR_V)
255 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
256 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
257 CSPR_PORT_SIZE_16 | \
258 CSPR_MSEL_NOR | \
259 CSPR_V)
260 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
261 /* NOR Flash Timing Params */
262 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
263
264 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
265 FTIM0_NOR_TEADC(0x5) | \
266 FTIM0_NOR_TEAHC(0x5))
267 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
268 FTIM1_NOR_TRAD_NOR(0x1A) |\
269 FTIM1_NOR_TSEQRAD_NOR(0x13))
270 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
271 FTIM2_NOR_TCH(0x4) | \
272 FTIM2_NOR_TWPH(0x0E) | \
273 FTIM2_NOR_TWP(0x1c))
274 #define CONFIG_SYS_NOR_FTIM3 0x0
275
276 #define CONFIG_SYS_FLASH_QUIET_TEST
277 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
278
279 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
280 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
281 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
282 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
283
284 #define CONFIG_SYS_FLASH_EMPTY_INFO
285 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
286 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
287
288 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
289 #define QIXIS_BASE 0xffdf0000
290 #define QIXIS_LBMAP_SWITCH 6
291 #define QIXIS_LBMAP_MASK 0x0f
292 #define QIXIS_LBMAP_SHIFT 0
293 #define QIXIS_LBMAP_DFLTBANK 0x00
294 #define QIXIS_LBMAP_ALTBANK 0x04
295 #define QIXIS_RST_CTL_RESET 0x83
296 #define QIXIS_RST_FORCE_MEM 0x1
297 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
298 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
299 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
300 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
301
302 #define CONFIG_SYS_CSPR3_EXT (0xf)
303 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
304 | CSPR_PORT_SIZE_8 \
305 | CSPR_MSEL_GPCM \
306 | CSPR_V)
307 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
308 #define CONFIG_SYS_CSOR3 0x0
309 /* QIXIS Timing parameters for IFC CS3 */
310 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
311 FTIM0_GPCM_TEADC(0x0e) | \
312 FTIM0_GPCM_TEAHC(0x0e))
313 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
314 FTIM1_GPCM_TRAD(0x3f))
315 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
316 FTIM2_GPCM_TCH(0x8) | \
317 FTIM2_GPCM_TWP(0x1f))
318 #define CONFIG_SYS_CS3_FTIM3 0x0
319
320 /* NAND Flash on IFC */
321 #define CONFIG_NAND_FSL_IFC
322 #define CONFIG_SYS_NAND_BASE 0xff800000
323 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
324
325 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
326 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
327 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
328 | CSPR_MSEL_NAND /* MSEL = NAND */ \
329 | CSPR_V)
330 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
331
332 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
333 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
334 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
335 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
336 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
337 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
338 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
339
340 #define CONFIG_SYS_NAND_ONFI_DETECTION
341
342 /* ONFI NAND Flash mode0 Timing Params */
343 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
344 FTIM0_NAND_TWP(0x18) | \
345 FTIM0_NAND_TWCHT(0x07) | \
346 FTIM0_NAND_TWH(0x0a))
347 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
348 FTIM1_NAND_TWBE(0x39) | \
349 FTIM1_NAND_TRR(0x0e) | \
350 FTIM1_NAND_TRP(0x18))
351 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
352 FTIM2_NAND_TREH(0x0a) | \
353 FTIM2_NAND_TWHRE(0x1e))
354 #define CONFIG_SYS_NAND_FTIM3 0x0
355
356 #define CONFIG_SYS_NAND_DDR_LAW 11
357 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
358 #define CONFIG_SYS_MAX_NAND_DEVICE 1
359 #define CONFIG_MTD_NAND_VERIFY_WRITE
360 #define CONFIG_CMD_NAND
361 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
362
363 #if defined(CONFIG_NAND)
364 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
365 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
366 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
367 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
368 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
369 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
370 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
371 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
372 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
373 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
374 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
380 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
381 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
382 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
383 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
384 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
385 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
386 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
387 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
388 #else
389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
397 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
405 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
406 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
407 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
408 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
409 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
410 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
411 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
412 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
413 #endif
414
415 #if defined(CONFIG_RAMBOOT_PBL)
416 #define CONFIG_SYS_RAMBOOT
417 #endif
418
419 #ifdef CONFIG_SPL_BUILD
420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
421 #else
422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
423 #endif
424
425 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
426 #define CONFIG_MISC_INIT_R
427 #define CONFIG_HWCONFIG
428
429 /* define to use L1 as initial stack */
430 #define CONFIG_L1_INIT_RAM
431 #define CONFIG_SYS_INIT_RAM_LOCK
432 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
435 /* The assembler doesn't like typecast */
436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
437 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
438 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
439 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
440 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
441 GENERATED_GBL_DATA_SIZE)
442 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
443 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
444 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
445
446 /*
447 * Serial Port
448 */
449 #define CONFIG_CONS_INDEX 1
450 #define CONFIG_SYS_NS16550
451 #define CONFIG_SYS_NS16550_SERIAL
452 #define CONFIG_SYS_NS16550_REG_SIZE 1
453 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
454 #define CONFIG_SYS_BAUDRATE_TABLE \
455 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
456 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
457 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
458 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
459 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
460
461 /* Use the HUSH parser */
462 #define CONFIG_SYS_HUSH_PARSER
463 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
464
465 /* pass open firmware flat tree */
466 #define CONFIG_OF_LIBFDT
467 #define CONFIG_OF_BOARD_SETUP
468 #define CONFIG_OF_STDOUT_VIA_ALIAS
469
470 /* new uImage format support */
471 #define CONFIG_FIT
472 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
473
474 /*
475 * I2C
476 */
477 #define CONFIG_SYS_I2C
478 #define CONFIG_SYS_I2C_FSL
479 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
480 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
481 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
482 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
483 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
484 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
485 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
486 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
487 #define CONFIG_SYS_FSL_I2C_SPEED 100000
488 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
489 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
490 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
491 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
492 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
493 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
494 #define I2C_MUX_CH_DEFAULT 0x8
495
496
497 /*
498 * RapidIO
499 */
500 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
501 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
502 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
503 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
504 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
505 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
506 /*
507 * for slave u-boot IMAGE instored in master memory space,
508 * PHYS must be aligned based on the SIZE
509 */
510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
514 /*
515 * for slave UCODE and ENV instored in master memory space,
516 * PHYS must be aligned based on the SIZE
517 */
518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
520 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
521
522 /* slave core release by master*/
523 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
524 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
525
526 /*
527 * SRIO_PCIE_BOOT - SLAVE
528 */
529 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
530 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
531 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
532 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
533 #endif
534
535 /*
536 * eSPI - Enhanced SPI
537 */
538 #ifdef CONFIG_SPI_FLASH
539 #define CONFIG_FSL_ESPI
540 #define CONFIG_SPI_FLASH_STMICRO
541 #ifndef CONFIG_SPL_BUILD
542 #define CONFIG_SPI_FLASH_SST
543 #define CONFIG_SPI_FLASH_EON
544 #endif
545
546 #define CONFIG_CMD_SF
547 #define CONFIG_SPI_FLASH_BAR
548 #define CONFIG_SF_DEFAULT_SPEED 10000000
549 #define CONFIG_SF_DEFAULT_MODE 0
550 #endif
551
552 /*
553 * General PCI
554 * Memory space is mapped 1-1, but I/O space must start from 0.
555 */
556 #define CONFIG_PCI /* Enable PCI/PCIE */
557 #define CONFIG_PCIE1 /* PCIE controler 1 */
558 #define CONFIG_PCIE2 /* PCIE controler 2 */
559 #define CONFIG_PCIE3 /* PCIE controler 3 */
560 #define CONFIG_PCIE4 /* PCIE controler 4 */
561 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
562 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
563 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
564 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
565 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
571 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
572
573 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
574 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
575 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
576 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
577 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
578 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
579 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
580 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
581 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
582
583 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
584 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
585 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
586 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
587 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
588 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
589 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
590 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
591 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
592
593 /* controller 4, Base address 203000 */
594 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
595 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
596 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
597 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
598 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
599 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
600 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
601
602 #ifdef CONFIG_PCI
603 #define CONFIG_PCI_INDIRECT_BRIDGE
604 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
605 #define CONFIG_NET_MULTI
606 #define CONFIG_E1000
607 #define CONFIG_PCI_PNP /* do pci plug-and-play */
608 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
609 #define CONFIG_DOS_PARTITION
610 #endif
611
612 /* Qman/Bman */
613 #ifndef CONFIG_NOBQFMAN
614 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
615 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
616 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
617 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
618 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
619 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
620 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
621 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
622 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
623
624 #define CONFIG_SYS_DPAA_FMAN
625 #define CONFIG_SYS_DPAA_PME
626 #define CONFIG_SYS_PMAN
627 #define CONFIG_SYS_DPAA_DCE
628 #define CONFIG_SYS_DPAA_RMAN /* RMan */
629 #define CONFIG_SYS_INTERLAKEN
630
631 /* Default address of microcode for the Linux Fman driver */
632 #if defined(CONFIG_SPIFLASH)
633 /*
634 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
635 * env, so we got 0x110000.
636 */
637 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
638 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
639 #elif defined(CONFIG_SDCARD)
640 /*
641 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
642 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
643 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
644 */
645 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
646 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
647 #elif defined(CONFIG_NAND)
648 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
649 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
650 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
651 /*
652 * Slave has no ucode locally, it can fetch this from remote. When implementing
653 * in two corenet boards, slave's ucode could be stored in master's memory
654 * space, the address can be mapped from slave TLB->slave LAW->
655 * slave SRIO or PCIE outbound window->master inbound window->
656 * master LAW->the ucode address in master's memory space.
657 */
658 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
659 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
660 #else
661 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
662 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
663 #endif
664 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
665 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
666 #endif /* CONFIG_NOBQFMAN */
667
668 #ifdef CONFIG_SYS_DPAA_FMAN
669 #define CONFIG_FMAN_ENET
670 #define CONFIG_PHYLIB_10G
671 #define CONFIG_PHY_VITESSE
672 #define CONFIG_PHY_REALTEK
673 #define CONFIG_PHY_TERANETICS
674 #define RGMII_PHY1_ADDR 0x1
675 #define RGMII_PHY2_ADDR 0x2
676 #define FM1_10GEC1_PHY_ADDR 0x3
677 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
678 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
679 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
680 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
681 #endif
682
683 #ifdef CONFIG_FMAN_ENET
684 #define CONFIG_MII /* MII PHY management */
685 #define CONFIG_ETHPRIME "FM1@DTSEC3"
686 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
687 #endif
688
689 /*
690 * SATA
691 */
692 #ifdef CONFIG_FSL_SATA_V2
693 #define CONFIG_LIBATA
694 #define CONFIG_FSL_SATA
695 #define CONFIG_SYS_SATA_MAX_DEVICE 2
696 #define CONFIG_SATA1
697 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
698 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
699 #define CONFIG_SATA2
700 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
701 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
702 #define CONFIG_LBA48
703 #define CONFIG_CMD_SATA
704 #define CONFIG_DOS_PARTITION
705 #define CONFIG_CMD_EXT2
706 #endif
707
708 /*
709 * USB
710 */
711 #ifdef CONFIG_USB_EHCI
712 #define CONFIG_CMD_USB
713 #define CONFIG_USB_STORAGE
714 #define CONFIG_USB_EHCI_FSL
715 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
716 #define CONFIG_CMD_EXT2
717 #define CONFIG_HAS_FSL_DR_USB
718 #endif
719
720 /*
721 * SDHC
722 */
723 #ifdef CONFIG_MMC
724 #define CONFIG_CMD_MMC
725 #define CONFIG_FSL_ESDHC
726 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
727 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
728 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
729 #define CONFIG_GENERIC_MMC
730 #define CONFIG_CMD_EXT2
731 #define CONFIG_CMD_FAT
732 #define CONFIG_DOS_PARTITION
733 #endif
734
735
736 /*
737 * Dynamic MTD Partition support with mtdparts
738 */
739 #ifndef CONFIG_SYS_NO_FLASH
740 #define CONFIG_MTD_DEVICE
741 #define CONFIG_MTD_PARTITIONS
742 #define CONFIG_CMD_MTDPARTS
743 #define CONFIG_FLASH_CFI_MTD
744 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
745 "spi0=spife110000.0"
746 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
747 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
748 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
749 "1m(uboot),5m(kernel),128k(dtb),-(user)"
750 #endif
751
752 /*
753 * Environment
754 */
755 #define CONFIG_LOADS_ECHO /* echo on for serial download */
756 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
757
758 /*
759 * Command line configuration.
760 */
761 #include <config_cmd_default.h>
762
763 #define CONFIG_CMD_DHCP
764 #define CONFIG_CMD_ELF
765 #define CONFIG_CMD_ERRATA
766 #define CONFIG_CMD_GREPENV
767 #define CONFIG_CMD_IRQ
768 #define CONFIG_CMD_I2C
769 #define CONFIG_CMD_MII
770 #define CONFIG_CMD_PING
771 #define CONFIG_CMD_SETEXPR
772 #define CONFIG_CMD_REGINFO
773 #define CONFIG_CMD_BDI
774
775 #ifdef CONFIG_PCI
776 #define CONFIG_CMD_PCI
777 #define CONFIG_CMD_NET
778 #endif
779
780 /*
781 * Miscellaneous configurable options
782 */
783 #define CONFIG_SYS_LONGHELP /* undef to save memory */
784 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
785 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
786 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
787 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
788 #ifdef CONFIG_CMD_KGDB
789 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
790 #else
791 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
792 #endif
793 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
794 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
795 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
796
797 /*
798 * For booting Linux, the board info and command line data
799 * have to be in the first 64 MB of memory, since this is
800 * the maximum mapped by the Linux kernel during initialization.
801 */
802 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
803 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
804
805 #ifdef CONFIG_CMD_KGDB
806 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
807 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
808 #endif
809
810 /*
811 * Environment Configuration
812 */
813 #define CONFIG_ROOTPATH "/opt/nfsroot"
814 #define CONFIG_BOOTFILE "uImage"
815 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
816
817 /* default location for tftp and bootm */
818 #define CONFIG_LOADADDR 1000000
819 #define CONFIG_BAUDRATE 115200
820 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
821 #define __USB_PHY_TYPE utmi
822
823 #define CONFIG_EXTRA_ENV_SETTINGS \
824 "hwconfig=fsl_ddr:" \
825 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
826 "bank_intlv=auto;" \
827 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
828 "netdev=eth0\0" \
829 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
830 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
831 "tftpflash=tftpboot $loadaddr $uboot && " \
832 "protect off $ubootaddr +$filesize && " \
833 "erase $ubootaddr +$filesize && " \
834 "cp.b $loadaddr $ubootaddr $filesize && " \
835 "protect on $ubootaddr +$filesize && " \
836 "cmp.b $loadaddr $ubootaddr $filesize\0" \
837 "consoledev=ttyS0\0" \
838 "ramdiskaddr=2000000\0" \
839 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
840 "fdtaddr=c00000\0" \
841 "fdtfile=t2080qds/t2080qds.dtb\0" \
842 "bdev=sda3\0"
843
844 /*
845 * For emulation this causes u-boot to jump to the start of the
846 * proof point app code automatically
847 */
848 #define CONFIG_PROOF_POINTS \
849 "setenv bootargs root=/dev/$bdev rw " \
850 "console=$consoledev,$baudrate $othbootargs;" \
851 "cpu 1 release 0x29000000 - - -;" \
852 "cpu 2 release 0x29000000 - - -;" \
853 "cpu 3 release 0x29000000 - - -;" \
854 "cpu 4 release 0x29000000 - - -;" \
855 "cpu 5 release 0x29000000 - - -;" \
856 "cpu 6 release 0x29000000 - - -;" \
857 "cpu 7 release 0x29000000 - - -;" \
858 "go 0x29000000"
859
860 #define CONFIG_HVBOOT \
861 "setenv bootargs config-addr=0x60000000; " \
862 "bootm 0x01000000 - 0x00f00000"
863
864 #define CONFIG_ALU \
865 "setenv bootargs root=/dev/$bdev rw " \
866 "console=$consoledev,$baudrate $othbootargs;" \
867 "cpu 1 release 0x01000000 - - -;" \
868 "cpu 2 release 0x01000000 - - -;" \
869 "cpu 3 release 0x01000000 - - -;" \
870 "cpu 4 release 0x01000000 - - -;" \
871 "cpu 5 release 0x01000000 - - -;" \
872 "cpu 6 release 0x01000000 - - -;" \
873 "cpu 7 release 0x01000000 - - -;" \
874 "go 0x01000000"
875
876 #define CONFIG_LINUX \
877 "setenv bootargs root=/dev/ram rw " \
878 "console=$consoledev,$baudrate $othbootargs;" \
879 "setenv ramdiskaddr 0x02000000;" \
880 "setenv fdtaddr 0x00c00000;" \
881 "setenv loadaddr 0x1000000;" \
882 "bootm $loadaddr $ramdiskaddr $fdtaddr"
883
884 #define CONFIG_HDBOOT \
885 "setenv bootargs root=/dev/$bdev rw " \
886 "console=$consoledev,$baudrate $othbootargs;" \
887 "tftp $loadaddr $bootfile;" \
888 "tftp $fdtaddr $fdtfile;" \
889 "bootm $loadaddr - $fdtaddr"
890
891 #define CONFIG_NFSBOOTCOMMAND \
892 "setenv bootargs root=/dev/nfs rw " \
893 "nfsroot=$serverip:$rootpath " \
894 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
895 "console=$consoledev,$baudrate $othbootargs;" \
896 "tftp $loadaddr $bootfile;" \
897 "tftp $fdtaddr $fdtfile;" \
898 "bootm $loadaddr - $fdtaddr"
899
900 #define CONFIG_RAMBOOTCOMMAND \
901 "setenv bootargs root=/dev/ram rw " \
902 "console=$consoledev,$baudrate $othbootargs;" \
903 "tftp $ramdiskaddr $ramdiskfile;" \
904 "tftp $loadaddr $bootfile;" \
905 "tftp $fdtaddr $fdtfile;" \
906 "bootm $loadaddr $ramdiskaddr $fdtaddr"
907
908 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
909
910 #ifdef CONFIG_SECURE_BOOT
911 #include <asm/fsl_secure_boot.h>
912 #undef CONFIG_CMD_USB
913 #endif
914
915 #endif /* __T208xQDS_H */