include/configs/T4240RDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_SATA_V2
  14 #define CONFIG_PCIE4
  15
  16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_SYS_TEXT_BASE            0x00201000
  27 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32
  33 #ifdef  CONFIG_SDCARD
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  35 #define CONFIG_SPL_MMC_MINIMAL
  36 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  37 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  38 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  39 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  40 #ifndef CONFIG_SPL_BUILD
  41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  42 #endif
  43 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  45 #define CONFIG_SPL_MMC_BOOT
  46 #endif
  47
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_SKIP_RELOCATE
  50 #define CONFIG_SPL_COMMON_INIT_DDR
  51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  52 #endif
  53
  54 #endif
  55 #endif /* CONFIG_RAMBOOT_PBL */
  56
  57 #define CONFIG_DDR_ECC
  58
  59 /* High Level Configuration Options */
  60 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  61 #define CONFIG_MP                       /* support multiple processors */
  62
  63 #ifndef CONFIG_SYS_TEXT_BASE
  64 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  65 #endif
  66
  67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  68 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  69 #endif
  70
  71 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  72 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  73 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  74 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  75 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  76 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  77 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  78
  79 #define CONFIG_ENV_OVERWRITE
  80
  81 /*
  82  * These can be toggled for performance analysis, otherwise use default.
  83  */
  84 #define CONFIG_SYS_CACHE_STASHING
  85 #define CONFIG_BTB                      /* toggle branch predition */
  86 #ifdef CONFIG_DDR_ECC
  87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  88 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  89 #endif
  90
  91 #define CONFIG_ENABLE_36BIT_PHYS
  92
  93 #define CONFIG_ADDR_MAP
  94 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  95
  96 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  97 #define CONFIG_SYS_MEMTEST_END          0x00400000
  98 #define CONFIG_SYS_ALT_MEMTEST
  99
 100 /*
 101  *  Config the L3 Cache as L3 SRAM
 102  */
 103 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 104 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 105 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 106 #ifdef CONFIG_RAMBOOT_PBL
 107 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 108 #endif
 109 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 110 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 111 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 112 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 113
 114 #define CONFIG_SYS_DCSRBAR              0xf0000000
 115 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 116
 117 /*
 118  * DDR Setup
 119  */
 120 #define CONFIG_VERY_BIG_RAM
 121 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 122 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 123
 124 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 125 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 126 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 127
 128 #define CONFIG_DDR_SPD
 129
 130 /*
 131  * IFC Definitions
 132  */
 133 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 134 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 135
 136 #ifdef CONFIG_SPL_BUILD
 137 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 138 #else
 139 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 140 #endif
 141
 142 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 143 #define CONFIG_MISC_INIT_R
 144
 145 #define CONFIG_HWCONFIG
 146
 147 /* define to use L1 as initial stack */
 148 #define CONFIG_L1_INIT_RAM
 149 #define CONFIG_SYS_INIT_RAM_LOCK
 150 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 151 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 153 /* The assembler doesn't like typecast */
 154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 155         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 156           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 157 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 158
 159 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 160                                         GENERATED_GBL_DATA_SIZE)
 161 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 162
 163 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 164 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 165
 166 /* Serial Port - controlled on board with jumper J8
 167  * open - index 2
 168  * shorted - index 1
 169  */
 170 #define CONFIG_CONS_INDEX       1
 171 #define CONFIG_SYS_NS16550_SERIAL
 172 #define CONFIG_SYS_NS16550_REG_SIZE     1
 173 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 174
 175 #define CONFIG_SYS_BAUDRATE_TABLE       \
 176         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 177
 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 180 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 181 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 182
 183 /* I2C */
 184 #define CONFIG_SYS_I2C
 185 #define CONFIG_SYS_I2C_FSL
 186 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 187 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 188 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 189 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 190
 191 /*
 192  * General PCI
 193  * Memory space is mapped 1-1, but I/O space must start from 0.
 194  */
 195
 196 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 197 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 198 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 199 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 200 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 201 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 202 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 203 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 204 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 205
 206 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 207 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 208 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 209 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 210 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 211 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 212 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 213 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 214 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 215
 216 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 217 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 218 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 219 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 220 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 221 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 222 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 223 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 224 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 225
 226 /* controller 4, Base address 203000 */
 227 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 228 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 229 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 230 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 231 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 232 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 233
 234 #ifdef CONFIG_PCI
 235 #define CONFIG_PCI_INDIRECT_BRIDGE
 236
 237 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 238 #endif  /* CONFIG_PCI */
 239
 240 /* SATA */
 241 #ifdef CONFIG_FSL_SATA_V2
 242 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 243 #define CONFIG_SATA1
 244 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 245 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 246 #define CONFIG_SATA2
 247 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 248 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 249
 250 #define CONFIG_LBA48
 251 #endif
 252
 253 #ifdef CONFIG_FMAN_ENET
 254 #define CONFIG_MII              /* MII PHY management */
 255 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 256 #endif
 257
 258 /*
 259  * Environment
 260  */
 261 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 262 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 263
 264 /*
 265  * Command line configuration.
 266  */
 267
 268 /*
 269  * Miscellaneous configurable options
 270  */
 271 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 272 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 273 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 274 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 275
 276 /*
 277  * For booting Linux, the board info and command line data
 278  * have to be in the first 64 MB of memory, since this is
 279  * the maximum mapped by the Linux kernel during initialization.
 280  */
 281 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 282 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 283
 284 #ifdef CONFIG_CMD_KGDB
 285 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 286 #endif
 287
 288 /*
 289  * Environment Configuration
 290  */
 291 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 292 #define CONFIG_BOOTFILE         "uImage"
 293 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 294
 295 /* default location for tftp and bootm */
 296 #define CONFIG_LOADADDR         1000000
 297
 298 #define CONFIG_HVBOOT                                   \
 299         "setenv bootargs config-addr=0x60000000; "      \
 300         "bootm 0x01000000 - 0x00f00000"
 301
 302 #ifndef CONFIG_MTD_NOR_FLASH
 303 #else
 304 #define CONFIG_FLASH_CFI_DRIVER
 305 #define CONFIG_SYS_FLASH_CFI
 306 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 307 #endif
 308
 309 #if defined(CONFIG_SPIFLASH)
 310 #define CONFIG_SYS_EXTRA_ENV_RELOC
 311 #define CONFIG_ENV_SPI_BUS              0
 312 #define CONFIG_ENV_SPI_CS               0
 313 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 314 #define CONFIG_ENV_SPI_MODE             0
 315 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 316 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 317 #define CONFIG_ENV_SECT_SIZE            0x10000
 318 #elif defined(CONFIG_SDCARD)
 319 #define CONFIG_SYS_EXTRA_ENV_RELOC
 320 #define CONFIG_SYS_MMC_ENV_DEV          0
 321 #define CONFIG_ENV_SIZE                 0x2000
 322 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 323 #elif defined(CONFIG_NAND)
 324 #define CONFIG_SYS_EXTRA_ENV_RELOC
 325 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 326 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 327 #elif defined(CONFIG_ENV_IS_NOWHERE)
 328 #define CONFIG_ENV_SIZE         0x2000
 329 #else
 330 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 331 #define CONFIG_ENV_SIZE         0x2000
 332 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 333 #endif
 334
 335 #define CONFIG_SYS_CLK_FREQ     66666666
 336 #define CONFIG_DDR_CLK_FREQ     133333333
 337
 338 #ifndef __ASSEMBLY__
 339 unsigned long get_board_sys_clk(void);
 340 unsigned long get_board_ddr_clk(void);
 341 #endif
 342
 343 /*
 344  * DDR Setup
 345  */
 346 #define CONFIG_SYS_SPD_BUS_NUM  0
 347 #define SPD_EEPROM_ADDRESS1     0x52
 348 #define SPD_EEPROM_ADDRESS2     0x54
 349 #define SPD_EEPROM_ADDRESS3     0x56
 350 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 351 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 352
 353 /*
 354  * IFC Definitions
 355  */
 356 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 357 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 358                                 + 0x8000000) | \
 359                                 CSPR_PORT_SIZE_16 | \
 360                                 CSPR_MSEL_NOR | \
 361                                 CSPR_V)
 362 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 363 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 364                                 CSPR_PORT_SIZE_16 | \
 365                                 CSPR_MSEL_NOR | \
 366                                 CSPR_V)
 367 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 368 /* NOR Flash Timing Params */
 369 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 370
 371 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 372                                 FTIM0_NOR_TEADC(0x5) | \
 373                                 FTIM0_NOR_TEAHC(0x5))
 374 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 375                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 376                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 377 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 378                                 FTIM2_NOR_TCH(0x4) | \
 379                                 FTIM2_NOR_TWPH(0x0E) | \
 380                                 FTIM2_NOR_TWP(0x1c))
 381 #define CONFIG_SYS_NOR_FTIM3    0x0
 382
 383 #define CONFIG_SYS_FLASH_QUIET_TEST
 384 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 385
 386 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 387 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 388 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 389 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 390
 391 #define CONFIG_SYS_FLASH_EMPTY_INFO
 392 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 393                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 394
 395 /* NAND Flash on IFC */
 396 #define CONFIG_NAND_FSL_IFC
 397 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 398 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 399 #define CONFIG_SYS_NAND_BASE            0xff800000
 400 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 401
 402 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 403 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 404                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 405                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 406                                 | CSPR_V)
 407 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 408
 409 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 410                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 411                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 412                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 413                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 414                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 415                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 416
 417 #define CONFIG_SYS_NAND_ONFI_DETECTION
 418
 419 /* ONFI NAND Flash mode0 Timing Params */
 420 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 421                                         FTIM0_NAND_TWP(0x18)   | \
 422                                         FTIM0_NAND_TWCHT(0x07) | \
 423                                         FTIM0_NAND_TWH(0x0a))
 424 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 425                                         FTIM1_NAND_TWBE(0x39)  | \
 426                                         FTIM1_NAND_TRR(0x0e)   | \
 427                                         FTIM1_NAND_TRP(0x18))
 428 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 429                                         FTIM2_NAND_TREH(0x0a) | \
 430                                         FTIM2_NAND_TWHRE(0x1e))
 431 #define CONFIG_SYS_NAND_FTIM3           0x0
 432
 433 #define CONFIG_SYS_NAND_DDR_LAW         11
 434 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 435 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 436
 437 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 438
 439 #if defined(CONFIG_NAND)
 440 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 441 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 442 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 443 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 444 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 445 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 446 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 447 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 448 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 449 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 450 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 451 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 452 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 453 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 454 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 455 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 456 #else
 457 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 458 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 459 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 460 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 461 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 462 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 463 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 464 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 465 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 466 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 467 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 468 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 469 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 470 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 471 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 472 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 473 #endif
 474 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 475 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 476 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 477 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 478 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 479 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 480 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 481 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 482
 483 /* CPLD on IFC */
 484 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 485 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 486 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 487 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 488                                 | CSPR_PORT_SIZE_8 \
 489                                 | CSPR_MSEL_GPCM \
 490                                 | CSPR_V)
 491
 492 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 493 #define CONFIG_SYS_CSOR3        0x0
 494
 495 /* CPLD Timing parameters for IFC CS3 */
 496 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 497                                         FTIM0_GPCM_TEADC(0x0e) | \
 498                                         FTIM0_GPCM_TEAHC(0x0e))
 499 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 500                                         FTIM1_GPCM_TRAD(0x1f))
 501 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 502                                         FTIM2_GPCM_TCH(0x8) | \
 503                                         FTIM2_GPCM_TWP(0x1f))
 504 #define CONFIG_SYS_CS3_FTIM3            0x0
 505
 506 #if defined(CONFIG_RAMBOOT_PBL)
 507 #define CONFIG_SYS_RAMBOOT
 508 #endif
 509
 510 /* I2C */
 511 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 512 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 513 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 514 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 515
 516 #define I2C_MUX_CH_DEFAULT      0x8
 517 #define I2C_MUX_CH_VOL_MONITOR  0xa
 518 #define I2C_MUX_CH_VSC3316_FS   0xc
 519 #define I2C_MUX_CH_VSC3316_BS   0xd
 520
 521 /* Voltage monitor on channel 2*/
 522 #define I2C_VOL_MONITOR_ADDR            0x40
 523 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 524 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 525 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 526
 527 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 528 #ifndef CONFIG_SPL_BUILD
 529 #define CONFIG_VID
 530 #endif
 531 #define CONFIG_VOL_MONITOR_IR36021_SET
 532 #define CONFIG_VOL_MONITOR_IR36021_READ
 533 /* The lowest and highest voltage allowed for T4240RDB */
 534 #define VDD_MV_MIN                      819
 535 #define VDD_MV_MAX                      1212
 536
 537 /*
 538  * eSPI - Enhanced SPI
 539  */
 540 #define CONFIG_SF_DEFAULT_SPEED         10000000
 541 #define CONFIG_SF_DEFAULT_MODE          0
 542
 543 /* Qman/Bman */
 544 #ifndef CONFIG_NOBQFMAN
 545 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 546 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 547 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 548 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 549 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 550 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 551 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 552 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 553 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 554                                         CONFIG_SYS_BMAN_CENA_SIZE)
 555 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 556 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 557 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 558 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 559 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 560 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 561 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 562 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 563 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 564 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 565 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 566                                         CONFIG_SYS_QMAN_CENA_SIZE)
 567 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 568 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 569
 570 #define CONFIG_SYS_DPAA_FMAN
 571 #define CONFIG_SYS_DPAA_PME
 572 #define CONFIG_SYS_PMAN
 573 #define CONFIG_SYS_DPAA_DCE
 574 #define CONFIG_SYS_DPAA_RMAN
 575 #define CONFIG_SYS_INTERLAKEN
 576
 577 /* Default address of microcode for the Linux Fman driver */
 578 #if defined(CONFIG_SPIFLASH)
 579 /*
 580  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 581  * env, so we got 0x110000.
 582  */
 583 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 584 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 585 #elif defined(CONFIG_SDCARD)
 586 /*
 587  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 588  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 589  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 590  */
 591 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 592 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 593 #elif defined(CONFIG_NAND)
 594 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 595 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 596 #else
 597 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 598 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 599 #endif
 600 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 601 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 602 #endif /* CONFIG_NOBQFMAN */
 603
 604 #ifdef CONFIG_SYS_DPAA_FMAN
 605 #define CONFIG_FMAN_ENET
 606 #define CONFIG_PHYLIB_10G
 607 #define CONFIG_PHY_VITESSE
 608 #define CONFIG_PHY_CORTINA
 609 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 610 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 611 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 612 #define CONFIG_PHY_TERANETICS
 613 #define SGMII_PHY_ADDR1 0x0
 614 #define SGMII_PHY_ADDR2 0x1
 615 #define SGMII_PHY_ADDR3 0x2
 616 #define SGMII_PHY_ADDR4 0x3
 617 #define SGMII_PHY_ADDR5 0x4
 618 #define SGMII_PHY_ADDR6 0x5
 619 #define SGMII_PHY_ADDR7 0x6
 620 #define SGMII_PHY_ADDR8 0x7
 621 #define FM1_10GEC1_PHY_ADDR     0x10
 622 #define FM1_10GEC2_PHY_ADDR     0x11
 623 #define FM2_10GEC1_PHY_ADDR     0x12
 624 #define FM2_10GEC2_PHY_ADDR     0x13
 625 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 626 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 627 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 628 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 629 #endif
 630
 631 /* SATA */
 632 #ifdef CONFIG_FSL_SATA_V2
 633 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 634 #define CONFIG_SATA1
 635 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 636 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 637 #define CONFIG_SATA2
 638 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 639 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 640
 641 #define CONFIG_LBA48
 642 #endif
 643
 644 #ifdef CONFIG_FMAN_ENET
 645 #define CONFIG_MII              /* MII PHY management */
 646 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 647 #endif
 648
 649 /*
 650 * USB
 651 */
 652 #define CONFIG_USB_EHCI_FSL
 653 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 654 #define CONFIG_HAS_FSL_DR_USB
 655
 656 #ifdef CONFIG_MMC
 657 #define CONFIG_FSL_ESDHC
 658 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 659 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 660 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 661 #endif
 662
 663
 664 #define __USB_PHY_TYPE  utmi
 665
 666 /*
 667  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 668  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 669  * interleaving. It can be cacheline, page, bank, superbank.
 670  * See doc/README.fsl-ddr for details.
 671  */
 672 #ifdef CONFIG_ARCH_T4240
 673 #define CTRL_INTLV_PREFERED 3way_4KB
 674 #else
 675 #define CTRL_INTLV_PREFERED cacheline
 676 #endif
 677
 678 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 679         "hwconfig=fsl_ddr:"                                     \
 680         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 681         "bank_intlv=auto;"                                      \
 682         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 683         "netdev=eth0\0"                                         \
 684         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 685         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 686         "tftpflash=tftpboot $loadaddr $uboot && "               \
 687         "protect off $ubootaddr +$filesize && "                 \
 688         "erase $ubootaddr +$filesize && "                       \
 689         "cp.b $loadaddr $ubootaddr $filesize && "               \
 690         "protect on $ubootaddr +$filesize && "                  \
 691         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 692         "consoledev=ttyS0\0"                                    \
 693         "ramdiskaddr=2000000\0"                                 \
 694         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 695         "fdtaddr=1e00000\0"                                     \
 696         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 697         "bdev=sda3\0"
 698
 699 #define CONFIG_HVBOOT                                   \
 700         "setenv bootargs config-addr=0x60000000; "      \
 701         "bootm 0x01000000 - 0x00f00000"
 702
 703 #define CONFIG_LINUX                                    \
 704         "setenv bootargs root=/dev/ram rw "             \
 705         "console=$consoledev,$baudrate $othbootargs;"   \
 706         "setenv ramdiskaddr 0x02000000;"                \
 707         "setenv fdtaddr 0x00c00000;"                    \
 708         "setenv loadaddr 0x1000000;"                    \
 709         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 710
 711 #define CONFIG_HDBOOT                                   \
 712         "setenv bootargs root=/dev/$bdev rw "           \
 713         "console=$consoledev,$baudrate $othbootargs;"   \
 714         "tftp $loadaddr $bootfile;"                     \
 715         "tftp $fdtaddr $fdtfile;"                       \
 716         "bootm $loadaddr - $fdtaddr"
 717
 718 #define CONFIG_NFSBOOTCOMMAND                   \
 719         "setenv bootargs root=/dev/nfs rw "     \
 720         "nfsroot=$serverip:$rootpath "          \
 721         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 722         "console=$consoledev,$baudrate $othbootargs;"   \
 723         "tftp $loadaddr $bootfile;"             \
 724         "tftp $fdtaddr $fdtfile;"               \
 725         "bootm $loadaddr - $fdtaddr"
 726
 727 #define CONFIG_RAMBOOTCOMMAND                           \
 728         "setenv bootargs root=/dev/ram rw "             \
 729         "console=$consoledev,$baudrate $othbootargs;"   \
 730         "tftp $ramdiskaddr $ramdiskfile;"               \
 731         "tftp $loadaddr $bootfile;"                     \
 732         "tftp $fdtaddr $fdtfile;"                       \
 733         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 734
 735 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 736
 737 #include <asm/fsl_secure_boot.h>
 738
 739 #endif  /* __CONFIG_H */