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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/T4240RDB.h
2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_T4240RDB
14 #define CONFIG_PHYS_64BIT
15 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_FSL_SATA_V2
21 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
23 #ifdef CONFIG_RAMBOOT_PBL
24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
27 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
30 #define CONFIG_DDR_ECC
32 #define CONFIG_CMD_REGINFO
34 /* High Level Configuration Options */
36 #define CONFIG_E500 /* BOOKE e500 family */
37 #define CONFIG_E500MC /* BOOKE e500mc family */
38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
39 #define CONFIG_MP /* support multiple processors */
41 #ifndef CONFIG_SYS_TEXT_BASE
42 #define CONFIG_SYS_TEXT_BASE 0xeff40000
45 #ifndef CONFIG_RESET_VECTOR_ADDRESS
46 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
49 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
50 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
51 #define CONFIG_FSL_IFC /* Enable IFC Support */
52 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
53 #define CONFIG_PCI /* Enable PCI/PCIE */
54 #define CONFIG_PCIE1 /* PCIE controler 1 */
55 #define CONFIG_PCIE2 /* PCIE controler 2 */
56 #define CONFIG_PCIE3 /* PCIE controler 3 */
57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
60 #define CONFIG_FSL_LAW /* Use common FSL init code */
62 #define CONFIG_ENV_OVERWRITE
65 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_SYS_CACHE_STASHING
68 #define CONFIG_BTB /* toggle branch predition */
70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
71 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
74 #define CONFIG_ENABLE_36BIT_PHYS
76 #define CONFIG_ADDR_MAP
77 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
79 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
80 #define CONFIG_SYS_MEMTEST_END 0x00400000
81 #define CONFIG_SYS_ALT_MEMTEST
82 #define CONFIG_PANIC_HANG /* do not reset board on panic */
85 * Config the L3 Cache as L3 SRAM
87 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
89 #define CONFIG_SYS_DCSRBAR 0xf0000000
90 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
95 #define CONFIG_VERY_BIG_RAM
96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
101 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
102 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
104 #define CONFIG_DDR_SPD
105 #define CONFIG_SYS_FSL_DDR3
111 #define CONFIG_SYS_FLASH_BASE 0xe0000000
112 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
117 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
118 #define CONFIG_MISC_INIT_R
120 #define CONFIG_HWCONFIG
122 /* define to use L1 as initial stack */
123 #define CONFIG_L1_INIT_RAM
124 #define CONFIG_SYS_INIT_RAM_LOCK
125 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
127 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
128 /* The assembler doesn't like typecast */
129 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
130 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
131 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
132 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
134 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
135 GENERATED_GBL_DATA_SIZE)
136 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
138 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
139 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
141 /* Serial Port - controlled on board with jumper J8
145 #define CONFIG_CONS_INDEX 1
146 #define CONFIG_SYS_NS16550
147 #define CONFIG_SYS_NS16550_SERIAL
148 #define CONFIG_SYS_NS16550_REG_SIZE 1
149 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
151 #define CONFIG_SYS_BAUDRATE_TABLE \
152 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
154 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
155 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
156 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
157 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
159 /* Use the HUSH parser */
160 #define CONFIG_SYS_HUSH_PARSER
161 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
163 /* pass open firmware flat tree */
164 #define CONFIG_OF_LIBFDT
165 #define CONFIG_OF_BOARD_SETUP
166 #define CONFIG_OF_STDOUT_VIA_ALIAS
168 /* new uImage format support */
170 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
173 #define CONFIG_SYS_I2C
174 #define CONFIG_SYS_I2C_FSL
175 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
176 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
177 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
178 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
182 * Memory space is mapped 1-1, but I/O space must start from 0.
185 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
186 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
187 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
188 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
189 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
190 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
191 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
192 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
193 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
195 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
196 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
197 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
198 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
199 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
200 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
201 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
202 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
203 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
205 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
206 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
207 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
208 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
209 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
210 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
211 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
212 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
213 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
215 /* controller 4, Base address 203000 */
216 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
217 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
218 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
219 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
220 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
221 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
224 #define CONFIG_PCI_INDIRECT_BRIDGE
225 #define CONFIG_NET_MULTI
226 #define CONFIG_PCI_PNP /* do pci plug-and-play */
229 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
230 #define CONFIG_DOS_PARTITION
231 #endif /* CONFIG_PCI */
234 #ifdef CONFIG_FSL_SATA_V2
235 #define CONFIG_LIBATA
236 #define CONFIG_FSL_SATA
238 #define CONFIG_SYS_SATA_MAX_DEVICE 2
240 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
241 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
243 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
244 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
247 #define CONFIG_CMD_SATA
248 #define CONFIG_DOS_PARTITION
249 #define CONFIG_CMD_EXT2
252 #ifdef CONFIG_FMAN_ENET
253 #define CONFIG_MII /* MII PHY management */
254 #define CONFIG_ETHPRIME "FM1@DTSEC1"
255 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
261 #define CONFIG_LOADS_ECHO /* echo on for serial download */
262 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
265 * Command line configuration.
267 #include <config_cmd_default.h>
269 #define CONFIG_CMD_DHCP
270 #define CONFIG_CMD_ELF
271 #define CONFIG_CMD_ERRATA
272 #define CONFIG_CMD_GREPENV
273 #define CONFIG_CMD_IRQ
274 #define CONFIG_CMD_I2C
275 #define CONFIG_CMD_MII
276 #define CONFIG_CMD_PING
277 #define CONFIG_CMD_SETEXPR
280 #define CONFIG_CMD_PCI
281 #define CONFIG_CMD_NET
285 * Miscellaneous configurable options
287 #define CONFIG_SYS_LONGHELP /* undef to save memory */
288 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
289 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
290 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
291 #ifdef CONFIG_CMD_KGDB
292 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
294 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
296 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
297 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
298 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
301 * For booting Linux, the board info and command line data
302 * have to be in the first 64 MB of memory, since this is
303 * the maximum mapped by the Linux kernel during initialization.
305 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
306 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
308 #ifdef CONFIG_CMD_KGDB
309 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
313 * Environment Configuration
315 #define CONFIG_ROOTPATH "/opt/nfsroot"
316 #define CONFIG_BOOTFILE "uImage"
317 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
319 /* default location for tftp and bootm */
320 #define CONFIG_LOADADDR 1000000
323 #define CONFIG_BAUDRATE 115200
325 #define CONFIG_HVBOOT \
326 "setenv bootargs config-addr=0x60000000; " \
327 "bootm 0x01000000 - 0x00f00000"
329 #ifdef CONFIG_SYS_NO_FLASH
330 #ifndef CONFIG_RAMBOOT_PBL
331 #define CONFIG_ENV_IS_NOWHERE
334 #define CONFIG_FLASH_CFI_DRIVER
335 #define CONFIG_SYS_FLASH_CFI
336 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
339 #if defined(CONFIG_SPIFLASH)
340 #define CONFIG_SYS_EXTRA_ENV_RELOC
341 #define CONFIG_ENV_IS_IN_SPI_FLASH
342 #define CONFIG_ENV_SPI_BUS 0
343 #define CONFIG_ENV_SPI_CS 0
344 #define CONFIG_ENV_SPI_MAX_HZ 10000000
345 #define CONFIG_ENV_SPI_MODE 0
346 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
347 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
348 #define CONFIG_ENV_SECT_SIZE 0x10000
349 #elif defined(CONFIG_SDCARD)
350 #define CONFIG_SYS_EXTRA_ENV_RELOC
351 #define CONFIG_ENV_IS_IN_MMC
352 #define CONFIG_SYS_MMC_ENV_DEV 0
353 #define CONFIG_ENV_SIZE 0x2000
354 #define CONFIG_ENV_OFFSET (512 * 1658)
355 #elif defined(CONFIG_NAND)
356 #define CONFIG_SYS_EXTRA_ENV_RELOC
357 #define CONFIG_ENV_IS_IN_NAND
358 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
359 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
360 #elif defined(CONFIG_ENV_IS_NOWHERE)
361 #define CONFIG_ENV_SIZE 0x2000
363 #define CONFIG_ENV_IS_IN_FLASH
364 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
365 #define CONFIG_ENV_SIZE 0x2000
366 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
369 #define CONFIG_SYS_CLK_FREQ 66666666
370 #define CONFIG_DDR_CLK_FREQ 133333333
373 unsigned long get_board_sys_clk(void);
374 unsigned long get_board_ddr_clk(void);
380 #define CONFIG_SYS_SPD_BUS_NUM 0
381 #define SPD_EEPROM_ADDRESS1 0x52
382 #define SPD_EEPROM_ADDRESS2 0x54
383 #define SPD_EEPROM_ADDRESS3 0x56
384 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
385 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
390 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
391 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
393 CSPR_PORT_SIZE_16 | \
396 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
397 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
398 CSPR_PORT_SIZE_16 | \
401 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
402 /* NOR Flash Timing Params */
403 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
405 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
406 FTIM0_NOR_TEADC(0x5) | \
407 FTIM0_NOR_TEAHC(0x5))
408 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
409 FTIM1_NOR_TRAD_NOR(0x1A) |\
410 FTIM1_NOR_TSEQRAD_NOR(0x13))
411 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
412 FTIM2_NOR_TCH(0x4) | \
413 FTIM2_NOR_TWPH(0x0E) | \
415 #define CONFIG_SYS_NOR_FTIM3 0x0
417 #define CONFIG_SYS_FLASH_QUIET_TEST
418 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
420 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
421 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
422 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
423 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
425 #define CONFIG_SYS_FLASH_EMPTY_INFO
426 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
427 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
429 /* NAND Flash on IFC */
430 #define CONFIG_NAND_FSL_IFC
431 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
432 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
433 #define CONFIG_SYS_NAND_BASE 0xff800000
434 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
436 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
437 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
438 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
439 | CSPR_MSEL_NAND /* MSEL = NAND */ \
441 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
443 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
444 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
445 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
446 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
447 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
448 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
449 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
451 #define CONFIG_SYS_NAND_ONFI_DETECTION
453 /* ONFI NAND Flash mode0 Timing Params */
454 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
455 FTIM0_NAND_TWP(0x18) | \
456 FTIM0_NAND_TWCHT(0x07) | \
457 FTIM0_NAND_TWH(0x0a))
458 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
459 FTIM1_NAND_TWBE(0x39) | \
460 FTIM1_NAND_TRR(0x0e) | \
461 FTIM1_NAND_TRP(0x18))
462 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
463 FTIM2_NAND_TREH(0x0a) | \
464 FTIM2_NAND_TWHRE(0x1e))
465 #define CONFIG_SYS_NAND_FTIM3 0x0
467 #define CONFIG_SYS_NAND_DDR_LAW 11
468 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
469 #define CONFIG_SYS_MAX_NAND_DEVICE 1
470 #define CONFIG_MTD_NAND_VERIFY_WRITE
471 #define CONFIG_CMD_NAND
473 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
475 #if defined(CONFIG_NAND)
476 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
477 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
478 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
479 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
480 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
481 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
482 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
483 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
484 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
485 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
486 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
487 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
488 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
489 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
490 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
491 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
493 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
494 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
495 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
496 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
497 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
498 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
499 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
500 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
501 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
502 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
503 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
504 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
505 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
506 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
507 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
508 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
510 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
511 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
512 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
513 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
514 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
515 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
516 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
517 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
520 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
521 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
522 #define CONFIG_SYS_CSPR3_EXT (0xf)
523 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
528 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
529 #define CONFIG_SYS_CSOR3 0x0
531 /* CPLD Timing parameters for IFC CS3 */
532 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
533 FTIM0_GPCM_TEADC(0x0e) | \
534 FTIM0_GPCM_TEAHC(0x0e))
535 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
536 FTIM1_GPCM_TRAD(0x1f))
537 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
538 FTIM2_GPCM_TCH(0x8) | \
539 FTIM2_GPCM_TWP(0x1f))
540 #define CONFIG_SYS_CS3_FTIM3 0x0
542 #if defined(CONFIG_RAMBOOT_PBL)
543 #define CONFIG_SYS_RAMBOOT
548 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
549 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
550 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
551 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
553 #define I2C_MUX_CH_DEFAULT 0x8
554 #define I2C_MUX_CH_VOL_MONITOR 0xa
555 #define I2C_MUX_CH_VSC3316_FS 0xc
556 #define I2C_MUX_CH_VSC3316_BS 0xd
558 /* Voltage monitor on channel 2*/
559 #define I2C_VOL_MONITOR_ADDR 0x40
560 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
561 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
562 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
565 * eSPI - Enhanced SPI
567 #define CONFIG_FSL_ESPI
568 #define CONFIG_SPI_FLASH
569 #define CONFIG_SPI_FLASH_SST
570 #define CONFIG_CMD_SF
571 #define CONFIG_SF_DEFAULT_SPEED 10000000
572 #define CONFIG_SF_DEFAULT_MODE 0
576 #ifndef CONFIG_NOBQFMAN
577 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
578 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
579 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
580 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
581 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
582 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
583 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
584 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
585 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
587 #define CONFIG_SYS_DPAA_FMAN
588 #define CONFIG_SYS_DPAA_PME
589 #define CONFIG_SYS_PMAN
590 #define CONFIG_SYS_DPAA_DCE
591 #define CONFIG_SYS_DPAA_RMAN
592 #define CONFIG_SYS_INTERLAKEN
594 /* Default address of microcode for the Linux Fman driver */
595 #if defined(CONFIG_SPIFLASH)
597 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
598 * env, so we got 0x110000.
600 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
601 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
602 #elif defined(CONFIG_SDCARD)
604 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
605 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
606 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
608 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
609 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
610 #elif defined(CONFIG_NAND)
611 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
612 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
614 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
615 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
617 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
618 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
619 #endif /* CONFIG_NOBQFMAN */
621 #ifdef CONFIG_SYS_DPAA_FMAN
622 #define CONFIG_FMAN_ENET
623 #define CONFIG_PHYLIB_10G
624 #define CONFIG_PHY_VITESSE
625 #define CONFIG_PHY_CORTINA
626 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
627 #define CONFIG_CORTINA_FW_LENGTH 0x40000
628 #define CONFIG_PHY_TERANETICS
629 #define SGMII_PHY_ADDR1 0x0
630 #define SGMII_PHY_ADDR2 0x1
631 #define SGMII_PHY_ADDR3 0x2
632 #define SGMII_PHY_ADDR4 0x3
633 #define SGMII_PHY_ADDR5 0x4
634 #define SGMII_PHY_ADDR6 0x5
635 #define SGMII_PHY_ADDR7 0x6
636 #define SGMII_PHY_ADDR8 0x7
637 #define FM1_10GEC1_PHY_ADDR 0x10
638 #define FM1_10GEC2_PHY_ADDR 0x11
639 #define FM2_10GEC1_PHY_ADDR 0x12
640 #define FM2_10GEC2_PHY_ADDR 0x13
641 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
642 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
643 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
644 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
649 #ifdef CONFIG_FSL_SATA_V2
650 #define CONFIG_LIBATA
651 #define CONFIG_FSL_SATA
653 #define CONFIG_SYS_SATA_MAX_DEVICE 2
655 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
656 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
658 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
659 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
662 #define CONFIG_CMD_SATA
663 #define CONFIG_DOS_PARTITION
664 #define CONFIG_CMD_EXT2
667 #ifdef CONFIG_FMAN_ENET
668 #define CONFIG_MII /* MII PHY management */
669 #define CONFIG_ETHPRIME "FM1@DTSEC1"
670 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
676 #define CONFIG_CMD_USB
677 #define CONFIG_USB_STORAGE
678 #define CONFIG_USB_EHCI
679 #define CONFIG_USB_EHCI_FSL
680 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
681 #define CONFIG_CMD_EXT2
682 #define CONFIG_HAS_FSL_DR_USB
687 #define CONFIG_FSL_ESDHC
688 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
689 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
690 #define CONFIG_CMD_MMC
691 #define CONFIG_GENERIC_MMC
692 #define CONFIG_CMD_EXT2
693 #define CONFIG_CMD_FAT
694 #define CONFIG_DOS_PARTITION
695 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
698 /* Hash command with SHA acceleration supported in hardware */
699 #ifdef CONFIG_FSL_CAAM
700 #define CONFIG_CMD_HASH
701 #define CONFIG_SHA_HW_ACCEL
704 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
706 #define __USB_PHY_TYPE utmi
709 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
710 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
711 * interleaving. It can be cacheline, page, bank, superbank.
712 * See doc/README.fsl-ddr for details.
714 #ifdef CONFIG_PPC_T4240
715 #define CTRL_INTLV_PREFERED 3way_4KB
717 #define CTRL_INTLV_PREFERED cacheline
720 #define CONFIG_EXTRA_ENV_SETTINGS \
721 "hwconfig=fsl_ddr:" \
722 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
724 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
726 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
727 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
728 "tftpflash=tftpboot $loadaddr $uboot && " \
729 "protect off $ubootaddr +$filesize && " \
730 "erase $ubootaddr +$filesize && " \
731 "cp.b $loadaddr $ubootaddr $filesize && " \
732 "protect on $ubootaddr +$filesize && " \
733 "cmp.b $loadaddr $ubootaddr $filesize\0" \
734 "consoledev=ttyS0\0" \
735 "ramdiskaddr=2000000\0" \
736 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
738 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
741 #define CONFIG_HVBOOT \
742 "setenv bootargs config-addr=0x60000000; " \
743 "bootm 0x01000000 - 0x00f00000"
745 #define CONFIG_LINUX \
746 "setenv bootargs root=/dev/ram rw " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "setenv ramdiskaddr 0x02000000;" \
749 "setenv fdtaddr 0x00c00000;" \
750 "setenv loadaddr 0x1000000;" \
751 "bootm $loadaddr $ramdiskaddr $fdtaddr"
753 #define CONFIG_HDBOOT \
754 "setenv bootargs root=/dev/$bdev rw " \
755 "console=$consoledev,$baudrate $othbootargs;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr - $fdtaddr"
760 #define CONFIG_NFSBOOTCOMMAND \
761 "setenv bootargs root=/dev/nfs rw " \
762 "nfsroot=$serverip:$rootpath " \
763 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
764 "console=$consoledev,$baudrate $othbootargs;" \
765 "tftp $loadaddr $bootfile;" \
766 "tftp $fdtaddr $fdtfile;" \
767 "bootm $loadaddr - $fdtaddr"
769 #define CONFIG_RAMBOOTCOMMAND \
770 "setenv bootargs root=/dev/ram rw " \
771 "console=$consoledev,$baudrate $othbootargs;" \
772 "tftp $ramdiskaddr $ramdiskfile;" \
773 "tftp $loadaddr $bootfile;" \
774 "tftp $fdtaddr $fdtfile;" \
775 "bootm $loadaddr $ramdiskaddr $fdtaddr"
777 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
779 #include <asm/fsl_secure_boot.h>
781 #ifdef CONFIG_SECURE_BOOT
782 /* Secure Boot target was not getting build for T4240 because of
783 * increased binary size. So the size is being reduced by removing USB
784 * which is anyways not used in Secure Environment.
786 #undef CONFIG_CMD_USB
787 #define CONFIG_CMD_BLOB
790 #endif /* __CONFIG_H */