include/configs/TOP5200.h

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
   6  *
   7  * TOP5200 differences from IceCube:
   8  * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
   9  *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
  10  * 1 SDRAM/DDRAM Bank up to 256 MB
  11  * local VPD I2C Bus is software driven and uses
  12  *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
  13  * FLASH is re-located at 0xff000000
  14  * Internal regs are at 0xf0000000
  15  * Reset jumps to 0x00000100
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC5XXX          1       /* This is an MPC5xxx CPU */
  45 #define CONFIG_MPC5200          1       /* More exactly a MPC5200 */
  46 #define CONFIG_TOP5200          1       /* ... on TOP5200 board - we need this for FEC.C */
  47
  48 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  49
  50 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  51 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  52
  53 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
  54 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  55 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
  56 #endif
  57
  58 /*
  59  * Serial console configuration
  60  */
  61 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  62 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  63 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  64
  65
  66 #ifdef CONFIG_EVAL5200          /* PCI is supported with Evaluation board only */
  67 /*
  68  * PCI Mapping:
  69  * 0x40000000 - 0x4fffffff - PCI Memory
  70  * 0x50000000 - 0x50ffffff - PCI IO Space
  71  */
  72 #  define CONFIG_PCI            1
  73 #  define CONFIG_PCI_PNP                1
  74 #  define CONFIG_PCI_SCAN_SHOW  1
  75
  76 #  define CONFIG_PCI_MEM_BUS    0x40000000
  77 #  define CONFIG_PCI_MEM_PHYS   CONFIG_PCI_MEM_BUS
  78 #  define CONFIG_PCI_MEM_SIZE   0x10000000
  79
  80 #  define CONFIG_PCI_IO_BUS     0x50000000
  81 #  define CONFIG_PCI_IO_PHYS    CONFIG_PCI_IO_BUS
  82 #  define CONFIG_PCI_IO_SIZE    0x01000000
  83
  84 #  define ADD_PCI_CMD           CFG_CMD_PCI
  85
  86 #else   /* no Evaluation board */
  87
  88 #  define ADD_PCI_CMD           0  /* no CFG_CMD_PCI */
  89
  90 #endif
  91
  92 /*
  93  * Supported commands
  94  */
  95 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  96                                 ADD_PCI_CMD     | \
  97                                 CFG_CMD_ASKENV  | \
  98                                 CFG_CMD_DATE    | \
  99                                 CFG_CMD_DHCP    | \
 100                                 CFG_CMD_I2C     | \
 101                                 CFG_CMD_EEPROM  | \
 102                                 CFG_CMD_REGINFO | \
 103                                 CFG_CMD_IMMAP   | \
 104                                 CFG_CMD_ELF     | \
 105                                 CFG_CMD_MII     | \
 106                                 CFG_CMD_BEDBUG  \
 107                               )
 108
 109 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 110 #include <cmd_confdefs.h>
 111
 112 /*
 113  * low boot
 114  */
 115 #if (TEXT_BASE == 0xFF000000)           /* Boot low with 16 MB Flash */
 116 #   define CFG_LOWBOOT          1
 117 #   define CFG_LOWBOOT16        1
 118 #endif
 119
 120 /*
 121  * Autobooting
 122  */
 123 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 124
 125 #define CONFIG_PREBOOT  "echo;" \
 126         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 127         "echo"
 128
 129 #undef  CONFIG_BOOTARGS
 130
 131 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 132         "netdev=eth0\0"                                                 \
 133         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 134                 "nfsroot=$(serverip):$(rootpath)\0"                     \
 135         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 136         "addip=setenv bootargs $(bootargs) "                            \
 137                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 138                 ":$(hostname):$(netdev):off panic=1\0"                  \
 139         "flash_nfs=run nfsargs addip;"                                  \
 140                 "bootm $(kernel_addr)\0"                                \
 141         "flash_self=run ramargs addip;"                                 \
 142                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 143         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
 144         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 145         "bootfile=/tftpboot/MPC5200/uImage\0"                           \
 146         ""
 147
 148 #define CONFIG_BOOTCOMMAND      "run flash_self"
 149
 150 /*
 151  * IPB Bus clocking configuration.
 152  */
 153 #undef CFG_IPBSPEED_133                 /* define for 133MHz speed */
 154
 155 /*
 156  * I2C configuration
 157  */
 158 /*
 159  * EEPROM configuration
 160  */
 161 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 162 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 163
 164 #define CFG_I2C_EEPROM_ADDR_LEN 2
 165 #define CFG_EEPROM_SIZE 0x2000
 166
 167 #define CONFIG_ENV_OVERWRITE
 168 #define CONFIG_MISC_INIT_R
 169
 170 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support */
 171 #define CONFIG_SOFT_I2C         1
 172
 173 #if defined (CONFIG_SOFT_I2C)
 174 #  define SDA0                  0x40
 175 #  define SCL0                  0x80
 176 #  define GPIOE0                *((volatile uchar*)(CFG_MBAR+0x0c00))
 177 #  define DDR0                  *((volatile uchar*)(CFG_MBAR+0x0c08))
 178 #  define DVO0                  *((volatile uchar*)(CFG_MBAR+0x0c0c))
 179 #  define DVI0                  *((volatile uchar*)(CFG_MBAR+0x0c20))
 180 #  define ODE0                  *((volatile uchar*)(CFG_MBAR+0x0c04))
 181 #  define I2C_INIT              {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
 182 #  define I2C_READ              ((DVI0&SDA0)?1:0)
 183 #  define I2C_SDA(x)    {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
 184 #  define I2C_SCL(x)    {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
 185 #  define I2C_DELAY             {udelay(5);}
 186 #  define I2C_ACTIVE    {DDR0|=SDA0;}
 187 #  define I2C_TRISTATE  {DDR0&=~SDA0;}
 188 #  define CFG_I2C_SPEED         100000
 189 #  define CFG_I2C_SLAVE         0x7F
 190 #endif
 191
 192 #if defined (CONFIG_HARD_I2C)
 193 #  define CFG_I2C_MODULE        2               /* Select I2C module #1 or #2 */
 194 #  define CFG_I2C_SPEED         100000  /* 100 kHz */
 195 #  define CFG_I2C_SLAVE         0x7F
 196 #endif
 197
 198 /*
 199  * Flash configuration, expect one 16 Megabyte Bank at most
 200  */
 201 #define CFG_FLASH_BASE          0xff000000
 202 #define CFG_FLASH_SIZE          0x01000000
 203 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 204 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0)
 205
 206 #define CFG_MAX_FLASH_SECT      256     /* max num of sects on one chip */
 207
 208 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 209 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 210
 211 #undef CONFIG_FLASH_16BIT       /* Flash is 8-bit */
 212
 213 /*
 214  * DRAM configuration - will be read from VPD later... TODO!
 215  */
 216 #if 0
 217 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
 218 #define CFG_DRAM_DDR            0
 219 #define CFG_DRAM_EMODE          0
 220 #define CFG_DRAM_MODE           0x008D
 221 #define CFG_DRAM_CONTROL        0x514F0000
 222 #define CFG_DRAM_CONFIG1        0xC2233A00
 223 #define CFG_DRAM_CONFIG2        0x88B70004
 224 #define CFG_DRAM_TAP_DEL        0x08
 225 #define CFG_DRAM_RAM_SIZE       0x19
 226 #endif
 227 #if 1
 228 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
 229 #define CFG_DRAM_DDR            0
 230 #define CFG_DRAM_EMODE          0
 231 #define CFG_DRAM_MODE           0x00CD
 232 #define CFG_DRAM_CONTROL        0x514F0000
 233 #define CFG_DRAM_CONFIG1        0xD2333A00
 234 #define CFG_DRAM_CONFIG2        0x8AD70004
 235 #define CFG_DRAM_TAP_DEL        0x08
 236 #define CFG_DRAM_RAM_SIZE       0x19
 237 #endif
 238
 239 /*
 240  * Environment settings
 241  */
 242 #define CFG_ENV_IS_IN_EEPROM    1       /* turn on EEPROM env feature */
 243 #define CFG_ENV_OFFSET          0x1000
 244 #define CFG_ENV_SIZE            0x0700
 245 #define CFG_I2C_EEPROM_ADDR 0x57
 246
 247 /*
 248  * VPD settings
 249  */
 250 #define CFG_FACT_OFFSET         0x1800
 251 #define CFG_FACT_SIZE           0x0800
 252 #define CFG_I2C_FACT_ADDR       0x57
 253
 254 /*
 255  * Memory map
 256  *
 257  * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
 258  */
 259 #define CFG_MBAR                        0xf0000000      /* DO NOT CHANGE this */
 260 #define CFG_SDRAM_BASE          0x00000000
 261 #define CFG_DEFAULT_MBAR        0x80000000
 262
 263 /* Use SRAM until RAM will be available */
 264 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 265 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 266
 267
 268 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 269 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 270 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 271
 272 #define CFG_MONITOR_BASE    TEXT_BASE
 273 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 274 #   define CFG_RAMBOOT          1
 275 #endif
 276
 277 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 278 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 279 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 280
 281 /*
 282  * Ethernet configuration
 283  */
 284 #define CONFIG_MPC5XXX_FEC      1
 285 #define CONFIG_FEC_10MBIT       1               /* Workaround for FEC 100Mbit problem */
 286 #define CONFIG_PHY_ADDR         0x1f
 287 #define CONFIG_PHY_TYPE         0x79c874
 288 /*
 289  * GPIO configuration:
 290  * PSC1,2,3 predefined as UART
 291  * PCI disabled
 292  * Ethernet 100 with MD
 293  */
 294 #define CFG_GPS_PORT_CONFIG     0x00058444
 295
 296 /*
 297  * Miscellaneous configurable options
 298  */
 299 #define CFG_LONGHELP                    /* undef to save memory     */
 300 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 301 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 302 #  define CFG_CBSIZE            1024    /* Console I/O Buffer Size  */
 303 #else
 304 #  define CFG_CBSIZE            256     /* Console I/O Buffer Size  */
 305 #endif
 306 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 307 #define CFG_MAXARGS             16              /* max number of command args   */
 308 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 309
 310 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 311 #define CFG_MEMTEST_END         0x01f00000      /* 1 ... 31 MB in DRAM  */
 312
 313 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 314
 315 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 316
 317 #ifdef CONFIG_EVAL5200          /* M48T08 is available with the Evaluation board only */
 318   #define CONFIG_RTC_MK48T59    1       /* use M48T08 on EVAL5200 */
 319   #define RTC(reg)              (0xf0010000+reg)
 320   /* setup CS2 for M48T08. Must MAP 64kB */
 321   #define CFG_CS2_START RTC(0)
 322   #define CFG_CS2_SIZE  0x10000
 323   /* setup CS2 configuration register: */
 324   /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
 325   /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
 326   #define CFG_CS2_CFG   0x00047800
 327 #else
 328   #define CONFIG_RTC_MPC5200    1       /* use internal MPC5200 RTC */
 329 #endif
 330
 331 /*
 332  * Various low-level settings
 333  */
 334 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 335 #define CFG_HID0_FINAL          HID0_ICE
 336
 337 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 338 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 339 #define CFG_BOOTCS_CFG          0x00047801
 340 #define CFG_CS0_START           CFG_FLASH_BASE
 341 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 342
 343 #define CFG_CS_BURST            0x00000000
 344 #define CFG_CS_DEADCYCLE        0x33333333
 345
 346 #define CFG_RESET_ADDRESS       0x7f000000
 347
 348 #endif /* __CONFIG_H */