include/configs/TQM823L.h

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  37 #define CONFIG_TQM823L          1       /* ...on a TQM8xxL module       */
  38
  39 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  40 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  41 #endif
  42
  43 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  44 #undef  CONFIG_8xx_CONS_SMC2
  45 #undef  CONFIG_8xx_CONS_NONE
  46 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  47
  48 #define CONFIG_BOOTCOUNT_LIMIT
  49
  50 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  51
  52 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  53
  54 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  55
  56 #undef  CONFIG_BOOTARGS
  57
  58 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  59         "netdev=eth0\0"                                                 \
  60         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  61                 "nfsroot=$(serverip):$(rootpath)\0"                     \
  62         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  63         "addip=setenv bootargs $(bootargs) "                            \
  64                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
  65                 ":$(hostname):$(netdev):off panic=1\0"                  \
  66         "flash_nfs=run nfsargs addip;"                                  \
  67                 "bootm $(kernel_addr)\0"                                \
  68         "flash_self=run ramargs addip;"                                 \
  69                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
  70         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
  71         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  72         "bootfile=/tftpboot/TQM860L/uImage\0"                           \
  73         "kernel_addr=40040000\0"                                        \
  74         "ramdisk_addr=40100000\0"                                       \
  75         ""
  76 #define CONFIG_BOOTCOMMAND      "run flash_self"
  77
  78 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  79 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  80
  81 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  82
  83 #ifdef CONFIG_LCD
  84 # undef  CONFIG_STATUS_LED              /* disturbs display             */
  85 #else
  86 # define CONFIG_STATUS_LED      1       /* Status LED enabled           */
  87 #endif  /* CONFIG_LCD */
  88
  89 #ifdef  CONFIG_BMS2003
  90 # define CONFIG_CAN_DRIVER      1       /* CAN Driver support enabled   */
  91 #else
  92 # undef CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  93 #endif
  94
  95 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  96
  97 #define CONFIG_MAC_PARTITION
  98 #define CONFIG_DOS_PARTITION
  99
 100 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 101
 102 #ifdef  CONFIG_SPLASH_SCREEN
 103 # define CONFIG_COMMANDS      ( CONFIG_CMD_DFL  | \
 104                                 CFG_CMD_ASKENV  | \
 105                                 CFG_CMD_BMP     | \
 106                                 CFG_CMD_DATE    | \
 107                                 CFG_CMD_DHCP    | \
 108                                 CFG_CMD_IDE     )
 109 #else
 110 # define CONFIG_COMMANDS      ( CONFIG_CMD_DFL  | \
 111                                 CFG_CMD_ASKENV  | \
 112                                 CFG_CMD_DATE    | \
 113                                 CFG_CMD_DHCP    | \
 114                                 CFG_CMD_IDE     )
 115 #endif
 116
 117 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 118 #include <cmd_confdefs.h>
 119
 120 /*
 121  * Miscellaneous configurable options
 122  */
 123 #define CFG_LONGHELP                    /* undef to save memory         */
 124 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 125
 126 #if 0
 127 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
 128 #endif
 129 #ifdef  CFG_HUSH_PARSER
 130 #define CFG_PROMPT_HUSH_PS2     "> "
 131 #endif
 132
 133 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 134 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 135 #else
 136 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 137 #endif
 138 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 139 #define CFG_MAXARGS             16      /* max number of command args   */
 140 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 141
 142 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 143 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 144
 145 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 146
 147 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 148
 149 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 150
 151 /*
 152  * Low Level Configuration Settings
 153  * (address mappings, register initial values, etc.)
 154  * You should know what you are doing if you make changes here.
 155  */
 156 /*-----------------------------------------------------------------------
 157  * Internal Memory Mapped Register
 158  */
 159 #define CFG_IMMR                0xFFF00000
 160
 161 /*-----------------------------------------------------------------------
 162  * Definitions for initial stack pointer and data area (in DPRAM)
 163  */
 164 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 165 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 166 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 167 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 168 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 169
 170 /*-----------------------------------------------------------------------
 171  * Start addresses for the final memory configuration
 172  * (Set up by the startup code)
 173  * Please note that CFG_SDRAM_BASE _must_ start at 0
 174  */
 175 #define CFG_SDRAM_BASE          0x00000000
 176 #define CFG_FLASH_BASE          0x40000000
 177 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 178 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 179 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 180
 181 /*
 182  * For booting Linux, the board info and command line data
 183  * have to be in the first 8 MB of memory, since this is
 184  * the maximum mapped by the Linux kernel during initialization.
 185  */
 186 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 187
 188 /*-----------------------------------------------------------------------
 189  * FLASH organization
 190  */
 191 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 192 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 193
 194 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 195 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 196
 197 #define CFG_ENV_IS_IN_FLASH     1
 198 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 199 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 200
 201 /* Address and size of Redundant Environment Sector     */
 202 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 203 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 204
 205 /*-----------------------------------------------------------------------
 206  * Hardware Information Block
 207  */
 208 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 209 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 210 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 211
 212 /*-----------------------------------------------------------------------
 213  * Cache Configuration
 214  */
 215 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 216 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 217 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 218 #endif
 219
 220 /*-----------------------------------------------------------------------
 221  * SYPCR - System Protection Control                            11-9
 222  * SYPCR can only be written once after reset!
 223  *-----------------------------------------------------------------------
 224  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 225  */
 226 #if defined(CONFIG_WATCHDOG)
 227 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 228                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 229 #else
 230 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 231 #endif
 232
 233 /*-----------------------------------------------------------------------
 234  * SIUMCR - SIU Module Configuration                            11-6
 235  *-----------------------------------------------------------------------
 236  * PCMCIA config., multi-function pin tri-state
 237  */
 238 #ifndef CONFIG_CAN_DRIVER
 239 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 240 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 241 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 242 #endif  /* CONFIG_CAN_DRIVER */
 243
 244 /*-----------------------------------------------------------------------
 245  * TBSCR - Time Base Status and Control                         11-26
 246  *-----------------------------------------------------------------------
 247  * Clear Reference Interrupt Status, Timebase freezing enabled
 248  */
 249 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 250
 251 /*-----------------------------------------------------------------------
 252  * RTCSC - Real-Time Clock Status and Control Register          11-27
 253  *-----------------------------------------------------------------------
 254  */
 255 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 256
 257 /*-----------------------------------------------------------------------
 258  * PISCR - Periodic Interrupt Status and Control                11-31
 259  *-----------------------------------------------------------------------
 260  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 261  */
 262 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 263
 264 /*-----------------------------------------------------------------------
 265  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 266  *-----------------------------------------------------------------------
 267  * Reset PLL lock status sticky bit, timer expired status bit and timer
 268  * interrupt status bit
 269  *
 270  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 271  */
 272 #ifdef  CONFIG_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 273 #define CFG_PLPRCR                                                      \
 274                 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 275 #else                   /* up to 66 MHz we use a 1:1 clock */
 276 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 277 #endif  /* CONFIG_80MHz */
 278
 279 /*-----------------------------------------------------------------------
 280  * SCCR - System Clock and reset Control Register               15-27
 281  *-----------------------------------------------------------------------
 282  * Set clock output, timebase and RTC source and divider,
 283  * power management and some other internal clocks
 284  */
 285 #define SCCR_MASK       SCCR_EBDF11
 286 #ifdef  CONFIG_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 287 #define CFG_SCCR        (/* SCCR_TBS  | */ \
 288                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 289                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 290                          SCCR_DFALCD00)
 291 #else                   /* up to 66 MHz we use a 1:1 clock */
 292 #define CFG_SCCR        (SCCR_TBS     | \
 293                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 294                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 295                          SCCR_DFALCD00)
 296 #endif  /* CONFIG_80MHz */
 297
 298 /*-----------------------------------------------------------------------
 299  * PCMCIA stuff
 300  *-----------------------------------------------------------------------
 301  *
 302  */
 303 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 304 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 305 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 306 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 307 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 308 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 309 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 310 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 311
 312 /*-----------------------------------------------------------------------
 313  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 314  *-----------------------------------------------------------------------
 315  */
 316
 317 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 318
 319 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 320 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 321 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 322
 323 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 324 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 325
 326 #define CFG_ATA_IDE0_OFFSET     0x0000
 327
 328 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 329
 330 /* Offset for data I/O                  */
 331 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 332
 333 /* Offset for normal register accesses  */
 334 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 335
 336 /* Offset for alternate registers       */
 337 #define CFG_ATA_ALT_OFFSET      0x0100
 338
 339 /*-----------------------------------------------------------------------
 340  *
 341  *-----------------------------------------------------------------------
 342  *
 343  */
 344 #define CFG_DER 0
 345
 346 /*
 347  * Init Memory Controller:
 348  *
 349  * BR0/1 and OR0/1 (FLASH)
 350  */
 351
 352 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 353 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 354
 355 /* used to re-map FLASH both when starting from SRAM or FLASH:
 356  * restrict access enough to keep SRAM working (if any)
 357  * but not too much to meddle with FLASH accesses
 358  */
 359 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 360 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 361
 362 /*
 363  * FLASH timing:
 364  */
 365 #if   defined(CONFIG_80MHz)
 366 /* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
 367 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
 368                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 369 #elif defined(CONFIG_66MHz)
 370 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 371 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 372                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 373 #else           /*   50 MHz */
 374 /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
 375 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 376                                  OR_SCY_2_CLK | OR_EHTR | OR_BI)
 377 #endif  /*CONFIG_??MHz */
 378
 379 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 380 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 381 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 382
 383 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 384 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 385 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 386
 387 /*
 388  * BR2/3 and OR2/3 (SDRAM)
 389  *
 390  */
 391 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 392 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 393 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 394
 395 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 396 #define CFG_OR_TIMING_SDRAM     0x00000A00
 397
 398 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 399 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 400
 401 #ifndef CONFIG_CAN_DRIVER
 402 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 403 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 404 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 405 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 406 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 407 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 408 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 409                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 410 #endif  /* CONFIG_CAN_DRIVER */
 411
 412 /*
 413  * Memory Periodic Timer Prescaler
 414  *
 415  * The Divider for PTA (refresh timer) configuration is based on an
 416  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 417  * the number of chip selects (NCS) and the actually needed refresh
 418  * rate is done by setting MPTPR.
 419  *
 420  * PTA is calculated from
 421  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 422  *
 423  *      gclk      CPU clock (not bus clock!)
 424  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 425  *
 426  * 4096  Rows from SDRAM example configuration
 427  * 1000  factor s -> ms
 428  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 429  *    4  Number of refresh cycles per period
 430  *   64  Refresh cycle in ms per number of rows
 431  * --------------------------------------------
 432  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 433  *
 434  * 50 MHz => 50.000.000 / Divider =  98
 435  * 66 Mhz => 66.000.000 / Divider = 129
 436  * 80 Mhz => 80.000.000 / Divider = 156
 437  */
 438 #if   defined(CONFIG_80MHz)
 439 #define CFG_MAMR_PTA            156
 440 #elif defined(CONFIG_66MHz)
 441 #define CFG_MAMR_PTA            129
 442 #else           /*   50 MHz */
 443 #define CFG_MAMR_PTA             98
 444 #endif  /*CONFIG_??MHz */
 445
 446 /*
 447  * For 16 MBit, refresh rates could be 31.3 us
 448  * (= 64 ms / 2K = 125 / quad bursts).
 449  * For a simpler initialization, 15.6 us is used instead.
 450  *
 451  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 452  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 453  */
 454 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 455 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 456
 457 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 458 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 459 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 460
 461 /*
 462  * MAMR settings for SDRAM
 463  */
 464
 465 /* 8 column SDRAM */
 466 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 467                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 468                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 469 /* 9 column SDRAM */
 470 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 471                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 472                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 473
 474
 475 /*
 476  * Internal Definitions
 477  *
 478  * Boot Flags
 479  */
 480 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 481 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 482
 483 #endif  /* __CONFIG_H */