include/configs/TQM823L.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  21 #define CONFIG_TQM823L          1       /* ...on a TQM8xxL module       */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  26 #define CONFIG_MPC8XX_LCD
  27 #define CONFIG_LCD_LOGO         1       /* print our logo on the LCD    */
  28 #define CONFIG_LCD_INFO         1       /* ... and some board info      */
  29 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  30 #endif
  31
  32 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  33 #define CONFIG_SYS_SMC_RXBUFLEN 128
  34 #define CONFIG_SYS_MAXIDLE      10
  35
  36 #define CONFIG_BOOTCOUNT_LIMIT
  37
  38
  39 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  40
  41 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  42
  43 #undef  CONFIG_BOOTARGS
  44
  45 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  46         "netdev=eth0\0"                                                 \
  47         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  48                 "nfsroot=${serverip}:${rootpath}\0"                     \
  49         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  50         "addip=setenv bootargs ${bootargs} "                            \
  51                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  52                 ":${hostname}:${netdev}:off panic=1\0"                  \
  53         "flash_nfs=run nfsargs addip;"                                  \
  54                 "bootm ${kernel_addr}\0"                                \
  55         "flash_self=run ramargs addip;"                                 \
  56                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  57         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  58         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  59         "hostname=TQM823L\0"                                            \
  60         "bootfile=TQM823L/uImage\0"                                     \
  61         "fdt_addr=40040000\0"                                           \
  62         "kernel_addr=40060000\0"                                        \
  63         "ramdisk_addr=40200000\0"                                       \
  64         "u-boot=TQM823L/u-image.bin\0"                                  \
  65         "load=tftp 200000 ${u-boot}\0"                                  \
  66         "update=prot off 40000000 +${filesize};"                        \
  67                 "era 40000000 +${filesize};"                            \
  68                 "cp.b 200000 40000000 ${filesize};"                     \
  69                 "sete filesize;save\0"                                  \
  70         ""
  71 #define CONFIG_BOOTCOMMAND      "run flash_self"
  72
  73 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  74 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  75
  76 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  77
  78 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_SUBNETMASK
  84 #define CONFIG_BOOTP_GATEWAY
  85 #define CONFIG_BOOTP_HOSTNAME
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88
  89 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #define CONFIG_CMD_DATE
  95 #define CONFIG_CMD_IDE
  96 #define CONFIG_CMD_JFFS2
  97
  98 #define CONFIG_NETCONSOLE
  99
 100 /*
 101  * Miscellaneous configurable options
 102  */
 103 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 104
 105 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 106
 107 #if defined(CONFIG_CMD_KGDB)
 108 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 109 #else
 110 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 111 #endif
 112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 113 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 114 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 115
 116 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 117 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 118
 119 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 120
 121 /*
 122  * Low Level Configuration Settings
 123  * (address mappings, register initial values, etc.)
 124  * You should know what you are doing if you make changes here.
 125  */
 126 /*-----------------------------------------------------------------------
 127  * Internal Memory Mapped Register
 128  */
 129 #define CONFIG_SYS_IMMR         0xFFF00000
 130
 131 /*-----------------------------------------------------------------------
 132  * Definitions for initial stack pointer and data area (in DPRAM)
 133  */
 134 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 135 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 136 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 137 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 138
 139 /*-----------------------------------------------------------------------
 140  * Start addresses for the final memory configuration
 141  * (Set up by the startup code)
 142  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 143  */
 144 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 145 #define CONFIG_SYS_FLASH_BASE           0x40000000
 146 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 148 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 149
 150 /*
 151  * For booting Linux, the board info and command line data
 152  * have to be in the first 8 MB of memory, since this is
 153  * the maximum mapped by the Linux kernel during initialization.
 154  */
 155 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 156
 157 /*-----------------------------------------------------------------------
 158  * FLASH organization
 159  */
 160
 161 /* use CFI flash driver */
 162 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 163 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 164 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 165 #define CONFIG_SYS_FLASH_EMPTY_INFO
 166 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 167 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks */
 168 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 169
 170 #define CONFIG_ENV_IS_IN_FLASH  1
 171 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 172 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 173
 174 /* Address and size of Redundant Environment Sector     */
 175 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 176 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 177
 178 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 179
 180 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 181
 182 /*-----------------------------------------------------------------------
 183  * Dynamic MTD partition support
 184  */
 185 #define CONFIG_CMD_MTDPARTS
 186 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 187 #define CONFIG_FLASH_CFI_MTD
 188 #define MTDIDS_DEFAULT          "nor0=TQM8xxL-0"
 189
 190 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxL-0:256k(u-boot),"      \
 191                                                 "128k(dtb),"            \
 192                                                 "1664k(kernel),"        \
 193                                                 "2m(rootfs),"           \
 194                                                 "4m(data)"
 195
 196 /*-----------------------------------------------------------------------
 197  * Hardware Information Block
 198  */
 199 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 200 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 201 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 202
 203 /*-----------------------------------------------------------------------
 204  * Cache Configuration
 205  */
 206 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 207 #if defined(CONFIG_CMD_KGDB)
 208 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 209 #endif
 210
 211 /*-----------------------------------------------------------------------
 212  * SYPCR - System Protection Control                            11-9
 213  * SYPCR can only be written once after reset!
 214  *-----------------------------------------------------------------------
 215  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 216  */
 217 #if defined(CONFIG_WATCHDOG)
 218 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 219                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 220 #else
 221 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 222 #endif
 223
 224 /*-----------------------------------------------------------------------
 225  * SIUMCR - SIU Module Configuration                            11-6
 226  *-----------------------------------------------------------------------
 227  * PCMCIA config., multi-function pin tri-state
 228  */
 229 #ifndef CONFIG_CAN_DRIVER
 230 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 231 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 232 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 233 #endif  /* CONFIG_CAN_DRIVER */
 234
 235 /*-----------------------------------------------------------------------
 236  * TBSCR - Time Base Status and Control                         11-26
 237  *-----------------------------------------------------------------------
 238  * Clear Reference Interrupt Status, Timebase freezing enabled
 239  */
 240 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 241
 242 /*-----------------------------------------------------------------------
 243  * RTCSC - Real-Time Clock Status and Control Register          11-27
 244  *-----------------------------------------------------------------------
 245  */
 246 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 247
 248 /*-----------------------------------------------------------------------
 249  * PISCR - Periodic Interrupt Status and Control                11-31
 250  *-----------------------------------------------------------------------
 251  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 252  */
 253 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 254
 255 /*-----------------------------------------------------------------------
 256  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 257  *-----------------------------------------------------------------------
 258  * Reset PLL lock status sticky bit, timer expired status bit and timer
 259  * interrupt status bit
 260  */
 261 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 262
 263 /*-----------------------------------------------------------------------
 264  * SCCR - System Clock and reset Control Register               15-27
 265  *-----------------------------------------------------------------------
 266  * Set clock output, timebase and RTC source and divider,
 267  * power management and some other internal clocks
 268  */
 269 #define SCCR_MASK       SCCR_EBDF11
 270 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 271                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 272                          SCCR_DFALCD00)
 273
 274 /*-----------------------------------------------------------------------
 275  * PCMCIA stuff
 276  *-----------------------------------------------------------------------
 277  *
 278  */
 279 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 280 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 281 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 282 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 283 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 284 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 285 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 286 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 287
 288 /*-----------------------------------------------------------------------
 289  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 290  *-----------------------------------------------------------------------
 291  */
 292
 293 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 294 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 295
 296 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 297 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 298 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 299
 300 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 301 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 302
 303 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 304
 305 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 306
 307 /* Offset for data I/O                  */
 308 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 309
 310 /* Offset for normal register accesses  */
 311 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 312
 313 /* Offset for alternate registers       */
 314 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 315
 316 /*-----------------------------------------------------------------------
 317  *
 318  *-----------------------------------------------------------------------
 319  *
 320  */
 321 #define CONFIG_SYS_DER  0
 322
 323 /*
 324  * Init Memory Controller:
 325  *
 326  * BR0/1 and OR0/1 (FLASH)
 327  */
 328
 329 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 330 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 331
 332 /* used to re-map FLASH both when starting from SRAM or FLASH:
 333  * restrict access enough to keep SRAM working (if any)
 334  * but not too much to meddle with FLASH accesses
 335  */
 336 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 337 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 338
 339 /*
 340  * FLASH timing:
 341  */
 342 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 343                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 344
 345 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 346 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 347 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 348
 349 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 350 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 351 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 352
 353 /*
 354  * BR2/3 and OR2/3 (SDRAM)
 355  *
 356  */
 357 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 358 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 359 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 360
 361 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 362 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 363
 364 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 365 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 366
 367 #ifndef CONFIG_CAN_DRIVER
 368 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 369 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 370 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 371 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 372 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 373 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 374 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 375                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 376 #endif  /* CONFIG_CAN_DRIVER */
 377
 378 /*
 379  * Memory Periodic Timer Prescaler
 380  *
 381  * The Divider for PTA (refresh timer) configuration is based on an
 382  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 383  * the number of chip selects (NCS) and the actually needed refresh
 384  * rate is done by setting MPTPR.
 385  *
 386  * PTA is calculated from
 387  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 388  *
 389  *      gclk      CPU clock (not bus clock!)
 390  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 391  *
 392  * 4096  Rows from SDRAM example configuration
 393  * 1000  factor s -> ms
 394  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 395  *    4  Number of refresh cycles per period
 396  *   64  Refresh cycle in ms per number of rows
 397  * --------------------------------------------
 398  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 399  *
 400  * 50 MHz => 50.000.000 / Divider =  98
 401  * 66 Mhz => 66.000.000 / Divider = 129
 402  * 80 Mhz => 80.000.000 / Divider = 156
 403  */
 404
 405 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 406 #define CONFIG_SYS_MAMR_PTA     98
 407
 408 /*
 409  * For 16 MBit, refresh rates could be 31.3 us
 410  * (= 64 ms / 2K = 125 / quad bursts).
 411  * For a simpler initialization, 15.6 us is used instead.
 412  *
 413  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 414  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 415  */
 416 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 417 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 418
 419 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 420 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 421 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 422
 423 /*
 424  * MAMR settings for SDRAM
 425  */
 426
 427 /* 8 column SDRAM */
 428 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 429                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 430                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 431 /* 9 column SDRAM */
 432 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 433                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 434                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 435
 436 #define CONFIG_HWCONFIG         1
 437
 438 #endif  /* __CONFIG_H */