include/configs/TQM823L.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  37 #define CONFIG_TQM823L          1       /* ...on a TQM8xxL module       */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40000000
  40
  41 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  42 #define CONFIG_MPC8XX_LCD
  43 #define CONFIG_LCD_LOGO         1       /* print our logo on the LCD    */
  44 #define CONFIG_LCD_INFO         1       /* ... and some board info      */
  45 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  46 #endif
  47
  48 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  49 #define CONFIG_SYS_SMC_RXBUFLEN 128
  50 #define CONFIG_SYS_MAXIDLE      10
  51 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  52
  53 #define CONFIG_BOOTCOUNT_LIMIT
  54
  55 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  56
  57 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  58
  59 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  60
  61 #undef  CONFIG_BOOTARGS
  62
  63 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  64         "netdev=eth0\0"                                                 \
  65         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  66                 "nfsroot=${serverip}:${rootpath}\0"                     \
  67         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  68         "addip=setenv bootargs ${bootargs} "                            \
  69                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  70                 ":${hostname}:${netdev}:off panic=1\0"                  \
  71         "flash_nfs=run nfsargs addip;"                                  \
  72                 "bootm ${kernel_addr}\0"                                \
  73         "flash_self=run ramargs addip;"                                 \
  74                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  75         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  76         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  77         "hostname=TQM823L\0"                                            \
  78         "bootfile=TQM823L/uImage\0"                                     \
  79         "fdt_addr=40040000\0"                                           \
  80         "kernel_addr=40060000\0"                                        \
  81         "ramdisk_addr=40200000\0"                                       \
  82         "u-boot=TQM823L/u-image.bin\0"                                  \
  83         "load=tftp 200000 ${u-boot}\0"                                  \
  84         "update=prot off 40000000 +${filesize};"                        \
  85                 "era 40000000 +${filesize};"                            \
  86                 "cp.b 200000 40000000 ${filesize};"                     \
  87                 "sete filesize;save\0"                                  \
  88         ""
  89 #define CONFIG_BOOTCOMMAND      "run flash_self"
  90
  91 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  92 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  93
  94 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  95
  96 #if defined(CONFIG_LCD)
  97 # undef  CONFIG_STATUS_LED              /* disturbs display             */
  98 #else
  99 # define CONFIG_STATUS_LED      1       /* Status LED enabled           */
 100 #endif  /* CONFIG_LCD */
 101
 102 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 103
 104 /*
 105  * BOOTP options
 106  */
 107 #define CONFIG_BOOTP_SUBNETMASK
 108 #define CONFIG_BOOTP_GATEWAY
 109 #define CONFIG_BOOTP_HOSTNAME
 110 #define CONFIG_BOOTP_BOOTPATH
 111 #define CONFIG_BOOTP_BOOTFILESIZE
 112
 113
 114 #define CONFIG_MAC_PARTITION
 115 #define CONFIG_DOS_PARTITION
 116
 117 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 118
 119
 120 /*
 121  * Command line configuration.
 122  */
 123 #include <config_cmd_default.h>
 124
 125 #define CONFIG_CMD_ASKENV
 126 #define CONFIG_CMD_DATE
 127 #define CONFIG_CMD_DHCP
 128 #define CONFIG_CMD_ELF
 129 #define CONFIG_CMD_EXT2
 130 #define CONFIG_CMD_IDE
 131 #define CONFIG_CMD_JFFS2
 132 #define CONFIG_CMD_NFS
 133 #define CONFIG_CMD_SNTP
 134
 135 #ifdef  CONFIG_SPLASH_SCREEN
 136     #define CONFIG_CMD_BMP
 137 #endif
 138
 139
 140 #define CONFIG_NETCONSOLE
 141
 142 /*
 143  * Miscellaneous configurable options
 144  */
 145 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 146 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 147
 148 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 149 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 150
 151 #if defined(CONFIG_CMD_KGDB)
 152 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 153 #else
 154 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 155 #endif
 156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 157 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 158 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 159
 160 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 161 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 162
 163 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 164
 165 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 166
 167 /*
 168  * Low Level Configuration Settings
 169  * (address mappings, register initial values, etc.)
 170  * You should know what you are doing if you make changes here.
 171  */
 172 /*-----------------------------------------------------------------------
 173  * Internal Memory Mapped Register
 174  */
 175 #define CONFIG_SYS_IMMR         0xFFF00000
 176
 177 /*-----------------------------------------------------------------------
 178  * Definitions for initial stack pointer and data area (in DPRAM)
 179  */
 180 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 183 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 184
 185 /*-----------------------------------------------------------------------
 186  * Start addresses for the final memory configuration
 187  * (Set up by the startup code)
 188  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 189  */
 190 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 191 #define CONFIG_SYS_FLASH_BASE           0x40000000
 192 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 194 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 195
 196 /*
 197  * For booting Linux, the board info and command line data
 198  * have to be in the first 8 MB of memory, since this is
 199  * the maximum mapped by the Linux kernel during initialization.
 200  */
 201 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 202
 203 /*-----------------------------------------------------------------------
 204  * FLASH organization
 205  */
 206
 207 /* use CFI flash driver */
 208 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 209 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 210 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 211 #define CONFIG_SYS_FLASH_EMPTY_INFO
 212 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 215
 216 #define CONFIG_ENV_IS_IN_FLASH  1
 217 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 218 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 219
 220 /* Address and size of Redundant Environment Sector     */
 221 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 222 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 223
 224 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 225
 226 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 227
 228 /*-----------------------------------------------------------------------
 229  * Dynamic MTD partition support
 230  */
 231 #define CONFIG_CMD_MTDPARTS
 232 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 233 #define CONFIG_FLASH_CFI_MTD
 234 #define MTDIDS_DEFAULT          "nor0=TQM8xxL-0"
 235
 236 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxL-0:256k(u-boot),"      \
 237                                                 "128k(dtb),"            \
 238                                                 "1664k(kernel),"        \
 239                                                 "2m(rootfs),"           \
 240                                                 "4m(data)"
 241
 242 /*-----------------------------------------------------------------------
 243  * Hardware Information Block
 244  */
 245 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 246 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 247 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 248
 249 /*-----------------------------------------------------------------------
 250  * Cache Configuration
 251  */
 252 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 253 #if defined(CONFIG_CMD_KGDB)
 254 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 255 #endif
 256
 257 /*-----------------------------------------------------------------------
 258  * SYPCR - System Protection Control                            11-9
 259  * SYPCR can only be written once after reset!
 260  *-----------------------------------------------------------------------
 261  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 262  */
 263 #if defined(CONFIG_WATCHDOG)
 264 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 265                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 266 #else
 267 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 268 #endif
 269
 270 /*-----------------------------------------------------------------------
 271  * SIUMCR - SIU Module Configuration                            11-6
 272  *-----------------------------------------------------------------------
 273  * PCMCIA config., multi-function pin tri-state
 274  */
 275 #ifndef CONFIG_CAN_DRIVER
 276 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 277 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 278 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 279 #endif  /* CONFIG_CAN_DRIVER */
 280
 281 /*-----------------------------------------------------------------------
 282  * TBSCR - Time Base Status and Control                         11-26
 283  *-----------------------------------------------------------------------
 284  * Clear Reference Interrupt Status, Timebase freezing enabled
 285  */
 286 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 287
 288 /*-----------------------------------------------------------------------
 289  * RTCSC - Real-Time Clock Status and Control Register          11-27
 290  *-----------------------------------------------------------------------
 291  */
 292 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 293
 294 /*-----------------------------------------------------------------------
 295  * PISCR - Periodic Interrupt Status and Control                11-31
 296  *-----------------------------------------------------------------------
 297  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 298  */
 299 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 300
 301 /*-----------------------------------------------------------------------
 302  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 303  *-----------------------------------------------------------------------
 304  * Reset PLL lock status sticky bit, timer expired status bit and timer
 305  * interrupt status bit
 306  */
 307 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 308
 309 /*-----------------------------------------------------------------------
 310  * SCCR - System Clock and reset Control Register               15-27
 311  *-----------------------------------------------------------------------
 312  * Set clock output, timebase and RTC source and divider,
 313  * power management and some other internal clocks
 314  */
 315 #define SCCR_MASK       SCCR_EBDF11
 316 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 317                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 318                          SCCR_DFALCD00)
 319
 320 /*-----------------------------------------------------------------------
 321  * PCMCIA stuff
 322  *-----------------------------------------------------------------------
 323  *
 324  */
 325 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 326 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 327 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 328 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 329 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 330 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 331 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 332 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 333
 334 /*-----------------------------------------------------------------------
 335  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 336  *-----------------------------------------------------------------------
 337  */
 338
 339 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 340 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 341
 342 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 343 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 344 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 345
 346 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 347 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 348
 349 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 350
 351 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 352
 353 /* Offset for data I/O                  */
 354 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 355
 356 /* Offset for normal register accesses  */
 357 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 358
 359 /* Offset for alternate registers       */
 360 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 361
 362 /*-----------------------------------------------------------------------
 363  *
 364  *-----------------------------------------------------------------------
 365  *
 366  */
 367 #define CONFIG_SYS_DER  0
 368
 369 /*
 370  * Init Memory Controller:
 371  *
 372  * BR0/1 and OR0/1 (FLASH)
 373  */
 374
 375 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 376 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 377
 378 /* used to re-map FLASH both when starting from SRAM or FLASH:
 379  * restrict access enough to keep SRAM working (if any)
 380  * but not too much to meddle with FLASH accesses
 381  */
 382 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 383 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 384
 385 /*
 386  * FLASH timing:
 387  */
 388 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 389                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 390
 391 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 392 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 393 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 394
 395 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 396 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 397 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 398
 399 /*
 400  * BR2/3 and OR2/3 (SDRAM)
 401  *
 402  */
 403 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 404 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 405 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 406
 407 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 408 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 409
 410 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 411 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 412
 413 #ifndef CONFIG_CAN_DRIVER
 414 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 415 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 416 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 417 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 418 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 419 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 420 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 421                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 422 #endif  /* CONFIG_CAN_DRIVER */
 423
 424 /*
 425  * Memory Periodic Timer Prescaler
 426  *
 427  * The Divider for PTA (refresh timer) configuration is based on an
 428  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 429  * the number of chip selects (NCS) and the actually needed refresh
 430  * rate is done by setting MPTPR.
 431  *
 432  * PTA is calculated from
 433  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 434  *
 435  *      gclk      CPU clock (not bus clock!)
 436  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 437  *
 438  * 4096  Rows from SDRAM example configuration
 439  * 1000  factor s -> ms
 440  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 441  *    4  Number of refresh cycles per period
 442  *   64  Refresh cycle in ms per number of rows
 443  * --------------------------------------------
 444  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 445  *
 446  * 50 MHz => 50.000.000 / Divider =  98
 447  * 66 Mhz => 66.000.000 / Divider = 129
 448  * 80 Mhz => 80.000.000 / Divider = 156
 449  */
 450
 451 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 452 #define CONFIG_SYS_MAMR_PTA     98
 453
 454 /*
 455  * For 16 MBit, refresh rates could be 31.3 us
 456  * (= 64 ms / 2K = 125 / quad bursts).
 457  * For a simpler initialization, 15.6 us is used instead.
 458  *
 459  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 460  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 461  */
 462 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 463 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 464
 465 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 466 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 467 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 468
 469 /*
 470  * MAMR settings for SDRAM
 471  */
 472
 473 /* 8 column SDRAM */
 474 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 475                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 476                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 477 /* 9 column SDRAM */
 478 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 479                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 480                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 481
 482 /* pass open firmware flat tree */
 483 #define CONFIG_OF_LIBFDT        1
 484 #define CONFIG_OF_BOARD_SETUP   1
 485 #define CONFIG_HWCONFIG         1
 486
 487 #endif  /* __CONFIG_H */