include/configs/TQM8260.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Imported from global configuration:
  33  *      CONFIG_MPC8255
  34  *      CONFIG_MPC8265
  35  *      CONFIG_200MHz
  36  *      CONFIG_266MHz
  37  *      CONFIG_300MHz
  38  *      CONFIG_L2_CACHE
  39  *      CONFIG_BUSMODE_60x
  40  */
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  48
  49 #if 0
  50 #define CONFIG_TQM8260          100     /* ...on a TQM8260 module Rev.100       */
  51 #else
  52 #define CONFIG_TQM8260          200     /* ...on a TQM8260 module Rev.200       */
  53 #endif
  54
  55 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1                      */
  56
  57 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  58
  59 #define CONFIG_BOOTCOUNT_LIMIT
  60
  61 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  62 #define CONFIG_BAUDRATE         230400
  63 #else
  64 #define CONFIG_BAUDRATE         9600
  65 #endif
  66
  67 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  68
  69 #undef  CONFIG_BOOTARGS
  70
  71 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  72         "netdev=eth0\0"                                                 \
  73         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  74                 "nfsroot=$(serverip):$(rootpath)\0"                     \
  75         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  76         "addip=setenv bootargs $(bootargs) "                            \
  77                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
  78                 ":$(hostname):$(netdev):off panic=1\0"                  \
  79         "flash_nfs=run nfsargs addip;"                                  \
  80                 "bootm $(kernel_addr)\0"                                \
  81         "flash_self=run ramargs addip;"                                 \
  82                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
  83         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
  84         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  85         "bootfile=/tftpboot/TQM8260/uImage\0"                           \
  86         "kernel_addr=40040000\0"                                        \
  87         "ramdisk_addr=40100000\0"                                       \
  88         ""
  89 #define CONFIG_BOOTCOMMAND      "run flash_self"
  90
  91 /* enable I2C and select the hardware/software driver */
  92 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  93 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  94 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  95 #define CFG_I2C_SLAVE           0x7F
  96
  97 /*
  98  * Software (bit-bang) I2C driver configuration
  99  */
 100
 101 /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
 102 #if (CONFIG_TQM8260 <= 100)
 103
 104 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 105 #define I2C_ACTIVE      (iop->pdir |=  0x00020000)
 106 #define I2C_TRISTATE    (iop->pdir &= ~0x00020000)
 107 #define I2C_READ        ((iop->pdat & 0x00020000) != 0)
 108 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00020000; \
 109                         else    iop->pdat &= ~0x00020000
 110 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00010000; \
 111                         else    iop->pdat &= ~0x00010000
 112 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 113
 114 #else
 115
 116 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 117 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 118 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 119 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 120 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 121                         else    iop->pdat &= ~0x00010000
 122 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 123                         else    iop->pdat &= ~0x00020000
 124 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 125 #endif
 126
 127 #define CFG_I2C_EEPROM_ADDR     0x50
 128 #define CFG_I2C_EEPROM_ADDR_LEN 2
 129 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 130 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 131
 132 #define CONFIG_I2C_X
 133
 134 /*
 135  * select serial console configuration
 136  *
 137  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 138  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 139  * for SCC).
 140  *
 141  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 142  * defined elsewhere (for example, on the cogent platform, there are serial
 143  * ports on the motherboard which are used for the serial console - see
 144  * cogent/cma101/serial.[ch]).
 145  */
 146 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 147 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 148 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 149 #ifdef CONFIG_82xx_CONS_SMC1
 150 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 151 #endif
 152 #ifdef CONFIG_82xx_CONS_SMC2
 153 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 154 #endif
 155
 156 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 157 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 158 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 159
 160 /*
 161  * select ethernet configuration
 162  *
 163  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 164  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 165  * for FCC)
 166  *
 167  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 168  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 169  * from CONFIG_COMMANDS to remove support for networking.
 170  *
 171  * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 172  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 173  */
 174 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 175 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 176 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 177 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 178
 179 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 180
 181 /*
 182  *  - RX clk is CLK11
 183  *  - TX clk is CLK12
 184  */
 185 # define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 186
 187 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 188
 189 /*
 190  * - Rx-CLK is CLK13
 191  * - Tx-CLK is CLK14
 192  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 193  * - Enable Full Duplex in FSMR
 194  */
 195 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 196 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 197 # define CFG_CPMFCR_RAMTYPE     0
 198 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 199
 200 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 201
 202
 203 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 204 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
 205 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 206 #else   /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
 207 # ifndef CONFIG_300MHz
 208 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 209 # else
 210 #  define CONFIG_8260_CLKIN     83333000        /* in Hz */
 211 # endif
 212 #endif  /* CONFIG_MPC8255 */
 213
 214 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 215 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 216
 217 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 218
 219 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 220
 221 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
 222                                  CFG_CMD_I2C    | \
 223                                  CFG_CMD_EEPROM)
 224
 225 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 226 #include <cmd_confdefs.h>
 227
 228 /*
 229  * Miscellaneous configurable options
 230  */
 231 #define CFG_LONGHELP                    /* undef to save memory         */
 232 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 233 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 234 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 235 #else
 236 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 237 #endif
 238 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 239 #define CFG_MAXARGS     16              /* max number of command args   */
 240 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 241
 242 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 243 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 244
 245 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 246
 247 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 248
 249 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 250
 251 #define CFG_RESET_ADDRESS 0xFFFFFFFC    /* "bad" address                */
 252
 253 /*
 254  * For booting Linux, the board info and command line data
 255  * have to be in the first 8 MB of memory, since this is
 256  * the maximum mapped by the Linux kernel during initialization.
 257  */
 258 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 259
 260
 261 /* What should the base address of the main FLASH be and how big is
 262  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
 263  * The main FLASH is whichever is connected to *CS0.
 264  */
 265 #define CFG_FLASH0_BASE 0x40000000
 266 #define CFG_FLASH1_BASE 0x60000000
 267 #define CFG_FLASH0_SIZE 32
 268 #define CFG_FLASH1_SIZE 32
 269
 270 /* Flash bank size (for preliminary settings)
 271  */
 272 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 273
 274 /*-----------------------------------------------------------------------
 275  * FLASH organization
 276  */
 277 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 278 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 279
 280 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 281 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 282
 283 #if 0
 284 /* Start port with environment in flash; switch to EEPROM later */
 285 #define CFG_ENV_IS_IN_FLASH     1
 286 #define CFG_ENV_ADDR            (CFG_FLASH_BASE+0x40000)
 287 #define CFG_ENV_SIZE            0x40000
 288 #define CFG_ENV_SECT_SIZE       0x40000
 289 #else
 290 /* Final version: environment in EEPROM */
 291 #define CFG_ENV_IS_IN_EEPROM    1
 292 #define CFG_ENV_OFFSET          0
 293 #define CFG_ENV_SIZE            2048
 294 #endif
 295
 296 /*-----------------------------------------------------------------------
 297  * Hardware Information Block
 298  */
 299 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 300 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 301 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 302
 303 /*-----------------------------------------------------------------------
 304  * Hard Reset Configuration Words
 305  *
 306  * if you change bits in the HRCW, you must also change the CFG_*
 307  * defines for the various registers affected by the HRCW e.g. changing
 308  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 309  */
 310 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 311
 312 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
 313 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0111)
 314 #else   /* ! MPC8255 && !MPC8265 */
 315 # if defined(CONFIG_266MHz)
 316 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0111)
 317 # elif defined(CONFIG_300MHz)
 318 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0110)
 319 # else
 320 #  define CFG_HRCW_MASTER       (__HRCW__ALL__)
 321 # endif
 322 #endif  /* CONFIG_MPC8255 */
 323
 324 /* no slaves so just fill with zeros */
 325 #define CFG_HRCW_SLAVE1         0
 326 #define CFG_HRCW_SLAVE2         0
 327 #define CFG_HRCW_SLAVE3         0
 328 #define CFG_HRCW_SLAVE4         0
 329 #define CFG_HRCW_SLAVE5         0
 330 #define CFG_HRCW_SLAVE6         0
 331 #define CFG_HRCW_SLAVE7         0
 332
 333 /*-----------------------------------------------------------------------
 334  * Internal Memory Mapped Register
 335  */
 336 #define CFG_IMMR                0xFFF00000
 337
 338 /*-----------------------------------------------------------------------
 339  * Definitions for initial stack pointer and data area (in DPRAM)
 340  */
 341 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 342 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 343 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 344 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 345 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 346
 347 /*-----------------------------------------------------------------------
 348  * Start addresses for the final memory configuration
 349  * (Set up by the startup code)
 350  * Please note that CFG_SDRAM_BASE _must_ start at 0
 351  *
 352  * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 353  * is mapped at SDRAM_BASE2_PRELIM.
 354  */
 355 #define CFG_SDRAM_BASE          0x00000000
 356 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 357 #define CFG_MONITOR_BASE        TEXT_BASE
 358 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 359 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 360
 361 /*
 362  * Internal Definitions
 363  *
 364  * Boot Flags
 365  */
 366 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 367 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 368
 369
 370 /*-----------------------------------------------------------------------
 371  * Cache Configuration
 372  */
 373 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 374 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 375 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 376 #endif
 377
 378 /*-----------------------------------------------------------------------
 379  * HIDx - Hardware Implementation-dependent Registers                    2-11
 380  *-----------------------------------------------------------------------
 381  * HID0 also contains cache control - initially enable both caches and
 382  * invalidate contents, then the final state leaves only the instruction
 383  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 384  * but Soft reset does not.
 385  *
 386  * HID1 has only read-only information - nothing to set.
 387  */
 388 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 389                                 HID0_IFEM|HID0_ABE)
 390 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 391 #define CFG_HID2        0
 392
 393 /*-----------------------------------------------------------------------
 394  * RMR - Reset Mode Register                                     5-5
 395  *-----------------------------------------------------------------------
 396  * turn on Checkstop Reset Enable
 397  */
 398 #define CFG_RMR         RMR_CSRE
 399
 400 /*-----------------------------------------------------------------------
 401  * BCR - Bus Configuration                                       4-25
 402  *-----------------------------------------------------------------------
 403  */
 404 #ifdef  CONFIG_BUSMODE_60x
 405 #define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 406                          BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode  */
 407 #else
 408 #define BCR_APD01       0x10000000
 409 #define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 410 #endif
 411
 412 /*-----------------------------------------------------------------------
 413  * SIUMCR - SIU Module Configuration                             4-31
 414  *-----------------------------------------------------------------------
 415  */
 416 #if 0
 417 #define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 418 #else
 419 #define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 420 #endif
 421
 422
 423 /*-----------------------------------------------------------------------
 424  * SYPCR - System Protection Control                             4-35
 425  * SYPCR can only be written once after reset!
 426  *-----------------------------------------------------------------------
 427  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 428  */
 429 #if defined(CONFIG_WATCHDOG)
 430 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 431                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 432 #else
 433 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 434                          SYPCR_SWRI|SYPCR_SWP)
 435 #endif /* CONFIG_WATCHDOG */
 436
 437 /*-----------------------------------------------------------------------
 438  * TMCNTSC - Time Counter Status and Control                     4-40
 439  *-----------------------------------------------------------------------
 440  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 441  * and enable Time Counter
 442  */
 443 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 444
 445 /*-----------------------------------------------------------------------
 446  * PISCR - Periodic Interrupt Status and Control                 4-42
 447  *-----------------------------------------------------------------------
 448  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 449  * Periodic timer
 450  */
 451 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 452
 453 /*-----------------------------------------------------------------------
 454  * SCCR - System Clock Control                                   9-8
 455  *-----------------------------------------------------------------------
 456  * Ensure DFBRG is Divide by 16
 457  */
 458 #define CFG_SCCR        0
 459
 460 /*-----------------------------------------------------------------------
 461  * RCCR - RISC Controller Configuration                         13-7
 462  *-----------------------------------------------------------------------
 463  */
 464 #define CFG_RCCR        0
 465
 466 /*
 467  * Init Memory Controller:
 468  *
 469  * Bank Bus     Machine PortSz  Device
 470  * ---- ---     ------- ------  ------
 471  *  0   60x     GPCM    64 bit  FLASH
 472  *  1   60x     SDRAM   64 bit  SDRAM
 473  *  2   Local   SDRAM   32 bit  SDRAM
 474  *
 475  */
 476
 477         /* Initialize SDRAM on local bus
 478          */
 479 #define CFG_INIT_LOCAL_SDRAM
 480
 481 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 482
 483 /* Minimum mask to separate preliminary
 484  * address ranges for CS[0:2]
 485  */
 486 #define CFG_GLOBAL_SDRAM_LIMIT  (512<<20)       /* less than 512 MB */
 487 #define CFG_LOCAL_SDRAM_LIMIT   (128<<20)       /* less than 128 MB */
 488
 489 #define CFG_MPTPR       0x4000
 490
 491 /*-----------------------------------------------------------------------------
 492  * Address for Mode Register Set (MRS) command
 493  *-----------------------------------------------------------------------------
 494  * In fact, the address is rather configuration data presented to the SDRAM on
 495  * its address lines. Because the address lines may be mux'ed externally either
 496  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 497  * address:
 498  *
 499  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 500  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 501  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 502  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 503  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 504  *-----------------------------------------------------------------------------
 505  */
 506 #define CFG_MRS_OFFS    0x00000110
 507
 508
 509 /* Bank 0 - FLASH
 510  */
 511 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 512                          BRx_PS_64                      |\
 513                          BRx_MS_GPCM_P                  |\
 514                          BRx_V)
 515
 516 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 517                          ORxG_CSNT                      |\
 518                          ORxG_ACS_DIV1                  |\
 519                          ORxG_SCY_3_CLK                 |\
 520                          ORxG_EHTR                      |\
 521                          ORxG_TRLX)
 522
 523         /* SDRAM on TQM8260 can have either 8 or 9 columns.
 524          * The number affects configuration values.
 525          */
 526
 527 /* Bank 1 - 60x bus SDRAM
 528  */
 529 #define CFG_PSRT        0x20
 530 #define CFG_LSRT        0x20
 531 #ifndef CFG_RAMBOOT
 532 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 533                          BRx_PS_64                      |\
 534                          BRx_MS_SDRAM_P                 |\
 535                          BRx_V)
 536
 537 #define CFG_OR1_PRELIM  CFG_OR1_8COL
 538
 539
 540         /* SDRAM initialization values for 8-column chips
 541          */
 542 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 543                          ORxS_BPD_4                     |\
 544                          ORxS_ROWST_PBI1_A7             |\
 545                          ORxS_NUMR_12)
 546
 547 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 548                          PSDMR_SDAM_A15_IS_A5           |\
 549                          PSDMR_BSMA_A12_A14             |\
 550                          PSDMR_SDA10_PBI1_A8            |\
 551                          PSDMR_RFRC_7_CLK               |\
 552                          PSDMR_PRETOACT_2W              |\
 553                          PSDMR_ACTTORW_2W               |\
 554                          PSDMR_LDOTOPRE_1C              |\
 555                          PSDMR_WRC_2C                   |\
 556                          PSDMR_EAMUX                    |\
 557                          PSDMR_CL_2)
 558
 559         /* SDRAM initialization values for 9-column chips
 560          */
 561 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 562                          ORxS_BPD_4                     |\
 563                          ORxS_ROWST_PBI1_A5             |\
 564                          ORxS_NUMR_13)
 565
 566 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 567                          PSDMR_SDAM_A16_IS_A5           |\
 568                          PSDMR_BSMA_A12_A14             |\
 569                          PSDMR_SDA10_PBI1_A7            |\
 570                          PSDMR_RFRC_7_CLK               |\
 571                          PSDMR_PRETOACT_2W              |\
 572                          PSDMR_ACTTORW_2W               |\
 573                          PSDMR_LDOTOPRE_1C              |\
 574                          PSDMR_WRC_2C                   |\
 575                          PSDMR_EAMUX                    |\
 576                          PSDMR_CL_2)
 577
 578 /* Bank 2 - Local bus SDRAM
 579  */
 580 #ifdef CFG_INIT_LOCAL_SDRAM
 581 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 582                          BRx_PS_32                      |\
 583                          BRx_MS_SDRAM_L                 |\
 584                          BRx_V)
 585
 586 #define CFG_OR2_PRELIM  CFG_OR2_8COL
 587
 588 #define SDRAM_BASE2_PRELIM      0x80000000
 589
 590         /* SDRAM initialization values for 8-column chips
 591          */
 592 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 593                          ORxS_BPD_4                     |\
 594                          ORxS_ROWST_PBI1_A8             |\
 595                          ORxS_NUMR_12)
 596
 597 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
 598                          PSDMR_SDAM_A15_IS_A5           |\
 599                          PSDMR_BSMA_A13_A15             |\
 600                          PSDMR_SDA10_PBI1_A9            |\
 601                          PSDMR_RFRC_7_CLK               |\
 602                          PSDMR_PRETOACT_2W              |\
 603                          PSDMR_ACTTORW_2W               |\
 604                          PSDMR_BL                       |\
 605                          PSDMR_LDOTOPRE_1C              |\
 606                          PSDMR_WRC_2C                   |\
 607                          PSDMR_CL_2)
 608
 609         /* SDRAM initialization values for 9-column chips
 610          */
 611 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 612                          ORxS_BPD_4                     |\
 613                          ORxS_ROWST_PBI1_A6             |\
 614                          ORxS_NUMR_13)
 615
 616 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
 617                          PSDMR_SDAM_A16_IS_A5           |\
 618                          PSDMR_BSMA_A13_A15             |\
 619                          PSDMR_SDA10_PBI1_A8            |\
 620                          PSDMR_RFRC_7_CLK               |\
 621                          PSDMR_PRETOACT_2W              |\
 622                          PSDMR_ACTTORW_2W               |\
 623                          PSDMR_BL                       |\
 624                          PSDMR_LDOTOPRE_1C              |\
 625                          PSDMR_WRC_2C                   |\
 626                          PSDMR_CL_2)
 627
 628 #endif /* CFG_INIT_LOCAL_SDRAM */
 629
 630 #endif /* CFG_RAMBOOT */
 631
 632 #endif  /* __CONFIG_H */