include/configs/TQM8272.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37 #define CONFIG_MPC8272_FAMILY   1
  38 #define CONFIG_TQM8272          1
  39
  40 #define CONFIG_GET_CPU_STR_F    1       /* Get the CPU ID STR */
  41 #define CONFIG_BOARD_GET_CPU_CLK_F      1 /* Get the CLKIN from board fct */
  42
  43 #define STK82xx_150             1       /* on a STK82xx.150 */
  44
  45 #define CONFIG_CPM2             1       /* Has a CPM2 */
  46
  47 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1              */
  48
  49 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  50
  51 #define CONFIG_BOARD_EARLY_INIT_R       1
  52
  53 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  54 #define CONFIG_BAUDRATE         230400
  55 #else
  56 #define CONFIG_BAUDRATE         115200
  57 #endif
  58
  59 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  60
  61 #undef  CONFIG_BOOTARGS
  62
  63 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  64         "netdev=eth0\0"                                                 \
  65         "consdev=ttyCPM0\0"                                             \
  66         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  67                 "nfsroot=${serverip}:${rootpath}\0"                     \
  68         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  69         "hostname=tqm8272\0"                                            \
  70         "addip=setenv bootargs ${bootargs} "                            \
  71                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  72                 ":${hostname}:${netdev}:off panic=1\0"                  \
  73         "addcons=setenv bootargs ${bootargs} "                          \
  74                 "console=$(consdev),$(baudrate)\0"                      \
  75         "flash_nfs=run nfsargs addip addcons;"                          \
  76                 "bootm ${kernel_addr}\0"                                \
  77         "flash_self=run ramargs addip addcons;"                         \
  78                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  79         "net_nfs=tftp 300000 ${bootfile};"                              \
  80                 "run nfsargs addip addcons;bootm\0"                     \
  81         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  82         "bootfile=/tftpboot/tqm8272/uImage\0"                           \
  83         "kernel_addr=40080000\0"                                        \
  84         "ramdisk_addr=40100000\0"                                       \
  85         "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"               \
  86         "update=protect off 40000000 4003ffff;era 40000000 4003ffff;"   \
  87                 "cp.b 300000 40000000 40000;"                           \
  88                 "setenv filesize;saveenv\0"                             \
  89         "cphwib=cp.b 4003fc00 33fc00 400\0"                             \
  90         "upd=run load cphwib update\0"                                  \
  91         ""
  92 #define CONFIG_BOOTCOMMAND      "run flash_self"
  93
  94 #define CONFIG_I2C      1
  95
  96 #if CONFIG_I2C
  97 /* enable I2C and select the hardware/software driver */
  98 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  99 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 100 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 101 #define CFG_I2C_SLAVE           0x7F
 102
 103 /*
 104  * Software (bit-bang) I2C driver configuration
 105  */
 106 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 107 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 108 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 109 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 110 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 111                         else    iop->pdat &= ~0x00010000
 112 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 113                         else    iop->pdat &= ~0x00020000
 114 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 115
 116 #define CONFIG_I2C_X
 117
 118 /* EEPROM */
 119 #define CFG_I2C_EEPROM_ADDR_LEN 2
 120 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 121 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 122 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom */
 123
 124 /* I2C RTC */
 125 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 126 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 127
 128 /* I2C SYSMON (LM75) */
 129 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 130 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 131 #define CFG_DTT_MAX_TEMP        70
 132 #define CFG_DTT_LOW_TEMP        -30
 133 #define CFG_DTT_HYSTERESIS      3
 134
 135 #else
 136 #undef CONFIG_HARD_I2C
 137 #undef CONFIG_SOFT_I2C
 138 #endif
 139
 140 /*
 141  * select serial console configuration
 142  *
 143  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 144  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 145  * for SCC).
 146  *
 147  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 148  * defined elsewhere (for example, on the cogent platform, there are serial
 149  * ports on the motherboard which are used for the serial console - see
 150  * cogent/cma101/serial.[ch]).
 151  */
 152 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 153 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 154 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 155 #ifdef CONFIG_82xx_CONS_SMC1
 156 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 157 #endif
 158 #ifdef CONFIG_82xx_CONS_SMC2
 159 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 160 #endif
 161
 162 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 163 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 164 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 165
 166 /*
 167  * select ethernet configuration
 168  *
 169  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 170  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 171  * for FCC)
 172  *
 173  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 174  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 175  *
 176  * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 177  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 178  */
 179 #define CFG_FCC_ETHERNET
 180
 181 #if defined(CFG_FCC_ETHERNET)
 182 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 183 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 184 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 185 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 186 #else
 187 #define CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 188 #undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 189 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 190 #define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 191 #endif
 192
 193 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 194
 195 /*
 196  *  - RX clk is CLK11
 197  *  - TX clk is CLK12
 198  */
 199 # define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 200
 201 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 202
 203 /*
 204  * - Rx-CLK is CLK13
 205  * - Tx-CLK is CLK14
 206  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 207  * - Enable Full Duplex in FSMR
 208  */
 209 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 210 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 211 # define CFG_CPMFCR_RAMTYPE     0
 212 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 213
 214 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 215
 216 #define CONFIG_MII                      /* MII PHY management           */
 217 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 218 /*
 219  * GPIO pins used for bit-banged MII communications
 220  */
 221 #define MDIO_PORT       2               /* Port C */
 222
 223 #if STK82xx_150
 224 #define CFG_MDIO_PIN    0x00008000      /* PC16 */
 225 #define CFG_MDC_PIN     0x00004000      /* PC17 */
 226 #endif
 227
 228 #if STK82xx_100
 229 #define CFG_MDIO_PIN    0x00000002      /* PC30 */
 230 #define CFG_MDC_PIN     0x00000001      /* PC31 */
 231 #endif
 232
 233 #if 1
 234 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 235 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 236 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 237
 238 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 239                         else    iop->pdat &= ~CFG_MDIO_PIN
 240
 241 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 242                         else    iop->pdat &= ~CFG_MDC_PIN
 243 #else
 244 #define MDIO_ACTIVE     ({unsigned long tmp; tmp = iop->pdir; tmp |=  CFG_MDIO_PIN; iop->pdir = tmp;})
 245 #define MDIO_TRISTATE   ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
 246 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 247
 248 #define MDIO(bit)       if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDIO_PIN; iop->pdat = tmp;}\
 249                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
 250
 251 #define MDC(bit)        if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDC_PIN; iop->pdat = tmp;}\
 252                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
 253 #endif
 254
 255 #define MIIDELAY        udelay(1)
 256
 257
 258 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 259 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 260
 261 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 262 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 263
 264 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 265
 266 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 267
 268 /*
 269  * BOOTP options
 270  */
 271 #define CONFIG_BOOTP_SUBNETMASK
 272 #define CONFIG_BOOTP_GATEWAY
 273 #define CONFIG_BOOTP_HOSTNAME
 274 #define CONFIG_BOOTP_BOOTPATH
 275 #define CONFIG_BOOTP_BOOTFILESIZE
 276
 277
 278 /*
 279  * Command line configuration.
 280  */
 281 #include <config_cmd_default.h>
 282
 283 #define CONFIG_CMD_I2C
 284 #define CONFIG_CMD_DHCP
 285 #define CONFIG_CMD_MII
 286 #define CONFIG_CMD_NAND
 287 #define CONFIG_CMD_NFS
 288 #define CONFIG_CMD_PCI
 289 #define CONFIG_CMD_PING
 290 #define CONFIG_CMD_SNTP
 291
 292 #if CONFIG_I2C
 293     #define CONFIG_CMD_I2C
 294     #define CONFIG_CMD_DATE
 295     #define CONFIG_CMD_DTT
 296     #define CONFIG_CMD_EEPROM
 297 #endif
 298
 299
 300 /*
 301  * Miscellaneous configurable options
 302  */
 303 #define CFG_LONGHELP                    /* undef to save memory         */
 304 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 305
 306 #if 0
 307 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 308 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 309 #ifdef  CFG_HUSH_PARSER
 310 #define CFG_PROMPT_HUSH_PS2     "> "
 311 #endif
 312 #endif
 313
 314 #if defined(CONFIG_CMD_KGDB)
 315 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 316 #else
 317 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 318 #endif
 319 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 320 #define CFG_MAXARGS     16              /* max number of command args   */
 321 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 322
 323 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 324 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 325
 326 #define CFG_LOAD_ADDR   0x300000        /* default load address */
 327
 328 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 329
 330 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 331
 332 #define CFG_RESET_ADDRESS 0x40000104    /* "bad" address                */
 333
 334 /*
 335  * For booting Linux, the board info and command line data
 336  * have to be in the first 8 MB of memory, since this is
 337  * the maximum mapped by the Linux kernel during initialization.
 338  */
 339 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 340
 341 /*-----------------------------------------------------------------------
 342  * CAN stuff
 343  *-----------------------------------------------------------------------
 344  */
 345 #define CFG_CAN_BASE    0x51000000
 346 #define CFG_CAN_SIZE    1
 347 #define CFG_CAN_BR      ((CFG_CAN_BASE & BRx_BA_MSK)    |\
 348                          BRx_PS_8                       |\
 349                          BRx_MS_UPMC                    |\
 350                          BRx_V)
 351
 352 #define CFG_CAN_OR      (MEG_TO_AM(CFG_CAN_SIZE)        |\
 353                          ORxU_BI)
 354
 355
 356 /* What should the base address of the main FLASH be and how big is
 357  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
 358  * The main FLASH is whichever is connected to *CS0.
 359  */
 360 #define CFG_FLASH0_BASE 0x40000000
 361 #define CFG_FLASH0_SIZE 32      /* 32 MB */
 362
 363 /* Flash bank size (for preliminary settings)
 364  */
 365 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 366
 367 /*-----------------------------------------------------------------------
 368  * FLASH organization
 369  */
 370 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 371 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 372
 373 #define CFG_FLASH_CFI                           /* flash is CFI compat. */
 374 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
 375 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 376 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 377
 378 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 379 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 380
 381 #define CFG_UPDATE_FLASH_SIZE
 382
 383 #define CONFIG_ENV_IS_IN_FLASH  1
 384 #define CONFIG_ENV_ADDR         (CFG_FLASH_BASE + 0x40000)
 385 #define CONFIG_ENV_SIZE         0x20000
 386 #define CONFIG_ENV_SECT_SIZE    0x20000
 387 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 388 #define CONFIG_ENV_SIZE_REDUND  0x20000
 389
 390 /* Where is the Hardwareinformation Block (from Monitor Sources) */
 391 #define MON_RES_LENGTH          (0x0003FC00)
 392 #define HWIB_INFO_START_ADDR    (CFG_FLASH_BASE + MON_RES_LENGTH)
 393 #define HWIB_INFO_LEN           512
 394 #define CIB_INFO_START_ADDR     (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 395 #define CIB_INFO_LEN            512
 396
 397 #define CFG_HWINFO_OFFSET       0x3fc00 /* offset of HW Info block */
 398 #define CFG_HWINFO_SIZE         0x00000060      /* size   of HW Info block */
 399 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 400
 401 /*-----------------------------------------------------------------------
 402  * NAND-FLASH stuff
 403  *-----------------------------------------------------------------------
 404  */
 405 #if defined(CONFIG_CMD_NAND)
 406
 407 #define CFG_NAND_CS_DIST                0x80
 408 #define CFG_NAND_UPM_WRITE_CMD_OFS      0x20
 409 #define CFG_NAND_UPM_WRITE_ADDR_OFS     0x40
 410
 411 #define CFG_NAND_BR     ((CFG_NAND0_BASE & BRx_BA_MSK)  |\
 412                          BRx_PS_8                       |\
 413                          BRx_MS_UPMB                    |\
 414                          BRx_V)
 415
 416 #define CFG_NAND_OR     (MEG_TO_AM(CFG_NAND_SIZE)       |\
 417                          ORxU_BI                        |\
 418                          ORxU_EHTR_8IDLE)
 419
 420 #define CFG_NAND_SIZE   1
 421 #define CFG_NAND0_BASE 0x50000000
 422 #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
 423 #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
 424 #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
 425
 426 #define CFG_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 427 #define NAND_MAX_CHIPS 1
 428
 429 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
 430                              CFG_NAND1_BASE, \
 431                              CFG_NAND2_BASE, \
 432                              CFG_NAND3_BASE, \
 433                            }
 434
 435 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
 436 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
 437 #define WRITE_NAND_UPM(d, adr, off) do \
 438 { \
 439         volatile unsigned char *addr = (unsigned char *) (adr + off); \
 440         WRITE_NAND(d, addr); \
 441 } while(0)
 442
 443 #endif /* CONFIG_CMD_NAND */
 444
 445 #define CONFIG_PCI
 446 #ifdef CONFIG_PCI
 447 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 448 #define CONFIG_PCI_PNP
 449 #define CONFIG_EEPRO100
 450 #define CFG_RX_ETH_BUFFER       8               /* use 8 rx buffer on eepro100  */
 451 #define CONFIG_PCI_SCAN_SHOW
 452 #endif
 453
 454 /*-----------------------------------------------------------------------
 455  * Hard Reset Configuration Words
 456  *
 457  * if you change bits in the HRCW, you must also change the CFG_*
 458  * defines for the various registers affected by the HRCW e.g. changing
 459  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 460  */
 461 #if 0
 462 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 463
 464 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0111)
 465 #else
 466 #define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 467 #endif
 468
 469 /* no slaves so just fill with zeros */
 470 #define CFG_HRCW_SLAVE1         0
 471 #define CFG_HRCW_SLAVE2         0
 472 #define CFG_HRCW_SLAVE3         0
 473 #define CFG_HRCW_SLAVE4         0
 474 #define CFG_HRCW_SLAVE5         0
 475 #define CFG_HRCW_SLAVE6         0
 476 #define CFG_HRCW_SLAVE7         0
 477
 478 /*-----------------------------------------------------------------------
 479  * Internal Memory Mapped Register
 480  */
 481 #define CFG_IMMR                0xFFF00000
 482
 483 /*-----------------------------------------------------------------------
 484  * Definitions for initial stack pointer and data area (in DPRAM)
 485  */
 486 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 487 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 488 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 489 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 490 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 491
 492 /*-----------------------------------------------------------------------
 493  * Start addresses for the final memory configuration
 494  * (Set up by the startup code)
 495  * Please note that CFG_SDRAM_BASE _must_ start at 0
 496  */
 497 #define CFG_SDRAM_BASE          0x00000000
 498 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 499 #define CFG_MONITOR_BASE        TEXT_BASE
 500 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor */
 501 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 502
 503 /*
 504  * Internal Definitions
 505  *
 506  * Boot Flags
 507  */
 508 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 509 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 510
 511 /*-----------------------------------------------------------------------
 512  * Cache Configuration
 513  */
 514 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 515 #if defined(CONFIG_CMD_KGDB)
 516 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 517 #endif
 518
 519 /*-----------------------------------------------------------------------
 520  * HIDx - Hardware Implementation-dependent Registers                    2-11
 521  *-----------------------------------------------------------------------
 522  * HID0 also contains cache control - initially enable both caches and
 523  * invalidate contents, then the final state leaves only the instruction
 524  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 525  * but Soft reset does not.
 526  *
 527  * HID1 has only read-only information - nothing to set.
 528  */
 529 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 530                                 HID0_IFEM|HID0_ABE)
 531 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 532 #define CFG_HID2        0
 533
 534 /*-----------------------------------------------------------------------
 535  * RMR - Reset Mode Register                                     5-5
 536  *-----------------------------------------------------------------------
 537  * turn on Checkstop Reset Enable
 538  */
 539 #define CFG_RMR         RMR_CSRE
 540
 541 /*-----------------------------------------------------------------------
 542  * BCR - Bus Configuration                                       4-25
 543  *-----------------------------------------------------------------------
 544  */
 545 #define CFG_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)       /* 60x mode  */
 546 #define BCR_APD01       0x10000000
 547 #define CFG_BCR_SINGLE          (BCR_APD01|BCR_ETM)     /* 8260 mode */
 548
 549 /*-----------------------------------------------------------------------
 550  * SIUMCR - SIU Module Configuration                             4-31
 551  *-----------------------------------------------------------------------
 552  */
 553 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 554 #define CFG_SIUMCR_LOW          (SIUMCR_DPPC00)
 555 #define CFG_SIUMCR_HIGH         (SIUMCR_DPPC00 | SIUMCR_ABE)
 556 #else
 557 #define CFG_SIUMCR              (SIUMCR_DPPC00)
 558 #endif
 559
 560 /*-----------------------------------------------------------------------
 561  * SYPCR - System Protection Control                             4-35
 562  * SYPCR can only be written once after reset!
 563  *-----------------------------------------------------------------------
 564  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 565  */
 566 #if defined(CONFIG_WATCHDOG)
 567 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 568                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 569 #else
 570 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 571                          SYPCR_SWRI|SYPCR_SWP)
 572 #endif /* CONFIG_WATCHDOG */
 573
 574 /*-----------------------------------------------------------------------
 575  * TMCNTSC - Time Counter Status and Control                     4-40
 576  *-----------------------------------------------------------------------
 577  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 578  * and enable Time Counter
 579  */
 580 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 581
 582 /*-----------------------------------------------------------------------
 583  * PISCR - Periodic Interrupt Status and Control                 4-42
 584  *-----------------------------------------------------------------------
 585  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 586  * Periodic timer
 587  */
 588 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 589
 590 /*-----------------------------------------------------------------------
 591  * SCCR - System Clock Control                                   9-8
 592  *-----------------------------------------------------------------------
 593  * Ensure DFBRG is Divide by 16
 594  */
 595 #define CFG_SCCR        SCCR_DFBRG01
 596
 597 /*-----------------------------------------------------------------------
 598  * RCCR - RISC Controller Configuration                         13-7
 599  *-----------------------------------------------------------------------
 600  */
 601 #define CFG_RCCR        0
 602
 603 /*
 604  * Init Memory Controller:
 605  *
 606  * Bank Bus     Machine PortSz  Device
 607  * ---- ---     ------- ------  ------
 608  *  0   60x     GPCM    32 bit  FLASH
 609  *  1   60x     SDRAM   64 bit  SDRAM
 610  *  2   60x     UPMB     8 bit  NAND
 611  *  3   60x     UPMC     8 bit  CAN
 612  *
 613  */
 614
 615 /* Initialize SDRAM
 616          */
 617 #undef CFG_INIT_LOCAL_SDRAM             /* No SDRAM on Local Bus */
 618
 619 #define SDRAM_MAX_SIZE  0x20000000      /* max. 512 MB          */
 620
 621 /* Minimum mask to separate preliminary
 622  * address ranges for CS[0:2]
 623  */
 624 #define CFG_GLOBAL_SDRAM_LIMIT  (512<<20)       /* less than 512 MB */
 625
 626 #define CFG_MPTPR       0x4000
 627
 628 /*-----------------------------------------------------------------------------
 629  * Address for Mode Register Set (MRS) command
 630  *-----------------------------------------------------------------------------
 631  * In fact, the address is rather configuration data presented to the SDRAM on
 632  * its address lines. Because the address lines may be mux'ed externally either
 633  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 634  * address:
 635  *
 636  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 637  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 638  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 639  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 640  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 641  *-----------------------------------------------------------------------------
 642  */
 643 #define CFG_MRS_OFFS    0x00000110
 644
 645 /* Bank 0 - FLASH
 646  */
 647 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 648                          BRx_PS_32                      |\
 649                          BRx_MS_GPCM_P                  |\
 650                          BRx_V)
 651
 652 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 653                          ORxG_CSNT                      |\
 654                          ORxG_ACS_DIV4                  |\
 655                          ORxG_SCY_8_CLK                 |\
 656                          ORxG_TRLX)
 657
 658 /* SDRAM on TQM8272 can have either 8 or 9 columns.
 659  * The number affects configuration values.
 660  */
 661
 662 /* Bank 1 - 60x bus SDRAM
 663  */
 664 #define CFG_PSRT        0x20    /* Low Value */
 665 /* #define CFG_PSRT        0x10  Fast Value */
 666 #define CFG_LSRT        0x20    /* Local Bus */
 667 #ifndef CFG_RAMBOOT
 668 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 669                          BRx_PS_64                      |\
 670                          BRx_MS_SDRAM_P                 |\
 671                          BRx_V)
 672
 673 #define CFG_OR1_PRELIM  CFG_OR1_8COL
 674
 675 /* SDRAM initialization values for 8-column chips
 676  */
 677 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 678                          ORxS_BPD_4                     |\
 679                          ORxS_ROWST_PBI1_A7             |\
 680                          ORxS_NUMR_12)
 681
 682 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 683                          PSDMR_SDAM_A15_IS_A5           |\
 684                          PSDMR_BSMA_A12_A14             |\
 685                          PSDMR_SDA10_PBI1_A8            |\
 686                          PSDMR_RFRC_7_CLK               |\
 687                          PSDMR_PRETOACT_2W              |\
 688                          PSDMR_ACTTORW_2W               |\
 689                          PSDMR_LDOTOPRE_1C              |\
 690                          PSDMR_WRC_2C                   |\
 691                          PSDMR_EAMUX                    |\
 692                          PSDMR_BUFCMD                   |\
 693                          PSDMR_CL_2)
 694
 695
 696 /* SDRAM initialization values for 9-column chips
 697  */
 698 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 699                          ORxS_BPD_4                     |\
 700                          ORxS_ROWST_PBI1_A5             |\
 701                          ORxS_NUMR_13)
 702
 703 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 704                          PSDMR_SDAM_A16_IS_A5           |\
 705                          PSDMR_BSMA_A12_A14             |\
 706                          PSDMR_SDA10_PBI1_A7            |\
 707                          PSDMR_RFRC_7_CLK               |\
 708                          PSDMR_PRETOACT_2W              |\
 709                          PSDMR_ACTTORW_2W               |\
 710                          PSDMR_LDOTOPRE_1C              |\
 711                          PSDMR_WRC_2C                   |\
 712                          PSDMR_EAMUX                    |\
 713                          PSDMR_BUFCMD                   |\
 714                          PSDMR_CL_2)
 715
 716 #define CFG_OR1_10COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 717                          ORxS_BPD_4                     |\
 718                          ORxS_ROWST_PBI1_A4             |\
 719                          ORxS_NUMR_13)
 720
 721 #define CFG_PSDMR_10COL  (PSDMR_PBI                      |\
 722                          PSDMR_SDAM_A17_IS_A5           |\
 723                          PSDMR_BSMA_A12_A14             |\
 724                          PSDMR_SDA10_PBI1_A4            |\
 725                          PSDMR_RFRC_6_CLK               |\
 726                          PSDMR_PRETOACT_2W              |\
 727                          PSDMR_ACTTORW_2W               |\
 728                          PSDMR_LDOTOPRE_1C              |\
 729                          PSDMR_WRC_2C                   |\
 730                          PSDMR_EAMUX                    |\
 731                          PSDMR_BUFCMD                   |\
 732                          PSDMR_CL_2)
 733
 734 #define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
 735 #define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
 736 #define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
 737 #define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
 738 #define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
 739 #define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
 740
 741 #define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
 742 #define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
 743 #define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
 744 #define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
 745 #define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
 746 #define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
 747
 748 #define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
 749 #define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
 750 #define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
 751 #define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
 752 #define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
 753 #define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
 754
 755 #define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
 756 #define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
 757 #define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
 758 #define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
 759 #define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 760 #define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 761
 762 #endif /* CFG_RAMBOOT */
 763
 764 #endif  /* __CONFIG_H */