include/configs/TQM834x.h

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * TQM8349 board configuration file
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  */
  34 #define CONFIG_E300             1       /* E300 Family */
  35 #define CONFIG_MPC83XX          1       /* MPC83XX family */
  36 #define CONFIG_MPC834X          1       /* MPC834X specific */
  37 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  38 #define CONFIG_TQM834X          1       /* TQM834X board specific */
  39
  40 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
  41 #define CFG_IMMR                0xff400000
  42
  43 /* System clock. Primary input clock when in PCI host mode */
  44 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
  45
  46 /*
  47  * Local Bus LCRR
  48  *    LCRR:  DLL bypass, Clock divider is 8
  49  *
  50  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  51  *
  52  * External Local Bus rate is
  53  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  54  */
  55 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_8)
  56
  57 /* board pre init: do not call, nothing to do */
  58 #undef CONFIG_BOARD_EARLY_INIT_F
  59
  60 /* detect the number of flash banks */
  61 #define CONFIG_BOARD_EARLY_INIT_R
  62
  63 /*
  64  * DDR Setup
  65  */
  66 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
  67 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  68 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
  69 #define DDR_CASLAT_25                           /* CASLAT set to 2.5 */
  70 #undef CONFIG_DDR_ECC                           /* only for ECC DDR module */
  71 #undef CONFIG_SPD_EEPROM                        /* do not use SPD EEPROM for DDR setup */
  72
  73 #undef CFG_DRAM_TEST                            /* memory test, takes time */
  74 #define CFG_MEMTEST_START       0x00000000      /* memtest region */
  75 #define CFG_MEMTEST_END         0x00100000
  76
  77 /*
  78  * FLASH on the Local Bus
  79  */
  80 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
  81 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
  82 #undef CFG_FLASH_CHECKSUM
  83 #define CFG_FLASH_BASE          0x80000000      /* start of FLASH   */
  84 #define CFG_FLASH_SIZE          8               /* FLASH size in MB */
  85
  86 /* buffered writes in the AMD chip set is not supported yet */
  87 #undef CFG_FLASH_USE_BUFFER_WRITE
  88
  89 /*
  90  * FLASH bank number detection
  91  */
  92
  93 /*
  94  * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  95  * banks has to be determined at runtime and stored in a gloabl variable
  96  * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
  97  * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
  98  * should be made sufficiently large to accomodate the number of banks that
  99  * might actually be detected.  Since most (all?) Flash related functions use
 100  * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
 101  * defined as tqm834x_num_flash_banks.
 102  */
 103 #define CFG_MAX_FLASH_BANKS_DETECT      2
 104 #ifndef __ASSEMBLY__
 105 extern int tqm834x_num_flash_banks;
 106 #endif
 107 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
 108
 109 #define CFG_MAX_FLASH_SECT              512     /* max sectors per device */
 110
 111 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
 112 #define CFG_BR0_PRELIM          ((CFG_FLASH_BASE & BR_BA) | \
 113                                         BR_MS_GPCM | BR_PS_32 | BR_V)
 114
 115 /* FLASH timing (0x0000_0c54) */
 116 #define CFG_OR_TIMING_FLASH     (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
 117                                         OR_GPCM_SCY_5 | OR_GPCM_TRLX)
 118
 119 #define CFG_PRELIM_OR_AM        0xc0000000      /* OR addr mask: 1 GiB */
 120
 121 #define CFG_OR0_PRELIM          (CFG_PRELIM_OR_AM  | CFG_OR_TIMING_FLASH)
 122
 123 #define CFG_LBLAWAR0_PRELIM     0x8000001D      /* 1 GiB window size (2^(size + 1)) */
 124
 125 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* Window base at flash base */
 126
 127 /* disable remaining mappings */
 128 #define CFG_BR1_PRELIM          0x00000000
 129 #define CFG_OR1_PRELIM          0x00000000
 130 #define CFG_LBLAWBAR1_PRELIM    0x00000000
 131 #define CFG_LBLAWAR1_PRELIM     0x00000000
 132
 133 #define CFG_BR2_PRELIM          0x00000000
 134 #define CFG_OR2_PRELIM          0x00000000
 135 #define CFG_LBLAWBAR2_PRELIM    0x00000000
 136 #define CFG_LBLAWAR2_PRELIM     0x00000000
 137
 138 #define CFG_BR3_PRELIM          0x00000000
 139 #define CFG_OR3_PRELIM          0x00000000
 140 #define CFG_LBLAWBAR3_PRELIM    0x00000000
 141 #define CFG_LBLAWAR3_PRELIM     0x00000000
 142
 143 #define CFG_BR4_PRELIM          0x00000000
 144 #define CFG_OR4_PRELIM          0x00000000
 145 #define CFG_LBLAWBAR4_PRELIM    0x00000000
 146 #define CFG_LBLAWAR4_PRELIM     0x00000000
 147
 148 #define CFG_BR5_PRELIM          0x00000000
 149 #define CFG_OR5_PRELIM          0x00000000
 150 #define CFG_LBLAWBAR5_PRELIM    0x00000000
 151 #define CFG_LBLAWAR5_PRELIM     0x00000000
 152
 153 #define CFG_BR6_PRELIM          0x00000000
 154 #define CFG_OR6_PRELIM          0x00000000
 155 #define CFG_LBLAWBAR6_PRELIM    0x00000000
 156 #define CFG_LBLAWAR6_PRELIM     0x00000000
 157
 158 #define CFG_BR7_PRELIM          0x00000000
 159 #define CFG_OR7_PRELIM          0x00000000
 160 #define CFG_LBLAWBAR7_PRELIM    0x00000000
 161 #define CFG_LBLAWAR7_PRELIM     0x00000000
 162
 163 /*
 164  * Monitor config
 165  */
 166 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 167
 168 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 169 #define CFG_RAMBOOT
 170 #else
 171 #undef  CFG_RAMBOOT
 172 #endif
 173
 174 #define CONFIG_L1_INIT_RAM
 175 #define CFG_INIT_RAM_LOCK       1
 176 #define CFG_INIT_RAM_ADDR       0x20000000      /* Initial RAM address */
 177 #define CFG_INIT_RAM_END        0x1000          /* End of used area in RAM*/
 178
 179 #define CFG_GBL_DATA_SIZE       0x100           /* num bytes initial data */
 180 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 181 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 182
 183 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 184 #define CFG_MALLOC_LEN          (256 * 1024) /* Reserve 256 kB for malloc */
 185
 186 /*
 187  * Serial Port
 188  */
 189 #define CONFIG_CONS_INDEX       1
 190 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 191 #define CFG_NS16550
 192 #define CFG_NS16550_SERIAL
 193 #define CFG_NS16550_REG_SIZE    1
 194 #define CFG_NS16550_CLK         get_bus_freq(0)
 195
 196 #define CFG_BAUDRATE_TABLE  \
 197         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 198
 199 #define CFG_NS16550_COM1        (CFG_IMMR + 0x4500)
 200 #define CFG_NS16550_COM2        (CFG_IMMR + 0x4600)
 201
 202 /*
 203  * I2C
 204  */
 205 #define CONFIG_HARD_I2C                         /* I2C with hardware support    */
 206 #undef CONFIG_SOFT_I2C                          /* I2C bit-banged               */
 207 #define CONFIG_FSL_I2C
 208 #define CFG_I2C_SPEED                   400000  /* I2C speed: 400KHz            */
 209 #define CFG_I2C_SLAVE                   0x7F    /* slave address                */
 210 #define CFG_I2C_OFFSET                  0x3000
 211
 212 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
 213 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x                     */
 214 #define CFG_I2C_EEPROM_ADDR_LEN         2       /* 16 bit                       */
 215 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* 32 bytes per write           */
 216 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 217 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  12      /* 10ms +/- 20%                 */
 218 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom         */
 219
 220 /* I2C RTC */
 221 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c       */
 222 #define CFG_I2C_RTC_ADDR                0x68    /* at address 0x68              */
 223
 224 /* I2C SYSMON (LM75) */
 225 #define CONFIG_DTT_LM75                 1       /* ON Semi's LM75               */
 226 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses             */
 227 #define CFG_DTT_MAX_TEMP                70
 228 #define CFG_DTT_LOW_TEMP                -30
 229 #define CFG_DTT_HYSTERESIS              3
 230
 231 /*
 232  * TSEC
 233  */
 234 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 235 #define CONFIG_MII
 236
 237 #define CFG_TSEC1_OFFSET        0x24000
 238 #define CFG_TSEC1               (CFG_IMMR + CFG_TSEC1_OFFSET)
 239 #define CFG_TSEC2_OFFSET        0x25000
 240 #define CFG_TSEC2               (CFG_IMMR + CFG_TSEC2_OFFSET)
 241
 242 #if defined(CONFIG_TSEC_ENET)
 243
 244 #ifndef CONFIG_NET_MULTI
 245 #define CONFIG_NET_MULTI
 246 #endif
 247
 248 #define CONFIG_TSEC1            1
 249 #define CONFIG_TSEC1_NAME       "TSEC0"
 250 #define CONFIG_TSEC2            1
 251 #define CONFIG_TSEC2_NAME       "TSEC1"
 252 #define TSEC1_PHY_ADDR                  2
 253 #define TSEC2_PHY_ADDR                  1
 254 #define TSEC1_PHYIDX                    0
 255 #define TSEC2_PHYIDX                    0
 256 #define TSEC1_FLAGS             TSEC_GIGABIT
 257 #define TSEC2_FLAGS             TSEC_GIGABIT
 258
 259 /* Options are: TSEC[0-1] */
 260 #define CONFIG_ETHPRIME                 "TSEC0"
 261
 262 #endif  /* CONFIG_TSEC_ENET */
 263
 264 /*
 265  * General PCI
 266  * Addresses are mapped 1-1.
 267  */
 268 #define CONFIG_PCI
 269
 270 #if defined(CONFIG_PCI)
 271
 272 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 273 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 274
 275 /* PCI1 host bridge */
 276 #define CFG_PCI1_MEM_BASE       0xc0000000
 277 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 278 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 279 #define CFG_PCI1_IO_BASE        0xe2000000
 280 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 281 #define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
 282
 283 #undef CONFIG_EEPRO100
 284 #define CONFIG_EEPRO100
 285 #undef CONFIG_TULIP
 286
 287 #if !defined(CONFIG_PCI_PNP)
 288         #define PCI_ENET0_IOADDR        CFG_PCI1_IO_BASE
 289         #define PCI_ENET0_MEMADDR       CFG_PCI1_MEM_BASE
 290         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
 291 #endif
 292
 293 #define CFG_PCI_SUBSYS_VENDORID         0x1957  /* Freescale */
 294
 295 #endif  /* CONFIG_PCI */
 296
 297 /*
 298  * Environment
 299  */
 300 #define CONFIG_ENV_OVERWRITE
 301
 302 #ifndef CFG_RAMBOOT
 303         #define CONFIG_ENV_IS_IN_FLASH  1
 304         #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE + 0x40000)
 305         #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 306         #define CONFIG_ENV_SIZE         0x2000
 307 #else
 308         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 309         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 310         #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 311         #define CONFIG_ENV_SIZE         0x2000
 312 #endif
 313
 314 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 315 #define CFG_LOADS_BAUD_CHANGE           1       /* allow baudrate change */
 316
 317 /*
 318  * BOOTP options
 319  */
 320 #define CONFIG_BOOTP_BOOTFILESIZE
 321 #define CONFIG_BOOTP_BOOTPATH
 322 #define CONFIG_BOOTP_GATEWAY
 323 #define CONFIG_BOOTP_HOSTNAME
 324
 325
 326 /*
 327  * Command line configuration.
 328  */
 329 #include <config_cmd_default.h>
 330
 331 #define CONFIG_CMD_DATE
 332 #define CONFIG_CMD_DTT
 333 #define CONFIG_CMD_EEPROM
 334 #define CONFIG_CMD_I2C
 335 #define CONFIG_CMD_JFFS2
 336 #define CONFIG_CMD_MII
 337 #define CONFIG_CMD_PING
 338 #define CONFIG_CMD_DHCP
 339
 340 #if defined(CONFIG_PCI)
 341     #define CONFIG_CMD_PCI
 342 #endif
 343
 344 #if defined(CFG_RAMBOOT)
 345     #undef CONFIG_CMD_ENV
 346     #undef CONFIG_CMD_LOADS
 347 #endif
 348
 349 /*
 350  * Miscellaneous configurable options
 351  */
 352 #define CFG_LONGHELP                            /* undef to save memory */
 353 #define CFG_LOAD_ADDR           0x2000000       /* default load address */
 354 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 355
 356 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 357 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 358 #ifdef  CFG_HUSH_PARSER
 359 #define CFG_PROMPT_HUSH_PS2     "> "
 360 #endif
 361
 362 #if defined(CONFIG_CMD_KGDB)
 363         #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 364 #else
 365         #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 366 #endif
 367
 368 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 369 #define CFG_MAXARGS             16              /* max number of command args */
 370 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 371 #define CFG_HZ                  1000            /* decrementer freq: 1ms ticks */
 372
 373 #undef CONFIG_WATCHDOG                          /* watchdog disabled */
 374
 375 /*
 376  * For booting Linux, the board info and command line data
 377  * have to be in the first 8 MB of memory, since this is
 378  * the maximum mapped by the Linux kernel during initialization.
 379  */
 380 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 381
 382 #define CFG_HRCW_LOW (\
 383         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 384         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 385         HRCWL_CSB_TO_CLKIN_4X1 |\
 386         HRCWL_VCO_1X2 |\
 387         HRCWL_CORE_TO_CSB_2X1)
 388
 389 #if defined(PCI_64BIT)
 390 #define CFG_HRCW_HIGH (\
 391         HRCWH_PCI_HOST |\
 392         HRCWH_64_BIT_PCI |\
 393         HRCWH_PCI1_ARBITER_ENABLE |\
 394         HRCWH_PCI2_ARBITER_DISABLE |\
 395         HRCWH_CORE_ENABLE |\
 396         HRCWH_FROM_0X00000100 |\
 397         HRCWH_BOOTSEQ_DISABLE |\
 398         HRCWH_SW_WATCHDOG_DISABLE |\
 399         HRCWH_ROM_LOC_LOCAL_16BIT |\
 400         HRCWH_TSEC1M_IN_GMII |\
 401         HRCWH_TSEC2M_IN_GMII )
 402 #else
 403 #define CFG_HRCW_HIGH (\
 404         HRCWH_PCI_HOST |\
 405         HRCWH_32_BIT_PCI |\
 406         HRCWH_PCI1_ARBITER_ENABLE |\
 407         HRCWH_PCI2_ARBITER_DISABLE |\
 408         HRCWH_CORE_ENABLE |\
 409         HRCWH_FROM_0X00000100 |\
 410         HRCWH_BOOTSEQ_DISABLE |\
 411         HRCWH_SW_WATCHDOG_DISABLE |\
 412         HRCWH_ROM_LOC_LOCAL_16BIT |\
 413         HRCWH_TSEC1M_IN_GMII |\
 414         HRCWH_TSEC2M_IN_GMII )
 415 #endif
 416
 417 /* System IO Config */
 418 #define CFG_SICRH       SICRH_TSOBI1
 419 #define CFG_SICRL       SICRL_LDP_A
 420
 421 /* i-cache and d-cache disabled */
 422 #define CFG_HID0_INIT   0x000000000
 423 #define CFG_HID0_FINAL  CFG_HID0_INIT
 424 #define CFG_HID2        HID2_HBE
 425
 426 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 427
 428 /* DDR 0 - 512M */
 429 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 430 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 431 #define CFG_IBAT1L      (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 432 #define CFG_IBAT1U      (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 433
 434 /* stack in DCACHE @ 512M (no backing mem) */
 435 #define CFG_IBAT2L      (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 436 #define CFG_IBAT2U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 437
 438 /* PCI */
 439 #ifdef CONFIG_PCI
 440 #define CFG_IBAT3L      (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 441 #define CFG_IBAT3U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 442 #define CFG_IBAT4L      (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 443 #define CFG_IBAT4U      (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 444 #define CFG_IBAT5L      (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 445 #define CFG_IBAT5U      (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
 446 #else
 447 #define CFG_IBAT3L      (0)
 448 #define CFG_IBAT3U      (0)
 449 #define CFG_IBAT4L      (0)
 450 #define CFG_IBAT4U      (0)
 451 #define CFG_IBAT5L      (0)
 452 #define CFG_IBAT5U      (0)
 453 #endif
 454
 455 /* IMMRBAR */
 456 #define CFG_IBAT6L      (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 457 #define CFG_IBAT6U      (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
 458
 459 /* FLASH */
 460 #define CFG_IBAT7L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 461 #define CFG_IBAT7U      (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 462
 463 #define CFG_DBAT0L      CFG_IBAT0L
 464 #define CFG_DBAT0U      CFG_IBAT0U
 465 #define CFG_DBAT1L      CFG_IBAT1L
 466 #define CFG_DBAT1U      CFG_IBAT1U
 467 #define CFG_DBAT2L      CFG_IBAT2L
 468 #define CFG_DBAT2U      CFG_IBAT2U
 469 #define CFG_DBAT3L      CFG_IBAT3L
 470 #define CFG_DBAT3U      CFG_IBAT3U
 471 #define CFG_DBAT4L      CFG_IBAT4L
 472 #define CFG_DBAT4U      CFG_IBAT4U
 473 #define CFG_DBAT5L      CFG_IBAT5L
 474 #define CFG_DBAT5U      CFG_IBAT5U
 475 #define CFG_DBAT6L      CFG_IBAT6L
 476 #define CFG_DBAT6U      CFG_IBAT6U
 477 #define CFG_DBAT7L      CFG_IBAT7L
 478 #define CFG_DBAT7U      CFG_IBAT7U
 479
 480 /*
 481  * Internal Definitions
 482  *
 483  * Boot Flags
 484  */
 485 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 486 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 487
 488 #if defined(CONFIG_CMD_KGDB)
 489 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 490 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 491 #endif
 492
 493 /*
 494  * Environment Configuration
 495  */
 496
 497 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 498
 499 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 500 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 501
 502 #define CONFIG_BAUDRATE         115200
 503
 504 #define CONFIG_PREBOOT  "echo;" \
 505         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 506         "echo"
 507
 508 #undef  CONFIG_BOOTARGS
 509
 510 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 511         "netdev=eth0\0"                                                 \
 512         "hostname=tqm834x\0"                                            \
 513         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 514                 "nfsroot=${serverip}:${rootpath}\0"                     \
 515         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 516         "addip=setenv bootargs ${bootargs} "                            \
 517                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 518                 ":${hostname}:${netdev}:off panic=1\0"                  \
 519         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 520         "flash_nfs=run nfsargs addip addtty;"                           \
 521                 "bootm ${kernel_addr}\0"                                \
 522         "flash_self=run ramargs addip addtty;"                          \
 523                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 524         "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;"     \
 525                 "bootm\0"                                               \
 526         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 527         "bootfile=/tftpboot/tqm834x/uImage\0"                           \
 528         "kernel_addr=80060000\0"                                        \
 529         "ramdisk_addr=80160000\0"                                       \
 530         "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0"               \
 531         "update=protect off 80000000 8003ffff; "                        \
 532                 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0"   \
 533         "upd=run load update\0"                                         \
 534         ""
 535
 536 #define CONFIG_BOOTCOMMAND      "run flash_self"
 537
 538 /*
 539  * JFFS2 partitions
 540  */
 541 /* mtdparts command line support */
 542 #define CONFIG_JFFS2_CMDLINE
 543 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
 544
 545 /* default mtd partition table */
 546 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
 547                                                 "1m(kernel),2m(initrd),"\
 548                                                 "-(user);"\
 549
 550 #endif  /* __CONFIG_H */