include/configs/TQM850M.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  21 #define CONFIG_TQM850M          1       /* ...on a TQM8xxM module       */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  26 #define CONFIG_SYS_SMC_RXBUFLEN 128
  27 #define CONFIG_SYS_MAXIDLE      10
  28
  29 #define CONFIG_BOOTCOUNT_LIMIT
  30
  31
  32 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  33
  34 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  35
  36 #undef  CONFIG_BOOTARGS
  37
  38 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  39         "netdev=eth0\0"                                                 \
  40         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  41                 "nfsroot=${serverip}:${rootpath}\0"                     \
  42         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  43         "addip=setenv bootargs ${bootargs} "                            \
  44                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  45                 ":${hostname}:${netdev}:off panic=1\0"                  \
  46         "flash_nfs=run nfsargs addip;"                                  \
  47                 "bootm ${kernel_addr}\0"                                \
  48         "flash_self=run ramargs addip;"                                 \
  49                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  50         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  51         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  52         "hostname=TQM850M\0"                                            \
  53         "bootfile=TQM850M/uImage\0"                                     \
  54         "fdt_addr=40080000\0"                                           \
  55         "kernel_addr=400A0000\0"                                        \
  56         "ramdisk_addr=40280000\0"                                       \
  57         "u-boot=TQM850M/u-image.bin\0"                                  \
  58         "load=tftp 200000 ${u-boot}\0"                                  \
  59         "update=prot off 40000000 +${filesize};"                        \
  60                 "era 40000000 +${filesize};"                            \
  61                 "cp.b 200000 40000000 ${filesize};"                     \
  62                 "sete filesize;save\0"                                  \
  63         ""
  64 #define CONFIG_BOOTCOMMAND      "run flash_self"
  65
  66 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  67 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  68
  69 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  70
  71 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  72
  73 /*
  74  * BOOTP options
  75  */
  76 #define CONFIG_BOOTP_SUBNETMASK
  77 #define CONFIG_BOOTP_GATEWAY
  78 #define CONFIG_BOOTP_HOSTNAME
  79 #define CONFIG_BOOTP_BOOTPATH
  80 #define CONFIG_BOOTP_BOOTFILESIZE
  81
  82 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  83
  84 /*
  85  * Command line configuration.
  86  */
  87
  88 #define CONFIG_NETCONSOLE
  89
  90 /*
  91  * Miscellaneous configurable options
  92  */
  93 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  94
  95 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
  96
  97 #if defined(CONFIG_CMD_KGDB)
  98 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
  99 #else
 100 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 101 #endif
 102 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 103 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 104 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 105
 106 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 107 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 108
 109 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 110
 111 /*
 112  * Low Level Configuration Settings
 113  * (address mappings, register initial values, etc.)
 114  * You should know what you are doing if you make changes here.
 115  */
 116 /*-----------------------------------------------------------------------
 117  * Internal Memory Mapped Register
 118  */
 119 #define CONFIG_SYS_IMMR         0xFFF00000
 120
 121 /*-----------------------------------------------------------------------
 122  * Definitions for initial stack pointer and data area (in DPRAM)
 123  */
 124 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 125 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 126 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 127 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 128
 129 /*-----------------------------------------------------------------------
 130  * Start addresses for the final memory configuration
 131  * (Set up by the startup code)
 132  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 133  */
 134 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 135 #define CONFIG_SYS_FLASH_BASE           0x40000000
 136 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 138 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 139
 140 /*
 141  * For booting Linux, the board info and command line data
 142  * have to be in the first 8 MB of memory, since this is
 143  * the maximum mapped by the Linux kernel during initialization.
 144  */
 145 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 146
 147 /*-----------------------------------------------------------------------
 148  * FLASH organization
 149  */
 150
 151 /* use CFI flash driver */
 152 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 153 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 154 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 155 #define CONFIG_SYS_FLASH_EMPTY_INFO
 156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 157 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 158 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 159
 160 #define CONFIG_ENV_IS_IN_FLASH  1
 161 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 162 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 163 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector     */
 164
 165 /* Address and size of Redundant Environment Sector     */
 166 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 167 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 168
 169 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 170
 171 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 172
 173 /*-----------------------------------------------------------------------
 174  * Dynamic MTD partition support
 175  */
 176 #define CONFIG_CMD_MTDPARTS
 177 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 178 #define CONFIG_FLASH_CFI_MTD
 179 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 180
 181 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 182                                                 "128k(dtb),"            \
 183                                                 "1920k(kernel),"        \
 184                                                 "5632(rootfs),"         \
 185                                                 "4m(data)"
 186
 187 /*-----------------------------------------------------------------------
 188  * Hardware Information Block
 189  */
 190 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 191 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 192 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 193
 194 /*-----------------------------------------------------------------------
 195  * Cache Configuration
 196  */
 197 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 198 #if defined(CONFIG_CMD_KGDB)
 199 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 200 #endif
 201
 202 /*-----------------------------------------------------------------------
 203  * SYPCR - System Protection Control                            11-9
 204  * SYPCR can only be written once after reset!
 205  *-----------------------------------------------------------------------
 206  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 207  */
 208 #if defined(CONFIG_WATCHDOG)
 209 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 210                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 211 #else
 212 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 213 #endif
 214
 215 /*-----------------------------------------------------------------------
 216  * SIUMCR - SIU Module Configuration                            11-6
 217  *-----------------------------------------------------------------------
 218  * PCMCIA config., multi-function pin tri-state
 219  */
 220 #ifndef CONFIG_CAN_DRIVER
 221 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 222 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 223 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 224 #endif  /* CONFIG_CAN_DRIVER */
 225
 226 /*-----------------------------------------------------------------------
 227  * TBSCR - Time Base Status and Control                         11-26
 228  *-----------------------------------------------------------------------
 229  * Clear Reference Interrupt Status, Timebase freezing enabled
 230  */
 231 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 232
 233 /*-----------------------------------------------------------------------
 234  * RTCSC - Real-Time Clock Status and Control Register          11-27
 235  *-----------------------------------------------------------------------
 236  */
 237 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 238
 239 /*-----------------------------------------------------------------------
 240  * PISCR - Periodic Interrupt Status and Control                11-31
 241  *-----------------------------------------------------------------------
 242  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 243  */
 244 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 245
 246 /*-----------------------------------------------------------------------
 247  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 248  *-----------------------------------------------------------------------
 249  * Reset PLL lock status sticky bit, timer expired status bit and timer
 250  * interrupt status bit
 251  */
 252 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 253
 254 /*-----------------------------------------------------------------------
 255  * SCCR - System Clock and reset Control Register               15-27
 256  *-----------------------------------------------------------------------
 257  * Set clock output, timebase and RTC source and divider,
 258  * power management and some other internal clocks
 259  */
 260 #define SCCR_MASK       SCCR_EBDF11
 261 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 262                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 263                          SCCR_DFALCD00)
 264
 265 /*-----------------------------------------------------------------------
 266  * PCMCIA stuff
 267  *-----------------------------------------------------------------------
 268  *
 269  */
 270 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 271 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 272 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 273 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 274 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 275 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 276 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 277 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 278
 279 /*-----------------------------------------------------------------------
 280  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 281  *-----------------------------------------------------------------------
 282  */
 283
 284 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 285 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 286
 287 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 288 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 289 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 290
 291 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 292 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 293
 294 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 295
 296 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 297
 298 /* Offset for data I/O                  */
 299 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 300
 301 /* Offset for normal register accesses  */
 302 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 303
 304 /* Offset for alternate registers       */
 305 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 306
 307 /*-----------------------------------------------------------------------
 308  *
 309  *-----------------------------------------------------------------------
 310  *
 311  */
 312 #define CONFIG_SYS_DER  0
 313
 314 /*
 315  * Init Memory Controller:
 316  *
 317  * BR0/1 and OR0/1 (FLASH)
 318  */
 319
 320 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 321 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 322
 323 /* used to re-map FLASH both when starting from SRAM or FLASH:
 324  * restrict access enough to keep SRAM working (if any)
 325  * but not too much to meddle with FLASH accesses
 326  */
 327 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 328 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 329
 330 /*
 331  * FLASH timing:
 332  */
 333 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 334                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 335
 336 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 337 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 338 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 339
 340 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 341 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 342 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 343
 344 /*
 345  * BR2/3 and OR2/3 (SDRAM)
 346  *
 347  */
 348 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 349 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 350 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 351
 352 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 353 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 354
 355 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 356 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 357
 358 #ifndef CONFIG_CAN_DRIVER
 359 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 360 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 361 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 362 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 363 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 364 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 365 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 366                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 367 #endif  /* CONFIG_CAN_DRIVER */
 368
 369 /*
 370  * Memory Periodic Timer Prescaler
 371  *
 372  * The Divider for PTA (refresh timer) configuration is based on an
 373  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 374  * the number of chip selects (NCS) and the actually needed refresh
 375  * rate is done by setting MPTPR.
 376  *
 377  * PTA is calculated from
 378  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 379  *
 380  *      gclk      CPU clock (not bus clock!)
 381  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 382  *
 383  * 4096  Rows from SDRAM example configuration
 384  * 1000  factor s -> ms
 385  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 386  *    4  Number of refresh cycles per period
 387  *   64  Refresh cycle in ms per number of rows
 388  * --------------------------------------------
 389  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 390  *
 391  * 50 MHz => 50.000.000 / Divider =  98
 392  * 66 Mhz => 66.000.000 / Divider = 129
 393  * 80 Mhz => 80.000.000 / Divider = 156
 394  */
 395
 396 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 397 #define CONFIG_SYS_MAMR_PTA     98
 398
 399 /*
 400  * For 16 MBit, refresh rates could be 31.3 us
 401  * (= 64 ms / 2K = 125 / quad bursts).
 402  * For a simpler initialization, 15.6 us is used instead.
 403  *
 404  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 405  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 406  */
 407 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 408 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 409
 410 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 411 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 412 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 413
 414 /*
 415  * MAMR settings for SDRAM
 416  */
 417
 418 /* 8 column SDRAM */
 419 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 420                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 421                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 422 /* 9 column SDRAM */
 423 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 424                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 425                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 426
 427 #define CONFIG_HWCONFIG         1
 428
 429 #endif  /* __CONFIG_H */