include/configs/TQM850M.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  37 #define CONFIG_TQM850M          1       /* ...on a TQM8xxM module       */
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #undef  CONFIG_8xx_CONS_NONE
  42 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  43
  44 #define CONFIG_BOOTCOUNT_LIMIT
  45
  46 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  47
  48 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  49
  50 #undef  CONFIG_BOOTARGS
  51
  52 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  53         "netdev=eth0\0"                                                 \
  54         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  55                 "nfsroot=${serverip}:${rootpath}\0"                     \
  56         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  57         "addip=setenv bootargs ${bootargs} "                            \
  58                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  59                 ":${hostname}:${netdev}:off panic=1\0"                  \
  60         "flash_nfs=run nfsargs addip;"                                  \
  61                 "bootm ${kernel_addr}\0"                                \
  62         "flash_self=run ramargs addip;"                                 \
  63                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  64         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  65         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  66         "hostname=TQM850M\0"                                            \
  67         "bootfile=TQM850M/uImage\0"                                     \
  68         "fdt_addr=40080000\0"                                           \
  69         "kernel_addr=400A0000\0"                                        \
  70         "ramdisk_addr=40280000\0"                                       \
  71         "u-boot=TQM850M/u-image.bin\0"                                  \
  72         "load=tftp 200000 ${u-boot}\0"                                  \
  73         "update=prot off 40000000 +${filesize};"                        \
  74                 "era 40000000 +${filesize};"                            \
  75                 "cp.b 200000 40000000 ${filesize};"                     \
  76                 "sete filesize;save\0"                                  \
  77         ""
  78 #define CONFIG_BOOTCOMMAND      "run flash_self"
  79
  80 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  81 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  82
  83 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  84
  85 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  86
  87 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  88
  89 /*
  90  * BOOTP options
  91  */
  92 #define CONFIG_BOOTP_SUBNETMASK
  93 #define CONFIG_BOOTP_GATEWAY
  94 #define CONFIG_BOOTP_HOSTNAME
  95 #define CONFIG_BOOTP_BOOTPATH
  96 #define CONFIG_BOOTP_BOOTFILESIZE
  97
  98
  99 #define CONFIG_MAC_PARTITION
 100 #define CONFIG_DOS_PARTITION
 101
 102 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 103
 104 /*
 105  * Command line configuration.
 106  */
 107 #include <config_cmd_default.h>
 108
 109 #define CONFIG_CMD_ASKENV
 110 #define CONFIG_CMD_DATE
 111 #define CONFIG_CMD_DHCP
 112 #define CONFIG_CMD_ELF
 113 #define CONFIG_CMD_EXT2
 114 #define CONFIG_CMD_IDE
 115 #define CONFIG_CMD_JFFS2
 116 #define CONFIG_CMD_NFS
 117 #define CONFIG_CMD_SNTP
 118
 119
 120 #define CONFIG_NETCONSOLE
 121
 122
 123 /*
 124  * Miscellaneous configurable options
 125  */
 126 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 127 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 128
 129 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 130 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 131 #ifdef  CONFIG_SYS_HUSH_PARSER
 132 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 133 #endif
 134
 135 #if defined(CONFIG_CMD_KGDB)
 136 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 137 #else
 138 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 139 #endif
 140 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 141 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 142 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 143
 144 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 145 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 146
 147 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 148
 149 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 150
 151 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 152
 153 /*
 154  * Low Level Configuration Settings
 155  * (address mappings, register initial values, etc.)
 156  * You should know what you are doing if you make changes here.
 157  */
 158 /*-----------------------------------------------------------------------
 159  * Internal Memory Mapped Register
 160  */
 161 #define CONFIG_SYS_IMMR         0xFFF00000
 162
 163 /*-----------------------------------------------------------------------
 164  * Definitions for initial stack pointer and data area (in DPRAM)
 165  */
 166 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 167 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 168 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 170 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 171
 172 /*-----------------------------------------------------------------------
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 178 #define CONFIG_SYS_FLASH_BASE           0x40000000
 179 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 181 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 182
 183 /*
 184  * For booting Linux, the board info and command line data
 185  * have to be in the first 8 MB of memory, since this is
 186  * the maximum mapped by the Linux kernel during initialization.
 187  */
 188 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 189
 190 /*-----------------------------------------------------------------------
 191  * FLASH organization
 192  */
 193
 194 /* use CFI flash driver */
 195 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 196 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 197 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 198 #define CONFIG_SYS_FLASH_EMPTY_INFO
 199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 202
 203 #define CONFIG_ENV_IS_IN_FLASH  1
 204 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 205 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 206 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector     */
 207
 208 /* Address and size of Redundant Environment Sector     */
 209 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 210 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 211
 212 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 213
 214 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 215
 216 /*-----------------------------------------------------------------------
 217  * Dynamic MTD partition support
 218  */
 219 #define CONFIG_JFFS2_CMDLINE
 220 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 221
 222 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 223                                                 "128k(dtb),"            \
 224                                                 "1920k(kernel),"        \
 225                                                 "5632(rootfs),"         \
 226                                                 "4m(data)"
 227
 228 /*-----------------------------------------------------------------------
 229  * Hardware Information Block
 230  */
 231 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 232 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 233 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 234
 235 /*-----------------------------------------------------------------------
 236  * Cache Configuration
 237  */
 238 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 239 #if defined(CONFIG_CMD_KGDB)
 240 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 241 #endif
 242
 243 /*-----------------------------------------------------------------------
 244  * SYPCR - System Protection Control                            11-9
 245  * SYPCR can only be written once after reset!
 246  *-----------------------------------------------------------------------
 247  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 248  */
 249 #if defined(CONFIG_WATCHDOG)
 250 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 251                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 252 #else
 253 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 254 #endif
 255
 256 /*-----------------------------------------------------------------------
 257  * SIUMCR - SIU Module Configuration                            11-6
 258  *-----------------------------------------------------------------------
 259  * PCMCIA config., multi-function pin tri-state
 260  */
 261 #ifndef CONFIG_CAN_DRIVER
 262 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 263 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 264 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 265 #endif  /* CONFIG_CAN_DRIVER */
 266
 267 /*-----------------------------------------------------------------------
 268  * TBSCR - Time Base Status and Control                         11-26
 269  *-----------------------------------------------------------------------
 270  * Clear Reference Interrupt Status, Timebase freezing enabled
 271  */
 272 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 273
 274 /*-----------------------------------------------------------------------
 275  * RTCSC - Real-Time Clock Status and Control Register          11-27
 276  *-----------------------------------------------------------------------
 277  */
 278 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 279
 280 /*-----------------------------------------------------------------------
 281  * PISCR - Periodic Interrupt Status and Control                11-31
 282  *-----------------------------------------------------------------------
 283  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 284  */
 285 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 286
 287 /*-----------------------------------------------------------------------
 288  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 289  *-----------------------------------------------------------------------
 290  * Reset PLL lock status sticky bit, timer expired status bit and timer
 291  * interrupt status bit
 292  */
 293 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 294
 295 /*-----------------------------------------------------------------------
 296  * SCCR - System Clock and reset Control Register               15-27
 297  *-----------------------------------------------------------------------
 298  * Set clock output, timebase and RTC source and divider,
 299  * power management and some other internal clocks
 300  */
 301 #define SCCR_MASK       SCCR_EBDF11
 302 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 303                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 304                          SCCR_DFALCD00)
 305
 306 /*-----------------------------------------------------------------------
 307  * PCMCIA stuff
 308  *-----------------------------------------------------------------------
 309  *
 310  */
 311 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 312 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 313 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 314 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 315 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 316 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 317 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 318 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 319
 320 /*-----------------------------------------------------------------------
 321  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 322  *-----------------------------------------------------------------------
 323  */
 324
 325 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 326
 327 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 328 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 329 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 330
 331 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 332 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 333
 334 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 335
 336 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 337
 338 /* Offset for data I/O                  */
 339 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 340
 341 /* Offset for normal register accesses  */
 342 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 343
 344 /* Offset for alternate registers       */
 345 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 346
 347 /*-----------------------------------------------------------------------
 348  *
 349  *-----------------------------------------------------------------------
 350  *
 351  */
 352 #define CONFIG_SYS_DER  0
 353
 354 /*
 355  * Init Memory Controller:
 356  *
 357  * BR0/1 and OR0/1 (FLASH)
 358  */
 359
 360 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 361 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 362
 363 /* used to re-map FLASH both when starting from SRAM or FLASH:
 364  * restrict access enough to keep SRAM working (if any)
 365  * but not too much to meddle with FLASH accesses
 366  */
 367 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 368 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 369
 370 /*
 371  * FLASH timing:
 372  */
 373 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 374                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 375
 376 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 377 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 378 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 379
 380 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 381 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 382 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 383
 384 /*
 385  * BR2/3 and OR2/3 (SDRAM)
 386  *
 387  */
 388 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 389 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 390 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 391
 392 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 393 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 394
 395 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 396 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 397
 398 #ifndef CONFIG_CAN_DRIVER
 399 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 400 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 401 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 402 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 403 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 404 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 405 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 406                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 407 #endif  /* CONFIG_CAN_DRIVER */
 408
 409 /*
 410  * Memory Periodic Timer Prescaler
 411  *
 412  * The Divider for PTA (refresh timer) configuration is based on an
 413  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 414  * the number of chip selects (NCS) and the actually needed refresh
 415  * rate is done by setting MPTPR.
 416  *
 417  * PTA is calculated from
 418  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 419  *
 420  *      gclk      CPU clock (not bus clock!)
 421  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 422  *
 423  * 4096  Rows from SDRAM example configuration
 424  * 1000  factor s -> ms
 425  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 426  *    4  Number of refresh cycles per period
 427  *   64  Refresh cycle in ms per number of rows
 428  * --------------------------------------------
 429  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 430  *
 431  * 50 MHz => 50.000.000 / Divider =  98
 432  * 66 Mhz => 66.000.000 / Divider = 129
 433  * 80 Mhz => 80.000.000 / Divider = 156
 434  */
 435
 436 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 437 #define CONFIG_SYS_MAMR_PTA     98
 438
 439 /*
 440  * For 16 MBit, refresh rates could be 31.3 us
 441  * (= 64 ms / 2K = 125 / quad bursts).
 442  * For a simpler initialization, 15.6 us is used instead.
 443  *
 444  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 445  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 446  */
 447 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 448 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 449
 450 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 451 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 452 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 453
 454 /*
 455  * MAMR settings for SDRAM
 456  */
 457
 458 /* 8 column SDRAM */
 459 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 460                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 461                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 462 /* 9 column SDRAM */
 463 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 464                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 465                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 466
 467
 468 /*
 469  * Internal Definitions
 470  *
 471  * Boot Flags
 472  */
 473 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 474 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 475
 476 #endif  /* __CONFIG_H */