include/configs/TQM855L.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  21 #define CONFIG_TQM855L          1       /* ...on a TQM8xxL module       */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  26 #define CONFIG_SYS_SMC_RXBUFLEN 128
  27 #define CONFIG_SYS_MAXIDLE      10
  28
  29 #define CONFIG_BOOTCOUNT_LIMIT
  30
  31
  32 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  33
  34 #define CONFIG_PREBOOT  "echo;" \
  35         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  36         "echo"
  37
  38 #undef  CONFIG_BOOTARGS
  39
  40 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  41         "netdev=eth0\0"                                                 \
  42         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  43                 "nfsroot=${serverip}:${rootpath}\0"                     \
  44         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  45         "addip=setenv bootargs ${bootargs} "                            \
  46                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  47                 ":${hostname}:${netdev}:off panic=1\0"                  \
  48         "flash_nfs=run nfsargs addip;"                                  \
  49                 "bootm ${kernel_addr}\0"                                \
  50         "flash_self=run ramargs addip;"                                 \
  51                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  52         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  53         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  54         "hostname=TQM855L\0"                                            \
  55         "bootfile=TQM855L/uImage\0"                                     \
  56         "fdt_addr=40040000\0"                                           \
  57         "kernel_addr=40060000\0"                                        \
  58         "ramdisk_addr=40200000\0"                                       \
  59         "u-boot=TQM855L/u-image.bin\0"                                  \
  60         "load=tftp 200000 ${u-boot}\0"                                  \
  61         "update=prot off 40000000 +${filesize};"                        \
  62                 "era 40000000 +${filesize};"                            \
  63                 "cp.b 200000 40000000 ${filesize};"                     \
  64                 "sete filesize;save\0"                                  \
  65         ""
  66 #define CONFIG_BOOTCOMMAND      "run flash_self"
  67
  68 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  69 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  70
  71 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  72
  73 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  74
  75 /*
  76  * BOOTP options
  77  */
  78 #define CONFIG_BOOTP_SUBNETMASK
  79 #define CONFIG_BOOTP_GATEWAY
  80 #define CONFIG_BOOTP_HOSTNAME
  81 #define CONFIG_BOOTP_BOOTPATH
  82 #define CONFIG_BOOTP_BOOTFILESIZE
  83
  84 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  85
  86 /*
  87  * Command line configuration.
  88  */
  89 #define CONFIG_CMD_IDE
  90 #define CONFIG_CMD_JFFS2
  91
  92 #define CONFIG_NETCONSOLE
  93
  94 /*
  95  * Miscellaneous configurable options
  96  */
  97 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  98
  99 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 100
 101 #if defined(CONFIG_CMD_KGDB)
 102 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 103 #else
 104 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 105 #endif
 106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 107 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 108 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 109
 110 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 111 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 112
 113 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 114
 115 /*
 116  * Low Level Configuration Settings
 117  * (address mappings, register initial values, etc.)
 118  * You should know what you are doing if you make changes here.
 119  */
 120 /*-----------------------------------------------------------------------
 121  * Internal Memory Mapped Register
 122  */
 123 #define CONFIG_SYS_IMMR         0xFFF00000
 124
 125 /*-----------------------------------------------------------------------
 126  * Definitions for initial stack pointer and data area (in DPRAM)
 127  */
 128 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 129 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 130 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 131 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 132
 133 /*-----------------------------------------------------------------------
 134  * Start addresses for the final memory configuration
 135  * (Set up by the startup code)
 136  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 137  */
 138 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 139 #define CONFIG_SYS_FLASH_BASE           0x40000000
 140 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 142 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 143
 144 /*
 145  * For booting Linux, the board info and command line data
 146  * have to be in the first 8 MB of memory, since this is
 147  * the maximum mapped by the Linux kernel during initialization.
 148  */
 149 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 150
 151 /*-----------------------------------------------------------------------
 152  * FLASH organization
 153  */
 154
 155 /* use CFI flash driver */
 156 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 157 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 158 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 159 #define CONFIG_SYS_FLASH_EMPTY_INFO
 160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks */
 162 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 163
 164 #define CONFIG_ENV_IS_IN_FLASH  1
 165 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 166 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 167
 168 /* Address and size of Redundant Environment Sector     */
 169 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 170 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 171
 172 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 173
 174 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 175
 176 /*-----------------------------------------------------------------------
 177  * Dynamic MTD partition support
 178  */
 179 #define CONFIG_CMD_MTDPARTS
 180 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 181 #define CONFIG_FLASH_CFI_MTD
 182 #define MTDIDS_DEFAULT          "nor0=TQM8xxL-0"
 183
 184 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxL-0:256k(u-boot),"      \
 185                                                 "128k(dtb),"            \
 186                                                 "1664k(kernel),"        \
 187                                                 "2m(rootfs),"           \
 188                                                 "4m(data)"
 189
 190 /*-----------------------------------------------------------------------
 191  * Hardware Information Block
 192  */
 193 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 194 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 195 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 196
 197 /*-----------------------------------------------------------------------
 198  * Cache Configuration
 199  */
 200 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 201 #if defined(CONFIG_CMD_KGDB)
 202 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 203 #endif
 204
 205 /*-----------------------------------------------------------------------
 206  * SYPCR - System Protection Control                            11-9
 207  * SYPCR can only be written once after reset!
 208  *-----------------------------------------------------------------------
 209  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 210  */
 211 #if defined(CONFIG_WATCHDOG)
 212 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 213                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 214 #else
 215 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 216 #endif
 217
 218 /*-----------------------------------------------------------------------
 219  * SIUMCR - SIU Module Configuration                            11-6
 220  *-----------------------------------------------------------------------
 221  * PCMCIA config., multi-function pin tri-state
 222  */
 223 #ifndef CONFIG_CAN_DRIVER
 224 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 225 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 226 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 227 #endif  /* CONFIG_CAN_DRIVER */
 228
 229 /*-----------------------------------------------------------------------
 230  * TBSCR - Time Base Status and Control                         11-26
 231  *-----------------------------------------------------------------------
 232  * Clear Reference Interrupt Status, Timebase freezing enabled
 233  */
 234 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 235
 236 /*-----------------------------------------------------------------------
 237  * RTCSC - Real-Time Clock Status and Control Register          11-27
 238  *-----------------------------------------------------------------------
 239  */
 240 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 241
 242 /*-----------------------------------------------------------------------
 243  * PISCR - Periodic Interrupt Status and Control                11-31
 244  *-----------------------------------------------------------------------
 245  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 246  */
 247 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 248
 249 /*-----------------------------------------------------------------------
 250  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 251  *-----------------------------------------------------------------------
 252  * Reset PLL lock status sticky bit, timer expired status bit and timer
 253  * interrupt status bit
 254  */
 255 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 256
 257 /*-----------------------------------------------------------------------
 258  * SCCR - System Clock and reset Control Register               15-27
 259  *-----------------------------------------------------------------------
 260  * Set clock output, timebase and RTC source and divider,
 261  * power management and some other internal clocks
 262  */
 263 #define SCCR_MASK       SCCR_EBDF11
 264 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 265                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 266                          SCCR_DFALCD00)
 267
 268 /*-----------------------------------------------------------------------
 269  * PCMCIA stuff
 270  *-----------------------------------------------------------------------
 271  *
 272  */
 273 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 274 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 275 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 276 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 277 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 278 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 279 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 280 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 281
 282 /*-----------------------------------------------------------------------
 283  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 284  *-----------------------------------------------------------------------
 285  */
 286
 287 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 288 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 289
 290 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 291 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 292 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 293
 294 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 295 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 296
 297 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 298
 299 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 300
 301 /* Offset for data I/O                  */
 302 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 303
 304 /* Offset for normal register accesses  */
 305 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 306
 307 /* Offset for alternate registers       */
 308 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 309
 310 /*-----------------------------------------------------------------------
 311  *
 312  *-----------------------------------------------------------------------
 313  *
 314  */
 315 #define CONFIG_SYS_DER  0
 316
 317 /*
 318  * Init Memory Controller:
 319  *
 320  * BR0/1 and OR0/1 (FLASH)
 321  */
 322
 323 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 324 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 325
 326 /* used to re-map FLASH both when starting from SRAM or FLASH:
 327  * restrict access enough to keep SRAM working (if any)
 328  * but not too much to meddle with FLASH accesses
 329  */
 330 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 331 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 332
 333 /*
 334  * FLASH timing:
 335  */
 336 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 337                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 338
 339 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 340 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 341 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 342
 343 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 344 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 345 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 346
 347 /*
 348  * BR2/3 and OR2/3 (SDRAM)
 349  *
 350  */
 351 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 352 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 353 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 354
 355 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 356 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 357
 358 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 359 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 360
 361 #ifndef CONFIG_CAN_DRIVER
 362 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 363 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 364 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 365 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 366 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 367 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 368 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 369                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 370 #endif  /* CONFIG_CAN_DRIVER */
 371
 372 /*
 373  * Memory Periodic Timer Prescaler
 374  *
 375  * The Divider for PTA (refresh timer) configuration is based on an
 376  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 377  * the number of chip selects (NCS) and the actually needed refresh
 378  * rate is done by setting MPTPR.
 379  *
 380  * PTA is calculated from
 381  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 382  *
 383  *      gclk      CPU clock (not bus clock!)
 384  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 385  *
 386  * 4096  Rows from SDRAM example configuration
 387  * 1000  factor s -> ms
 388  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 389  *    4  Number of refresh cycles per period
 390  *   64  Refresh cycle in ms per number of rows
 391  * --------------------------------------------
 392  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 393  *
 394  * 50 MHz => 50.000.000 / Divider =  98
 395  * 66 Mhz => 66.000.000 / Divider = 129
 396  * 80 Mhz => 80.000.000 / Divider = 156
 397  */
 398
 399 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 400 #define CONFIG_SYS_MAMR_PTA     98
 401
 402 /*
 403  * For 16 MBit, refresh rates could be 31.3 us
 404  * (= 64 ms / 2K = 125 / quad bursts).
 405  * For a simpler initialization, 15.6 us is used instead.
 406  *
 407  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 408  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 409  */
 410 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 411 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 412
 413 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 414 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 415 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 416
 417 /*
 418  * MAMR settings for SDRAM
 419  */
 420
 421 /* 8 column SDRAM */
 422 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 423                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 424                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 425 /* 9 column SDRAM */
 426 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 427                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 428                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 429
 430 #define CONFIG_SCC1_ENET
 431 #define CONFIG_FEC_ENET
 432 #define CONFIG_ETHPRIME         "SCC"
 433
 434 #define CONFIG_HWCONFIG         1
 435
 436 #endif  /* __CONFIG_H */