include/configs/TQM855L.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  37 #define CONFIG_TQM855L          1       /* ...on a TQM8xxL module       */
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #undef  CONFIG_8xx_CONS_NONE
  42
  43 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  44
  45 #define CONFIG_BOOTCOUNT_LIMIT
  46
  47 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  48
  49 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  50
  51 #define CONFIG_PREBOOT  "echo;" \
  52         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  53         "echo"
  54
  55 #undef  CONFIG_BOOTARGS
  56
  57 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  58         "netdev=eth0\0"                                                 \
  59         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  60                 "nfsroot=${serverip}:${rootpath}\0"                     \
  61         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  62         "addip=setenv bootargs ${bootargs} "                            \
  63                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  64                 ":${hostname}:${netdev}:off panic=1\0"                  \
  65         "flash_nfs=run nfsargs addip;"                                  \
  66                 "bootm ${kernel_addr}\0"                                \
  67         "flash_self=run ramargs addip;"                                 \
  68                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  69         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  70         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  71         "bootfile=/tftpboot/TQM855L/uImage\0"                           \
  72         "kernel_addr=40040000\0"                                        \
  73         "ramdisk_addr=40100000\0"                                       \
  74         ""
  75 #define CONFIG_BOOTCOMMAND      "run flash_self"
  76
  77 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  78 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  79
  80 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  81
  82 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  83
  84 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  85
  86 /*
  87  * BOOTP options
  88  */
  89 #define CONFIG_BOOTP_SUBNETMASK
  90 #define CONFIG_BOOTP_GATEWAY
  91 #define CONFIG_BOOTP_HOSTNAME
  92 #define CONFIG_BOOTP_BOOTPATH
  93 #define CONFIG_BOOTP_BOOTFILESIZE
  94
  95
  96 #define CONFIG_MAC_PARTITION
  97 #define CONFIG_DOS_PARTITION
  98
  99 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 100
 101
 102 /*
 103  * Command line configuration.
 104  */
 105 #include <config_cmd_default.h>
 106
 107 #define CONFIG_CMD_ASKENV
 108 #define CONFIG_CMD_DATE
 109 #define CONFIG_CMD_DHCP
 110 #define CONFIG_CMD_IDE
 111 #define CONFIG_CMD_NFS
 112 #define CONFIG_CMD_SNTP
 113
 114
 115 /*
 116  * Miscellaneous configurable options
 117  */
 118 #define CFG_LONGHELP                    /* undef to save memory         */
 119 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 120
 121 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 122 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 123 #ifdef  CFG_HUSH_PARSER
 124 #define CFG_PROMPT_HUSH_PS2     "> "
 125 #endif
 126
 127 #if defined(CONFIG_CMD_KGDB)
 128 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 129 #else
 130 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 131 #endif
 132 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 133 #define CFG_MAXARGS             16      /* max number of command args   */
 134 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 135
 136 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 137 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 138
 139 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 140
 141 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 142
 143 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 144
 145 /*
 146  * Low Level Configuration Settings
 147  * (address mappings, register initial values, etc.)
 148  * You should know what you are doing if you make changes here.
 149  */
 150 /*-----------------------------------------------------------------------
 151  * Internal Memory Mapped Register
 152  */
 153 #define CFG_IMMR                0xFFF00000
 154
 155 /*-----------------------------------------------------------------------
 156  * Definitions for initial stack pointer and data area (in DPRAM)
 157  */
 158 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 159 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 160 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 161 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 162 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 163
 164 /*-----------------------------------------------------------------------
 165  * Start addresses for the final memory configuration
 166  * (Set up by the startup code)
 167  * Please note that CFG_SDRAM_BASE _must_ start at 0
 168  */
 169 #define CFG_SDRAM_BASE          0x00000000
 170 #define CFG_FLASH_BASE          0x40000000
 171 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 172 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 173 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 174
 175 /*
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 8 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization.
 179  */
 180 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 181
 182 /*-----------------------------------------------------------------------
 183  * FLASH organization
 184  */
 185 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 186 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 187
 188 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 189 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 190
 191 #define CFG_ENV_IS_IN_FLASH     1
 192 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 193 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 194
 195 /* Address and size of Redundant Environment Sector     */
 196 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 197 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 198
 199 /*-----------------------------------------------------------------------
 200  * Hardware Information Block
 201  */
 202 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 203 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 204 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 205
 206 /*-----------------------------------------------------------------------
 207  * Cache Configuration
 208  */
 209 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 210 #if defined(CONFIG_CMD_KGDB)
 211 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 212 #endif
 213
 214 /*-----------------------------------------------------------------------
 215  * SYPCR - System Protection Control                            11-9
 216  * SYPCR can only be written once after reset!
 217  *-----------------------------------------------------------------------
 218  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 219  */
 220 #if defined(CONFIG_WATCHDOG)
 221 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 222                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 223 #else
 224 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SIUMCR - SIU Module Configuration                            11-6
 229  *-----------------------------------------------------------------------
 230  * PCMCIA config., multi-function pin tri-state
 231  */
 232 #ifndef CONFIG_CAN_DRIVER
 233 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 234 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 235 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 236 #endif  /* CONFIG_CAN_DRIVER */
 237
 238 /*-----------------------------------------------------------------------
 239  * TBSCR - Time Base Status and Control                         11-26
 240  *-----------------------------------------------------------------------
 241  * Clear Reference Interrupt Status, Timebase freezing enabled
 242  */
 243 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 244
 245 /*-----------------------------------------------------------------------
 246  * RTCSC - Real-Time Clock Status and Control Register          11-27
 247  *-----------------------------------------------------------------------
 248  */
 249 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 250
 251 /*-----------------------------------------------------------------------
 252  * PISCR - Periodic Interrupt Status and Control                11-31
 253  *-----------------------------------------------------------------------
 254  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 255  */
 256 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 257
 258 /*-----------------------------------------------------------------------
 259  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 260  *-----------------------------------------------------------------------
 261  * Reset PLL lock status sticky bit, timer expired status bit and timer
 262  * interrupt status bit
 263  */
 264 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 265
 266 /*-----------------------------------------------------------------------
 267  * SCCR - System Clock and reset Control Register               15-27
 268  *-----------------------------------------------------------------------
 269  * Set clock output, timebase and RTC source and divider,
 270  * power management and some other internal clocks
 271  */
 272 #define SCCR_MASK       SCCR_EBDF11
 273 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 274                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 275                          SCCR_DFALCD00)
 276
 277 /*-----------------------------------------------------------------------
 278  * PCMCIA stuff
 279  *-----------------------------------------------------------------------
 280  *
 281  */
 282 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 283 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 284 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 285 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 286 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 287 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 288 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 289 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 290
 291 /*-----------------------------------------------------------------------
 292  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 293  *-----------------------------------------------------------------------
 294  */
 295
 296 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 297
 298 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 299 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 300 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 301
 302 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 303 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 304
 305 #define CFG_ATA_IDE0_OFFSET     0x0000
 306
 307 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 308
 309 /* Offset for data I/O                  */
 310 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 311
 312 /* Offset for normal register accesses  */
 313 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 314
 315 /* Offset for alternate registers       */
 316 #define CFG_ATA_ALT_OFFSET      0x0100
 317
 318 /*-----------------------------------------------------------------------
 319  *
 320  *-----------------------------------------------------------------------
 321  *
 322  */
 323 #define CFG_DER 0
 324
 325 /*
 326  * Init Memory Controller:
 327  *
 328  * BR0/1 and OR0/1 (FLASH)
 329  */
 330
 331 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 332 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 333
 334 /* used to re-map FLASH both when starting from SRAM or FLASH:
 335  * restrict access enough to keep SRAM working (if any)
 336  * but not too much to meddle with FLASH accesses
 337  */
 338 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 339 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 340
 341 /*
 342  * FLASH timing:
 343  */
 344 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 345                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 346
 347 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 348 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 349 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 350
 351 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 352 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 353 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 354
 355 /*
 356  * BR2/3 and OR2/3 (SDRAM)
 357  *
 358  */
 359 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 360 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 361 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 362
 363 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 364 #define CFG_OR_TIMING_SDRAM     0x00000A00
 365
 366 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 367 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 368
 369 #ifndef CONFIG_CAN_DRIVER
 370 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 371 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 372 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 373 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 374 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 375 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 376 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 377                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 378 #endif  /* CONFIG_CAN_DRIVER */
 379
 380 /*
 381  * Memory Periodic Timer Prescaler
 382  *
 383  * The Divider for PTA (refresh timer) configuration is based on an
 384  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 385  * the number of chip selects (NCS) and the actually needed refresh
 386  * rate is done by setting MPTPR.
 387  *
 388  * PTA is calculated from
 389  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 390  *
 391  *      gclk      CPU clock (not bus clock!)
 392  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 393  *
 394  * 4096  Rows from SDRAM example configuration
 395  * 1000  factor s -> ms
 396  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 397  *    4  Number of refresh cycles per period
 398  *   64  Refresh cycle in ms per number of rows
 399  * --------------------------------------------
 400  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 401  *
 402  * 50 MHz => 50.000.000 / Divider =  98
 403  * 66 Mhz => 66.000.000 / Divider = 129
 404  * 80 Mhz => 80.000.000 / Divider = 156
 405  */
 406
 407 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 408 #define CFG_MAMR_PTA    98
 409
 410 /*
 411  * For 16 MBit, refresh rates could be 31.3 us
 412  * (= 64 ms / 2K = 125 / quad bursts).
 413  * For a simpler initialization, 15.6 us is used instead.
 414  *
 415  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 416  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 417  */
 418 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 419 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 420
 421 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 422 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 423 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 424
 425 /*
 426  * MAMR settings for SDRAM
 427  */
 428
 429 /* 8 column SDRAM */
 430 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 431                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 432                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 433 /* 9 column SDRAM */
 434 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 435                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 436                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 437
 438
 439 /*
 440  * Internal Definitions
 441  *
 442  * Boot Flags
 443  */
 444 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 445 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 446
 447 #define CONFIG_SCC1_ENET
 448 #define CONFIG_FEC_ENET
 449 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 450
 451 #endif  /* __CONFIG_H */