include/configs/TQM855M.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  37 #define CONFIG_TQM855M          1       /* ...on a TQM8xxM module       */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40000000
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #define CONFIG_SYS_SMC_RXBUFLEN 128
  43 #define CONFIG_SYS_MAXIDLE      10
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  45
  46 #define CONFIG_BOOTCOUNT_LIMIT
  47
  48 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  49
  50 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  51
  52 #define CONFIG_PREBOOT  "echo;" \
  53         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  54         "echo"
  55
  56 #undef  CONFIG_BOOTARGS
  57
  58 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  59         "netdev=eth0\0"                                                 \
  60         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  61                 "nfsroot=${serverip}:${rootpath}\0"                     \
  62         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  63         "addip=setenv bootargs ${bootargs} "                            \
  64                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  65                 ":${hostname}:${netdev}:off panic=1\0"                  \
  66         "flash_nfs=run nfsargs addip;"                                  \
  67                 "bootm ${kernel_addr}\0"                                \
  68         "flash_self=run ramargs addip;"                                 \
  69                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  70         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  71         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  72         "hostname=TQM855M\0"                                            \
  73         "bootfile=TQM855M/uImage\0"                                     \
  74         "fdt_addr=40080000\0"                                           \
  75         "kernel_addr=400A0000\0"                                        \
  76         "ramdisk_addr=40280000\0"                                       \
  77         "u-boot=TQM855M/u-image.bin\0"                                  \
  78         "load=tftp 200000 ${u-boot}\0"                                  \
  79         "update=prot off 40000000 +${filesize};"                        \
  80                 "era 40000000 +${filesize};"                            \
  81                 "cp.b 200000 40000000 ${filesize};"                     \
  82                 "sete filesize;save\0"                                  \
  83         ""
  84 #define CONFIG_BOOTCOMMAND      "run flash_self"
  85
  86 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  87 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  88
  89 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  90
  91 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  92
  93 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  94
  95 /* enable I2C and select the hardware/software driver */
  96 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  97 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  98
  99 #define CONFIG_SYS_I2C_SPEED            93000   /* 93 kHz is supposed to work   */
 100 #define CONFIG_SYS_I2C_SLAVE            0xFE
 101
 102 #ifdef CONFIG_SOFT_I2C
 103 /*
 104  * Software (bit-bang) I2C driver configuration
 105  */
 106 #define PB_SCL          0x00000020      /* PB 26 */
 107 #define PB_SDA          0x00000010      /* PB 27 */
 108
 109 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 110 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 111 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 112 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 113 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 114                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 115 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 116                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 117 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 118 #endif  /* CONFIG_SOFT_I2C */
 119
 120 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM AT24C64       */
 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2               /* two byte address     */
 122 #if 0
 123 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec  */
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 126 #endif
 127
 128 /*
 129  * BOOTP options
 130  */
 131 #define CONFIG_BOOTP_SUBNETMASK
 132 #define CONFIG_BOOTP_GATEWAY
 133 #define CONFIG_BOOTP_HOSTNAME
 134 #define CONFIG_BOOTP_BOOTPATH
 135 #define CONFIG_BOOTP_BOOTFILESIZE
 136
 137
 138 #define CONFIG_MAC_PARTITION
 139 #define CONFIG_DOS_PARTITION
 140
 141 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 142
 143
 144 /*
 145  * Command line configuration.
 146  */
 147 #include <config_cmd_default.h>
 148
 149 #define CONFIG_CMD_ASKENV
 150 #define CONFIG_CMD_DATE
 151 #define CONFIG_CMD_DHCP
 152 #define CONFIG_CMD_ELF
 153 #define CONFIG_CMD_EXT2
 154 #define CONFIG_CMD_EEPROM
 155 #define CONFIG_CMD_IDE
 156 #define CONFIG_CMD_JFFS2
 157 #define CONFIG_CMD_NFS
 158 #define CONFIG_CMD_SNTP
 159
 160
 161 #define CONFIG_NETCONSOLE
 162
 163
 164 /*
 165  * Miscellaneous configurable options
 166  */
 167 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 168 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 169
 170 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 171 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 172 #ifdef  CONFIG_SYS_HUSH_PARSER
 173 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 174 #endif
 175
 176 #if defined(CONFIG_CMD_KGDB)
 177 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 178 #else
 179 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 180 #endif
 181 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 182 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 183 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 184
 185 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 186 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 187
 188 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 189
 190 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 191
 192 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 193
 194 /*
 195  * Low Level Configuration Settings
 196  * (address mappings, register initial values, etc.)
 197  * You should know what you are doing if you make changes here.
 198  */
 199 /*-----------------------------------------------------------------------
 200  * Internal Memory Mapped Register
 201  */
 202 #define CONFIG_SYS_IMMR         0xFFF00000
 203
 204 /*-----------------------------------------------------------------------
 205  * Definitions for initial stack pointer and data area (in DPRAM)
 206  */
 207 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 208 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 209 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 210 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 211
 212 /*-----------------------------------------------------------------------
 213  * Start addresses for the final memory configuration
 214  * (Set up by the startup code)
 215  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 216  */
 217 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 218 #define CONFIG_SYS_FLASH_BASE           0x40000000
 219 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 221 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 222
 223 /*
 224  * For booting Linux, the board info and command line data
 225  * have to be in the first 8 MB of memory, since this is
 226  * the maximum mapped by the Linux kernel during initialization.
 227  */
 228 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 229
 230 /*-----------------------------------------------------------------------
 231  * FLASH organization
 232  */
 233
 234 /* use CFI flash driver */
 235 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 236 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 237 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 238 #define CONFIG_SYS_FLASH_EMPTY_INFO
 239 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 240 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 241 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 242
 243 #define CONFIG_ENV_IS_IN_FLASH  1
 244 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 245 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 246 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector     */
 247
 248 /* Address and size of Redundant Environment Sector     */
 249 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 250 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 251
 252 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 253
 254 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 255
 256 /*-----------------------------------------------------------------------
 257  * Dynamic MTD partition support
 258  */
 259 #define CONFIG_CMD_MTDPARTS
 260 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 261 #define CONFIG_FLASH_CFI_MTD
 262 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 263
 264 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 265                                                 "128k(dtb),"            \
 266                                                 "1920k(kernel),"        \
 267                                                 "5632(rootfs),"         \
 268                                                 "4m(data)"
 269
 270 /*-----------------------------------------------------------------------
 271  * Hardware Information Block
 272  */
 273 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 274 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 275 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 276
 277 /*-----------------------------------------------------------------------
 278  * Cache Configuration
 279  */
 280 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 281 #if defined(CONFIG_CMD_KGDB)
 282 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 283 #endif
 284
 285 /*-----------------------------------------------------------------------
 286  * SYPCR - System Protection Control                            11-9
 287  * SYPCR can only be written once after reset!
 288  *-----------------------------------------------------------------------
 289  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 290  */
 291 #if defined(CONFIG_WATCHDOG)
 292 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 293                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 294 #else
 295 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 296 #endif
 297
 298 /*-----------------------------------------------------------------------
 299  * SIUMCR - SIU Module Configuration                            11-6
 300  *-----------------------------------------------------------------------
 301  * PCMCIA config., multi-function pin tri-state
 302  */
 303 #ifndef CONFIG_CAN_DRIVER
 304 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 305 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 306 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 307 #endif  /* CONFIG_CAN_DRIVER */
 308
 309 /*-----------------------------------------------------------------------
 310  * TBSCR - Time Base Status and Control                         11-26
 311  *-----------------------------------------------------------------------
 312  * Clear Reference Interrupt Status, Timebase freezing enabled
 313  */
 314 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 315
 316 /*-----------------------------------------------------------------------
 317  * RTCSC - Real-Time Clock Status and Control Register          11-27
 318  *-----------------------------------------------------------------------
 319  */
 320 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 321
 322 /*-----------------------------------------------------------------------
 323  * PISCR - Periodic Interrupt Status and Control                11-31
 324  *-----------------------------------------------------------------------
 325  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 326  */
 327 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 328
 329 /*-----------------------------------------------------------------------
 330  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 331  *-----------------------------------------------------------------------
 332  * Reset PLL lock status sticky bit, timer expired status bit and timer
 333  * interrupt status bit
 334  */
 335 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 336
 337 /*-----------------------------------------------------------------------
 338  * SCCR - System Clock and reset Control Register               15-27
 339  *-----------------------------------------------------------------------
 340  * Set clock output, timebase and RTC source and divider,
 341  * power management and some other internal clocks
 342  */
 343 #define SCCR_MASK       SCCR_EBDF11
 344 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 345                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 346                          SCCR_DFALCD00)
 347
 348 /*-----------------------------------------------------------------------
 349  * PCMCIA stuff
 350  *-----------------------------------------------------------------------
 351  *
 352  */
 353 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 354 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 355 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 356 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 357 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 358 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 359 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 360 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 361
 362 /*-----------------------------------------------------------------------
 363  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 364  *-----------------------------------------------------------------------
 365  */
 366
 367 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 368
 369 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 370 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 371 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 372
 373 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 374 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 375
 376 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 377
 378 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 379
 380 /* Offset for data I/O                  */
 381 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 382
 383 /* Offset for normal register accesses  */
 384 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 385
 386 /* Offset for alternate registers       */
 387 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 388
 389 /*-----------------------------------------------------------------------
 390  *
 391  *-----------------------------------------------------------------------
 392  *
 393  */
 394 #define CONFIG_SYS_DER  0
 395
 396 /*
 397  * Init Memory Controller:
 398  *
 399  * BR0/1 and OR0/1 (FLASH)
 400  */
 401
 402 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 403 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 404
 405 /* used to re-map FLASH both when starting from SRAM or FLASH:
 406  * restrict access enough to keep SRAM working (if any)
 407  * but not too much to meddle with FLASH accesses
 408  */
 409 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 410 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 411
 412 /*
 413  * FLASH timing:
 414  */
 415 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 416                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 417
 418 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 419 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 420 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 421
 422 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 423 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 424 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 425
 426 /*
 427  * BR2/3 and OR2/3 (SDRAM)
 428  *
 429  */
 430 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 431 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 432 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 433
 434 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 435 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 436
 437 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 438 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 439
 440 #ifndef CONFIG_CAN_DRIVER
 441 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 442 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 443 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 444 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 445 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 446 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 447 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 448                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 449 #endif  /* CONFIG_CAN_DRIVER */
 450
 451 /*
 452  * Memory Periodic Timer Prescaler
 453  *
 454  * The Divider for PTA (refresh timer) configuration is based on an
 455  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 456  * the number of chip selects (NCS) and the actually needed refresh
 457  * rate is done by setting MPTPR.
 458  *
 459  * PTA is calculated from
 460  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 461  *
 462  *      gclk      CPU clock (not bus clock!)
 463  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 464  *
 465  * 4096  Rows from SDRAM example configuration
 466  * 1000  factor s -> ms
 467  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 468  *    4  Number of refresh cycles per period
 469  *   64  Refresh cycle in ms per number of rows
 470  * --------------------------------------------
 471  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 472  *
 473  * 50 MHz => 50.000.000 / Divider =  98
 474  * 66 Mhz => 66.000.000 / Divider = 129
 475  * 80 Mhz => 80.000.000 / Divider = 156
 476  */
 477
 478 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 479 #define CONFIG_SYS_MAMR_PTA     98
 480
 481 /*
 482  * For 16 MBit, refresh rates could be 31.3 us
 483  * (= 64 ms / 2K = 125 / quad bursts).
 484  * For a simpler initialization, 15.6 us is used instead.
 485  *
 486  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 487  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 488  */
 489 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 490 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 491
 492 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 493 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 494 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 495
 496 /*
 497  * MAMR settings for SDRAM
 498  */
 499
 500 /* 8 column SDRAM */
 501 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 502                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 503                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 504 /* 9 column SDRAM */
 505 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 506                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 507                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 508
 509 #define CONFIG_SCC1_ENET
 510 #define CONFIG_FEC_ENET
 511 #define CONFIG_ETHPRIME         "SCC"
 512
 513 /* pass open firmware flat tree */
 514 #define CONFIG_OF_LIBFDT        1
 515 #define CONFIG_OF_BOARD_SETUP   1
 516 #define CONFIG_HWCONFIG         1
 517
 518 #endif  /* __CONFIG_H */