include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  46 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  47 #ifdef CONFIG_TQM8548
  48 #define CONFIG_PCI1
  49 #define CONFIG_PCIE1
  50 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  51 #endif
  52
  53 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  54
  55 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  56
  57  /*
  58  * Configuration for big NOR Flashes
  59  *
  60  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  61  * Please be aware, that this changes the whole memory map (new CCSRBAR
  62  * address, etc). You have to use an adapted Linux kernel or FDT blob
  63  * if this option is set.
  64  */
  65 #undef CONFIG_TQM_BIGFLASH
  66
  67 /*
  68  * NAND flash support (disabled by default)
  69  *
  70  * Warning: NAND support will likely increase the U-Boot image size
  71  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  72  */
  73 #undef CONFIG_NAND
  74
  75 /*
  76  * MPC8540 and MPC8548 don't have CPM module
  77  */
  78 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  79 #define CONFIG_CPM2             1       /* has CPM2                     */
  80 #endif
  81
  82 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  83
  84 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support           */
  85
  86 /*
  87  * sysclk for MPC85xx
  88  *
  89  * Two valid values are:
  90  *    33333333
  91  *    66666666
  92  *
  93  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  94  * is likely the desired value here, so that is now the default.
  95  * The board, however, can run at 66MHz.  In any event, this value
  96  * must match the settings of some switches.  Details can be found
  97  * in the README.mpc85xxads.
  98  */
  99
 100 #ifndef CONFIG_SYS_CLK_FREQ
 101 #define CONFIG_SYS_CLK_FREQ     33333333
 102 #endif
 103
 104 /*
 105  * These can be toggled for performance analysis, otherwise use default.
 106  */
 107 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 108 #define CONFIG_BTB                      /* toggle branch predition      */
 109 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming        */
 110
 111 #define CFG_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */
 112
 113 #undef  CFG_DRAM_TEST                   /* memory test, takes time      */
 114 #define CFG_MEMTEST_START       0x00000000
 115 #define CFG_MEMTEST_END         0x10000000
 116
 117 /*
 118  * Base addresses -- Note these are effective addresses where the
 119  * actual resources get mapped (not physical addresses)
 120  */
 121 #define CFG_CCSRBAR_DEFAULT     0xFF700000      /* CCSRBAR Default      */
 122 #ifdef CONFIG_TQM_BIGFLASH
 123 #define CFG_CCSRBAR             0xA0000000      /* relocated CCSRBAR    */
 124 #else /* !CONFIG_TQM_BIGFLASH */
 125 #define CFG_CCSRBAR             0xE0000000      /* relocated CCSRBAR    */
 126 #endif /* CONFIG_TQM_BIGFLASH */
 127 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 128 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 129
 130 #define CFG_PCI1_ADDR           (CFG_CCSRBAR + 0x8000)
 131 #define CFG_PCI2_ADDR           (CFG_CCSRBAR + 0x9000)
 132 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR + 0xa000)
 133
 134 /*
 135  * DDR Setup
 136  */
 137 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory */
 138 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 139
 140 #define CONFIG_NUM_DDR_CONTROLLERS      1
 141 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 142 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 143
 144 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 145 /* TQM8540 & 8560 need DLL-override */
 146 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 147 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 148 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 149
 150 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 151     defined(CONFIG_TQM8548)
 152 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 153 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 154
 155 /*
 156  * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 157  * series while new boards have 'N' type Flashes from the S29GLxxxN
 158  * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 159  */
 160 #ifdef CONFIG_TQM8548
 161 #define CONFIG_TQM_FLASH_N_TYPE
 162 #endif /* CONFIG_TQM8548 */
 163
 164 /*
 165  * Flash on the Local Bus
 166  */
 167 #ifdef CONFIG_TQM_BIGFLASH
 168 #define CFG_FLASH0              0xE0000000
 169 #define CFG_FLASH1              0xC0000000
 170 #else /* !CONFIG_TQM_BIGFLASH */
 171 #define CFG_FLASH0              0xFC000000
 172 #define CFG_FLASH1              0xF8000000
 173 #endif /* CONFIG_TQM_BIGFLASH */
 174 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH1, CFG_FLASH0 }
 175
 176 #define CFG_LBC_FLASH_BASE      CFG_FLASH1      /* Localbus flash start */
 177 #define CFG_FLASH_BASE          CFG_LBC_FLASH_BASE  /* start of FLASH   */
 178
 179 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 180  *
 181  * Note: According to timing specifications external addr latch delay
 182  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 183  *
 184  * For other Local Bus Clocks see following table:
 185  *
 186  * Clock/MHz   CFG_ORx_PRELIM
 187  * 166         0x.....CA5
 188  * 133         0x.....C85
 189  * 100         0x.....C65
 190  *  83         0x.....FA2
 191  *  66         0x.....C82
 192  *  50         0x.....C60
 193  *  42         0x.....040
 194  *  33         0x.....030
 195  *  25         0x.....020
 196  *
 197  */
 198 #ifdef CONFIG_TQM_BIGFLASH
 199 #define CFG_BR0_PRELIM          0xE0001801      /* port size 32bit      */
 200 #define CFG_OR0_PRELIM          0xE0000040      /* 512MB Flash          */
 201 #define CFG_BR1_PRELIM          0xC0001801      /* port size 32bit      */
 202 #define CFG_OR1_PRELIM          0xE0000040      /* 512MB Flash          */
 203 #else /* !CONFIG_TQM_BIGFLASH */
 204 #define CFG_BR0_PRELIM          0xfc001801      /* port size 32bit      */
 205 #define CFG_OR0_PRELIM          0xfc000040      /* 64MB Flash           */
 206 #define CFG_BR1_PRELIM          0xf8001801      /* port size 32bit      */
 207 #define CFG_OR1_PRELIM          0xfc000040      /* 64MB Flash           */
 208 #endif /* CONFIG_TQM_BIGFLASH */
 209
 210 #define CFG_FLASH_CFI                   /* flash is CFI compat.         */
 211 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 212 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 213 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 214 #define CFG_FLASH_USE_BUFFER_WRITE      1 /* speed up output to Flash   */
 215
 216 #define CFG_MAX_FLASH_BANKS     2       /* number of banks              */
 217 #define CFG_MAX_FLASH_SECT      512     /* sectors per device           */
 218 #undef  CFG_FLASH_CHECKSUM
 219 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms)     */
 220 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms)     */
 221
 222 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 223
 224 /*
 225  * Note: when changing the Local Bus clock divider you have to
 226  * change the timing values in CFG_ORx_PRELIM.
 227  *
 228  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 229  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 230  *                     for Local Bus Clock > 83.3 MHz.
 231  */
 232 #define CFG_LBC_LCRR            0x00030008      /* LB clock ratio reg   */
 233 #define CFG_LBC_LBCR            0x00000000      /* LB config reg        */
 234 #define CFG_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 235 #define CFG_LBC_MRTPR           0x20000000      /* LB refresh timer presc.*/
 236
 237 #define CONFIG_L1_INIT_RAM
 238 #define CFG_INIT_RAM_LOCK       1
 239 #define CFG_INIT_RAM_ADDR       (CFG_CCSRBAR \
 240                                  + 0x04010000)  /* Initial RAM address  */
 241 #define CFG_INIT_RAM_END        0x4000          /* End used area in RAM */
 242
 243 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data       */
 244 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 245 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 246
 247 #define CFG_MONITOR_LEN         (~TEXT_BASE + 1)/* Reserved for Monitor */
 248 #define CFG_MALLOC_LEN          (384 * 1024)    /* Reserved for malloc  */
 249
 250 /* Serial Port */
 251 #if defined(CONFIG_TQM8560)
 252
 253 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 254 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 255 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 256
 257 #else /* !CONFIG_TQM8560 */
 258
 259 #define CONFIG_CONS_INDEX     1
 260 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 261 #define CFG_NS16550
 262 #define CFG_NS16550_SERIAL
 263 #define CFG_NS16550_REG_SIZE    1
 264 #define CFG_NS16550_CLK         get_bus_freq(0)
 265
 266 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 267 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 268
 269 /* PS/2 Keyboard */
 270 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 271 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 272 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 273 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
 274 #define CONFIG_BOARD_EARLY_INIT_R       1
 275
 276 #endif /* CONFIG_TQM8560 */
 277
 278 #define CONFIG_BAUDRATE         115200
 279
 280 #define CFG_BAUDRATE_TABLE      \
 281         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 282
 283 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 284 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 285 #ifdef  CFG_HUSH_PARSER
 286 #define CFG_PROMPT_HUSH_PS2     "> "
 287 #endif
 288
 289 /* pass open firmware flat tree */
 290 #define CONFIG_OF_LIBFDT                1
 291 #define CONFIG_OF_BOARD_SETUP           1
 292 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 293
 294 /* CAN */
 295 #define CFG_CAN_BASE            (CFG_CCSRBAR \
 296                                  + 0x03000000)  /* CAN base address     */
 297 #ifdef CONFIG_CAN_DRIVER
 298 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 KiB address mask  */
 299 #define CFG_OR2_CAN             (CFG_CAN_OR_AM | OR_UPM_BI)
 300 #define CFG_BR2_CAN             ((CFG_CAN_BASE & BR_BA) | \
 301                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 302 #endif /* CONFIG_CAN_DRIVER */
 303
 304 /*
 305  * I2C
 306  */
 307 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 308 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 309 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 310 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 311 #define CFG_I2C_SLAVE           0x7F
 312 #define CFG_I2C_NOPROBES        {0x48}  /* Don't probe these addrs      */
 313 #define CFG_I2C_OFFSET          0x3000
 314
 315 /* I2C RTC */
 316 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 317 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 318
 319 /* I2C EEPROM */
 320 /*
 321  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 322  */
 323 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x             */
 324 #define CFG_I2C_EEPROM_ADDR_LEN         2
 325 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 326 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 327 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 328 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom */
 329
 330 /* I2C SYSMON (LM75) */
 331 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 332 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 333 #define CFG_DTT_MAX_TEMP        70
 334 #define CFG_DTT_LOW_TEMP        -30
 335 #define CFG_DTT_HYSTERESIS      3
 336
 337 #ifndef CONFIG_PCIE1
 338 /* RapidIO MMU */
 339 #ifdef CONFIG_TQM_BIGFLASH
 340 #define CFG_RIO_MEM_BASE        0xb0000000      /* base address         */
 341 #define CFG_RIO_MEM_SIZE        0x10000000      /* 256M                 */
 342 #else /* !CONFIG_TQM_BIGFLASH */
 343 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address         */
 344 #define CFG_RIO_MEM_SIZE        0x20000000      /* 512M                 */
 345 #endif /* CONFIG_TQM_BIGFLASH */
 346 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 347 #endif /* CONFIG_PCIE1 */
 348
 349 /* NAND FLASH */
 350 #ifdef CONFIG_NAND
 351
 352 #undef CONFIG_NAND_LEGACY
 353
 354 #define CONFIG_NAND_FSL_UPM     1
 355
 356 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 357
 358 /* address distance between chip selects */
 359 #define CFG_NAND_SELECT_DEVICE  1
 360 #define CFG_NAND_CS_DIST        0x200
 361
 362 #define CFG_NAND_SIZE           0x8000
 363 #define CFG_NAND0_BASE          (CFG_CCSRBAR + 0x03010000)
 364 #define CFG_NAND1_BASE          (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
 365 #define CFG_NAND2_BASE          (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
 366 #define CFG_NAND3_BASE          (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
 367
 368 #define CFG_MAX_NAND_DEVICE     2       /* Max number of NAND devices   */
 369 #define NAND_MAX_CHIPS          1
 370
 371 #if (CFG_MAX_NAND_DEVICE == 1)
 372 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
 373 #elif (CFG_MAX_NAND_DEVICE == 2)
 374 #define CFG_NAND_QUIET_TEST     1
 375 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
 376                              CFG_NAND1_BASE, \
 377 }
 378 #elif (CFG_MAX_NAND_DEVICE == 4)
 379 #define CFG_NAND_QUIET_TEST     1
 380 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
 381                              CFG_NAND1_BASE, \
 382                              CFG_NAND2_BASE, \
 383                              CFG_NAND3_BASE, \
 384 }
 385 #endif
 386
 387 /* CS3 for NAND Flash */
 388 #define CFG_BR3_PRELIM          ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \
 389                                  BR_MS_UPMB | BR_V)
 390 #define CFG_OR3_PRELIM          (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI)
 391
 392 #define NAND_BIG_DELAY_US       25      /* max tR for Samsung devices   */
 393
 394 #endif /* CONFIG_NAND */
 395
 396 /*
 397  * General PCI
 398  * Addresses are mapped 1-1.
 399  */
 400 #define CFG_PCI1_MEM_BASE       0x80000000
 401 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 402 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M                 */
 403 #define CFG_PCI1_IO_BASE        (CFG_CCSRBAR + 0x02000000)
 404 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 405 #define CFG_PCI1_IO_SIZE        0x1000000       /*  16M                 */
 406
 407 /* PCI view of System Memory */
 408 #define CFG_PCI_MEMORY_BUS      0x00000000
 409 #define CFG_PCI_MEMORY_PHYS     0x00000000
 410 #define CFG_PCI_MEMORY_SIZE     0x80000000
 411
 412 #ifdef CONFIG_PCIE1
 413 /*
 414  * General PCI express
 415  * Addresses are mapped 1-1.
 416  */
 417 #ifdef CONFIG_TQM_BIGFLASH
 418 #define CFG_PCIE1_MEM_BASE      0xb0000000
 419 #define CFG_PCIE1_MEM_SIZE      0x10000000      /* 512M                 */
 420 #define CFG_PCIE1_IO_BASE       0xaf000000
 421 #else /* !CONFIG_TQM_BIGFLASH */
 422 #define CFG_PCIE1_MEM_BASE      0xc0000000
 423 #define CFG_PCIE1_MEM_SIZE      0x20000000      /* 512M                 */
 424 #define CFG_PCIE1_IO_BASE       0xef000000
 425 #endif /* CONFIG_TQM_BIGFLASH */
 426 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 427 #define CFG_PCIE1_IO_PHYS       CFG_PCIE1_IO_BASE
 428 #define CFG_PCIE1_IO_SIZE       0x1000000       /* 16M                  */
 429 #endif /* CONFIG_PCIE1 */
 430
 431 #if defined(CONFIG_PCI)
 432
 433 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 434
 435 #define CONFIG_EEPRO100
 436 #undef CONFIG_TULIP
 437
 438 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 439 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola                     */
 440
 441 #endif /* CONFIG_PCI */
 442
 443 #define CONFIG_NET_MULTI        1
 444
 445 #define CONFIG_MII              1       /* MII PHY management           */
 446 #define CONFIG_TSEC1    1
 447 #define CONFIG_TSEC1_NAME       "TSEC0"
 448 #define CONFIG_TSEC2    1
 449 #define CONFIG_TSEC2_NAME       "TSEC1"
 450 #define TSEC1_PHY_ADDR          2
 451 #define TSEC2_PHY_ADDR          1
 452 #define TSEC1_PHYIDX            0
 453 #define TSEC2_PHYIDX            0
 454 #define TSEC1_FLAGS             TSEC_GIGABIT
 455 #define TSEC2_FLAGS             TSEC_GIGABIT
 456 #define FEC_PHY_ADDR            3
 457 #define FEC_PHYIDX              0
 458 #define FEC_FLAGS               0
 459 #define CONFIG_HAS_ETH0
 460 #define CONFIG_HAS_ETH1
 461 #define CONFIG_HAS_ETH2
 462
 463 #ifdef CONFIG_TQM8548
 464 /*
 465  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 466  *
 467  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 468  * additional adapter (AIO) between module and Starterkit.
 469  */
 470 #define CONFIG_TSEC3    1
 471 #define CONFIG_TSEC3_NAME       "TSEC2"
 472 #define CONFIG_TSEC4    1
 473 #define CONFIG_TSEC4_NAME       "TSEC3"
 474 #define TSEC3_PHY_ADDR          4
 475 #define TSEC4_PHY_ADDR          5
 476 #define TSEC3_PHYIDX            0
 477 #define TSEC4_PHYIDX            0
 478 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 479 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 480 #define CONFIG_HAS_ETH3
 481 #define CONFIG_HAS_ETH4
 482 #endif  /* CONFIG_TQM8548 */
 483
 484 /* Options are TSEC[0-1], FEC */
 485 #define CONFIG_ETHPRIME         "TSEC0"
 486
 487 #if defined(CONFIG_TQM8540)
 488 /*
 489  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 490  * The FEC port is connected on the same signals as the FCC3 port
 491  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 492  *
 493  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 494  * a - d (X50.2 - 3) to enable the FEC port.
 495  */
 496 #define CONFIG_MPC85XX_FEC      1
 497 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 498 #endif
 499
 500 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 501 /*
 502  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 503  * can be used at once, since only one FCC port is available on the STK85xx
 504  * Starterkit.
 505  *
 506  * To use this port you have to configure U-Boot to use the FCC port 1...2
 507  * and set the X47/X50 jumper to:
 508  * FCC1: a - b (X47.2 - X50.2)
 509  * FCC2: a - c (X50.2 - 1)
 510  */
 511 #define CONFIG_ETHER_ON_FCC
 512 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 513 #endif
 514
 515 #if defined(CONFIG_TQM8560)
 516 /*
 517  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 518  * can be used at once, since only one FCC port is available on the STK85xx
 519  * Starterkit.
 520  *
 521  * To use this port you have to configure U-Boot to use the FCC port 1...3
 522  * and set the X47/X50 jumper to:
 523  * FCC1: a - b (X47.2 - X50.2)
 524  * FCC2: a - c (X50.2 - 1)
 525  * FCC3: a - d (X50.2 - 3)
 526  */
 527 #define CONFIG_ETHER_ON_FCC
 528 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 529 #endif
 530
 531 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 532 #define CONFIG_ETHER_ON_FCC1
 533 #define CFG_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 534                                  CMXFCR_TF1CS_MSK)
 535 #define CFG_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 536 #define CFG_CPMFCR_RAMTYPE      0
 537 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 538 #endif
 539
 540 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 541 #define CONFIG_ETHER_ON_FCC2
 542 #define CFG_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 543                                  CMXFCR_TF2CS_MSK)
 544 #define CFG_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 545 #define CFG_CPMFCR_RAMTYPE      0
 546 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 547 #endif
 548
 549 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 550 #define CONFIG_ETHER_ON_FCC3
 551 #define CFG_CMXFCR_MASK3        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 552                                  CMXFCR_TF3CS_MSK)
 553 #define CFG_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 554 #define CFG_CPMFCR_RAMTYPE      0
 555 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 556 #endif
 557
 558 /*
 559  * Environment
 560  */
 561 #define CONFIG_ENV_IS_IN_FLASH  1
 562
 563 #ifdef CONFIG_TQM_FLASH_N_TYPE
 564 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K (one sector) for env    */
 565 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 566 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env    */
 567 #endif /* CONFIG_TQM_FLASH_N_TYPE */
 568 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 569 #define CONFIG_ENV_SIZE         0x2000
 570 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 571 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 572
 573 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 574 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 575
 576 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 577
 578 /*
 579  * BOOTP options
 580  */
 581 #define CONFIG_BOOTP_BOOTFILESIZE
 582 #define CONFIG_BOOTP_BOOTPATH
 583 #define CONFIG_BOOTP_GATEWAY
 584 #define CONFIG_BOOTP_HOSTNAME
 585
 586 #ifdef CONFIG_NAND
 587 /*
 588  * Use NAND-FLash as JFFS2 device
 589  */
 590 #define CONFIG_CMD_NAND
 591 #define CONFIG_CMD_JFFS2
 592
 593 #define CONFIG_JFFS2_NAND       1
 594
 595 #ifdef CONFIG_JFFS2_CMDLINE
 596 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 597 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 598 #else
 599 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 600 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 601 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 602 #endif /* CONFIG_JFFS2_CMDLINE */
 603
 604 #endif /* CONFIG_NAND */
 605
 606 /*
 607  * Command line configuration.
 608  */
 609 #include <config_cmd_default.h>
 610
 611 #define CONFIG_CMD_PING
 612 #define CONFIG_CMD_I2C
 613 #define CONFIG_CMD_DHCP
 614 #define CONFIG_CMD_NFS
 615 #define CONFIG_CMD_SNTP
 616 #define CONFIG_CMD_DATE
 617 #define CONFIG_CMD_EEPROM
 618 #define CONFIG_CMD_DTT
 619 #define CONFIG_CMD_MII
 620
 621 #if defined(CONFIG_PCI)
 622 #define CONFIG_CMD_PCI
 623 #endif
 624
 625 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 626
 627 /*
 628  * Miscellaneous configurable options
 629  */
 630 #define CFG_LONGHELP                    /* undef to save memory         */
 631 #define CFG_LOAD_ADDR   0x2000000       /* default load address         */
 632 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 633
 634 #if defined(CONFIG_CMD_KGDB)
 635 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 636 #else
 637 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 638 #endif
 639
 640 #define CFG_PBSIZE      (CFG_CBSIZE + \
 641                          sizeof(CFG_PROMPT) + 16)   /* Print Buf Size   */
 642 #define CFG_MAXARGS     16              /* max number of command args   */
 643 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 644 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks  */
 645
 646 /*
 647  * For booting Linux, the board info and command line data
 648  * have to be in the first 8 MB of memory, since this is
 649  * the maximum mapped by the Linux kernel during initialization.
 650  */
 651 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 652
 653 /*
 654  * Internal Definitions
 655  *
 656  * Boot Flags
 657  */
 658 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 659 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 660
 661 #if defined(CONFIG_CMD_KGDB)
 662 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 663 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 664 #endif
 665
 666 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 667
 668 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 669
 670 #define CONFIG_PREBOOT  "echo;" \
 671         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 672         "echo"
 673
 674 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 675
 676
 677 /*
 678  * Setup some board specific values for the default environment variables
 679  */
 680 #ifdef CONFIG_CPM2
 681 #define CONFIG_ENV_CONSDEV              "consdev=ttyCPM0\0"
 682 #else
 683 #define CONFIG_ENV_CONSDEV              "consdev=ttyS0\0"
 684 #endif
 685 #define CONFIG_ENV_FDT_FILE     "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 686                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 687 #define CONFIG_ENV_BOOTFILE     "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 688 #define CONFIG_ENV_UBOOT                "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 689                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 690
 691 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 692         CONFIG_ENV_BOOTFILE                                             \
 693         CONFIG_ENV_FDT_FILE                                             \
 694         CONFIG_ENV_CONSDEV                                                      \
 695         "netdev=eth0\0"                                                 \
 696         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 697                 "nfsroot=$serverip:$rootpath\0"                         \
 698         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 699         "addip=setenv bootargs $bootargs "                              \
 700                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 701                 ":$hostname:$netdev:off panic=1\0"                      \
 702         "addcons=setenv bootargs $bootargs "                            \
 703                 "console=$consdev,$baudrate\0"                          \
 704         "flash_nfs=run nfsargs addip addcons;"                          \
 705                 "bootm $kernel_addr - $fdt_addr\0"                      \
 706         "flash_self=run ramargs addip addcons;"                         \
 707                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 708         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 709                 "tftp $fdt_addr_r $fdt_file;"                           \
 710                 "run nfsargs addip addcons;"                            \
 711                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 712         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 713         "fdt_addr_r=900000\0"                                           \
 714         "kernel_addr_r=1000000\0"                                       \
 715         "fdt_addr=ffec0000\0"                                           \
 716         "kernel_addr=ffd00000\0"                                        \
 717         "ramdisk_addr=ff800000\0"                                       \
 718         CONFIG_ENV_UBOOT                                                        \
 719         "load=tftp 100000 $uboot\0"                                     \
 720         "update=protect off $uboot_addr +$filesize;"                    \
 721                 "erase $uboot_addr +$filesize;"                         \
 722                 "cp.b 100000 $uboot_addr $filesize;"                    \
 723                 "setenv filesize;saveenv\0"                             \
 724         "upd=run load update\0"                                         \
 725         ""
 726 #define CONFIG_BOOTCOMMAND      "run flash_self"
 727
 728 #endif /* __CONFIG_H */