include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  46 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  47 #ifdef CONFIG_TQM8548
  48 #define CONFIG_PCI1
  49 #define CONFIG_PCIE1
  50 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  51 #endif
  52
  53 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  54
  55 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  56
  57  /*
  58  * Configuration for big NOR Flashes
  59  *
  60  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  61  * Please be aware, that this changes the whole memory map (new CCSRBAR
  62  * address, etc). You have to use an adapted Linux kernel or FDT blob
  63  * if this option is set.
  64  */
  65 #undef CONFIG_TQM_BIGFLASH
  66
  67 /*
  68  * NAND flash support (disabled by default)
  69  *
  70  * Warning: NAND support will likely increase the U-Boot image size
  71  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  72  */
  73 #undef CONFIG_NAND
  74
  75 /*
  76  * MPC8540 and MPC8548 don't have CPM module
  77  */
  78 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  79 #define CONFIG_CPM2             1       /* has CPM2                     */
  80 #endif
  81
  82 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  83
  84 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support           */
  85
  86 /*
  87  * sysclk for MPC85xx
  88  *
  89  * Two valid values are:
  90  *    33333333
  91  *    66666666
  92  *
  93  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  94  * is likely the desired value here, so that is now the default.
  95  * The board, however, can run at 66MHz.  In any event, this value
  96  * must match the settings of some switches.  Details can be found
  97  * in the README.mpc85xxads.
  98  */
  99
 100 #ifndef CONFIG_SYS_CLK_FREQ
 101 #define CONFIG_SYS_CLK_FREQ     33333333
 102 #endif
 103
 104 /*
 105  * These can be toggled for performance analysis, otherwise use default.
 106  */
 107 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 108 #define CONFIG_BTB                      /* toggle branch predition      */
 109 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming        */
 110
 111 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
 112
 113 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
 114 #define CONFIG_SYS_MEMTEST_START        0x00000000
 115 #define CONFIG_SYS_MEMTEST_END          0x10000000
 116
 117 /*
 118  * Base addresses -- Note these are effective addresses where the
 119  * actual resources get mapped (not physical addresses)
 120  */
 121 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xFF700000      /* CCSRBAR Default      */
 122 #ifdef CONFIG_TQM_BIGFLASH
 123 #define CONFIG_SYS_CCSRBAR              0xA0000000      /* relocated CCSRBAR    */
 124 #else /* !CONFIG_TQM_BIGFLASH */
 125 #define CONFIG_SYS_CCSRBAR              0xE0000000      /* relocated CCSRBAR    */
 126 #endif /* CONFIG_TQM_BIGFLASH */
 127 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 128 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
 129
 130 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR + 0x8000)
 131 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR + 0x9000)
 132 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR + 0xa000)
 133
 134 /*
 135  * DDR Setup
 136  */
 137 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 138 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 139
 140 #define CONFIG_NUM_DDR_CONTROLLERS      1
 141 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 142 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 143
 144 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 145 /* TQM8540 & 8560 need DLL-override */
 146 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 147 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 148 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 149
 150 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 151     defined(CONFIG_TQM8548)
 152 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 153 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 154
 155 /*
 156  * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 157  * series while new boards have 'N' type Flashes from the S29GLxxxN
 158  * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 159  */
 160 #ifdef CONFIG_TQM8548
 161 #define CONFIG_TQM_FLASH_N_TYPE
 162 #endif /* CONFIG_TQM8548 */
 163
 164 /*
 165  * Flash on the Local Bus
 166  */
 167 #ifdef CONFIG_TQM_BIGFLASH
 168 #define CONFIG_SYS_FLASH0               0xE0000000
 169 #define CONFIG_SYS_FLASH1               0xC0000000
 170 #else /* !CONFIG_TQM_BIGFLASH */
 171 #define CONFIG_SYS_FLASH0               0xFC000000
 172 #define CONFIG_SYS_FLASH1               0xF8000000
 173 #endif /* CONFIG_TQM_BIGFLASH */
 174 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 175
 176 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
 177 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH    */
 178
 179 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 180  *
 181  * Note: According to timing specifications external addr latch delay
 182  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 183  *
 184  * For other Local Bus Clocks see following table:
 185  *
 186  * Clock/MHz   CONFIG_SYS_ORx_PRELIM
 187  * 166         0x.....CA5
 188  * 133         0x.....C85
 189  * 100         0x.....C65
 190  *  83         0x.....FA2
 191  *  66         0x.....C82
 192  *  50         0x.....C60
 193  *  42         0x.....040
 194  *  33         0x.....030
 195  *  25         0x.....020
 196  *
 197  */
 198 #ifdef CONFIG_TQM_BIGFLASH
 199 #define CONFIG_SYS_BR0_PRELIM           0xE0001801      /* port size 32bit      */
 200 #define CONFIG_SYS_OR0_PRELIM           0xE0000040      /* 512MB Flash          */
 201 #define CONFIG_SYS_BR1_PRELIM           0xC0001801      /* port size 32bit      */
 202 #define CONFIG_SYS_OR1_PRELIM           0xE0000040      /* 512MB Flash          */
 203 #else /* !CONFIG_TQM_BIGFLASH */
 204 #define CONFIG_SYS_BR0_PRELIM           0xfc001801      /* port size 32bit      */
 205 #define CONFIG_SYS_OR0_PRELIM           0xfc000040      /* 64MB Flash           */
 206 #define CONFIG_SYS_BR1_PRELIM           0xf8001801      /* port size 32bit      */
 207 #define CONFIG_SYS_OR1_PRELIM           0xfc000040      /* 64MB Flash           */
 208 #endif /* CONFIG_TQM_BIGFLASH */
 209
 210 #define CONFIG_SYS_FLASH_CFI                    /* flash is CFI compat.         */
 211 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 212 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 213 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 214 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1 /* speed up output to Flash   */
 215
 216 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks              */
 217 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device           */
 218 #undef  CONFIG_SYS_FLASH_CHECKSUM
 219 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 220 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 221
 222 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor     */
 223
 224 /*
 225  * Note: when changing the Local Bus clock divider you have to
 226  * change the timing values in CONFIG_SYS_ORx_PRELIM.
 227  *
 228  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 229  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 230  *                     for Local Bus Clock > 83.3 MHz.
 231  */
 232 #define CONFIG_SYS_LBC_LCRR             0x00030008      /* LB clock ratio reg   */
 233 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg        */
 234 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 235 #define CONFIG_SYS_LBC_MRTPR            0x20000000      /* LB refresh timer presc.*/
 236
 237 #define CONFIG_SYS_INIT_RAM_LOCK        1
 238 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_CCSRBAR \
 239                                  + 0x04010000)  /* Initial RAM address  */
 240 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End used area in RAM */
 241
 242 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data       */
 243 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 244 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 245
 246 #define CONFIG_SYS_MONITOR_LEN          (~TEXT_BASE + 1)/* Reserved for Monitor */
 247 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)    /* Reserved for malloc  */
 248
 249 /* Serial Port */
 250 #if defined(CONFIG_TQM8560)
 251
 252 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 253 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 254 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 255
 256 #else /* !CONFIG_TQM8560 */
 257
 258 #define CONFIG_CONS_INDEX     1
 259 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 260 #define CONFIG_SYS_NS16550
 261 #define CONFIG_SYS_NS16550_SERIAL
 262 #define CONFIG_SYS_NS16550_REG_SIZE     1
 263 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 264
 265 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 266 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 267
 268 /* PS/2 Keyboard */
 269 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 270 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 271 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 272 #define CONFIG_PS2MULT_DELAY    (CONFIG_SYS_HZ/2)       /* Initial delay        */
 273 #define CONFIG_BOARD_EARLY_INIT_R       1
 274
 275 #endif /* CONFIG_TQM8560 */
 276
 277 #define CONFIG_BAUDRATE         115200
 278
 279 #define CONFIG_SYS_BAUDRATE_TABLE       \
 280         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 281
 282 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 283 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 284 #ifdef  CONFIG_SYS_HUSH_PARSER
 285 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 286 #endif
 287
 288 /* pass open firmware flat tree */
 289 #define CONFIG_OF_LIBFDT                1
 290 #define CONFIG_OF_BOARD_SETUP           1
 291 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 292
 293 /* CAN */
 294 #define CONFIG_SYS_CAN_BASE             (CONFIG_SYS_CCSRBAR \
 295                                  + 0x03000000)  /* CAN base address     */
 296 #ifdef CONFIG_CAN_DRIVER
 297 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 KiB address mask  */
 298 #define CONFIG_SYS_OR2_CAN              (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
 299 #define CONFIG_SYS_BR2_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA) | \
 300                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 301 #endif /* CONFIG_CAN_DRIVER */
 302
 303 /*
 304  * I2C
 305  */
 306 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 307 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 308 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 309 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 310 #define CONFIG_SYS_I2C_SLAVE            0x7F
 311 #define CONFIG_SYS_I2C_NOPROBES {0x48}  /* Don't probe these addrs      */
 312 #define CONFIG_SYS_I2C_OFFSET           0x3000
 313
 314 /* I2C RTC */
 315 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 316 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 317
 318 /* I2C EEPROM */
 319 /*
 320  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 321  */
 322 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x             */
 323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 324 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 326 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 327
 328 /* I2C SYSMON (LM75) */
 329 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 330 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 331 #define CONFIG_SYS_DTT_MAX_TEMP 70
 332 #define CONFIG_SYS_DTT_LOW_TEMP -30
 333 #define CONFIG_SYS_DTT_HYSTERESIS       3
 334
 335 #ifndef CONFIG_PCIE1
 336 /* RapidIO MMU */
 337 #ifdef CONFIG_TQM_BIGFLASH
 338 #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000      /* base address         */
 339 #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000      /* 256M                 */
 340 #else /* !CONFIG_TQM_BIGFLASH */
 341 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address         */
 342 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M                 */
 343 #endif /* CONFIG_TQM_BIGFLASH */
 344 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 345 #endif /* CONFIG_PCIE1 */
 346
 347 /* NAND FLASH */
 348 #ifdef CONFIG_NAND
 349
 350 #undef CONFIG_NAND_LEGACY
 351
 352 #define CONFIG_NAND_FSL_UPM     1
 353
 354 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 355
 356 /* address distance between chip selects */
 357 #define CONFIG_SYS_NAND_SELECT_DEVICE   1
 358 #define CONFIG_SYS_NAND_CS_DIST 0x200
 359
 360 #define CONFIG_SYS_NAND_SIZE            0x8000
 361 #define CONFIG_SYS_NAND0_BASE           (CONFIG_SYS_CCSRBAR + 0x03010000)
 362 #define CONFIG_SYS_NAND1_BASE           (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 363 #define CONFIG_SYS_NAND2_BASE           (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 364 #define CONFIG_SYS_NAND3_BASE           (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 365
 366 #define CONFIG_SYS_MAX_NAND_DEVICE     2        /* Max number of NAND devices   */
 367 #define NAND_MAX_CHIPS          1
 368
 369 #if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
 370 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
 371 #elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
 372 #define CONFIG_SYS_NAND_QUIET_TEST      1
 373 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 374                              CONFIG_SYS_NAND1_BASE, \
 375 }
 376 #elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
 377 #define CONFIG_SYS_NAND_QUIET_TEST      1
 378 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 379                              CONFIG_SYS_NAND1_BASE, \
 380                              CONFIG_SYS_NAND2_BASE, \
 381                              CONFIG_SYS_NAND3_BASE, \
 382 }
 383 #endif
 384
 385 /* CS3 for NAND Flash */
 386 #define CONFIG_SYS_BR3_PRELIM           ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
 387                                  BR_MS_UPMB | BR_V)
 388 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 389
 390 #define NAND_BIG_DELAY_US       25      /* max tR for Samsung devices   */
 391
 392 #endif /* CONFIG_NAND */
 393
 394 /*
 395  * General PCI
 396  * Addresses are mapped 1-1.
 397  */
 398 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 399 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 400 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 401 #define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
 402 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 403 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /*  16M                 */
 404
 405 #ifdef CONFIG_PCIE1
 406 /*
 407  * General PCI express
 408  * Addresses are mapped 1-1.
 409  */
 410 #ifdef CONFIG_TQM_BIGFLASH
 411 #define CONFIG_SYS_PCIE1_MEM_BASE       0xb0000000
 412 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 512M                 */
 413 #define CONFIG_SYS_PCIE1_IO_BASE        0xaf000000
 414 #else /* !CONFIG_TQM_BIGFLASH */
 415 #define CONFIG_SYS_PCIE1_MEM_BASE       0xc0000000
 416 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M                 */
 417 #define CONFIG_SYS_PCIE1_IO_BASE        0xef000000
 418 #endif /* CONFIG_TQM_BIGFLASH */
 419 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 420 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BASE
 421 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M                  */
 422 #endif /* CONFIG_PCIE1 */
 423
 424 #if defined(CONFIG_PCI)
 425
 426 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 427
 428 #define CONFIG_EEPRO100
 429 #undef CONFIG_TULIP
 430
 431 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 432 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola                     */
 433
 434 #endif /* CONFIG_PCI */
 435
 436 #define CONFIG_NET_MULTI        1
 437
 438 #define CONFIG_MII              1       /* MII PHY management           */
 439 #define CONFIG_TSEC1    1
 440 #define CONFIG_TSEC1_NAME       "TSEC0"
 441 #define CONFIG_TSEC2    1
 442 #define CONFIG_TSEC2_NAME       "TSEC1"
 443 #define TSEC1_PHY_ADDR          2
 444 #define TSEC2_PHY_ADDR          1
 445 #define TSEC1_PHYIDX            0
 446 #define TSEC2_PHYIDX            0
 447 #define TSEC1_FLAGS             TSEC_GIGABIT
 448 #define TSEC2_FLAGS             TSEC_GIGABIT
 449 #define FEC_PHY_ADDR            3
 450 #define FEC_PHYIDX              0
 451 #define FEC_FLAGS               0
 452 #define CONFIG_HAS_ETH0
 453 #define CONFIG_HAS_ETH1
 454 #define CONFIG_HAS_ETH2
 455
 456 #ifdef CONFIG_TQM8548
 457 /*
 458  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 459  *
 460  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 461  * additional adapter (AIO) between module and Starterkit.
 462  */
 463 #define CONFIG_TSEC3    1
 464 #define CONFIG_TSEC3_NAME       "TSEC2"
 465 #define CONFIG_TSEC4    1
 466 #define CONFIG_TSEC4_NAME       "TSEC3"
 467 #define TSEC3_PHY_ADDR          4
 468 #define TSEC4_PHY_ADDR          5
 469 #define TSEC3_PHYIDX            0
 470 #define TSEC4_PHYIDX            0
 471 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 472 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 473 #define CONFIG_HAS_ETH3
 474 #define CONFIG_HAS_ETH4
 475 #endif  /* CONFIG_TQM8548 */
 476
 477 /* Options are TSEC[0-1], FEC */
 478 #define CONFIG_ETHPRIME         "TSEC0"
 479
 480 #if defined(CONFIG_TQM8540)
 481 /*
 482  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 483  * The FEC port is connected on the same signals as the FCC3 port
 484  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 485  *
 486  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 487  * a - d (X50.2 - 3) to enable the FEC port.
 488  */
 489 #define CONFIG_MPC85XX_FEC      1
 490 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 491 #endif
 492
 493 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 494 /*
 495  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 496  * can be used at once, since only one FCC port is available on the STK85xx
 497  * Starterkit.
 498  *
 499  * To use this port you have to configure U-Boot to use the FCC port 1...2
 500  * and set the X47/X50 jumper to:
 501  * FCC1: a - b (X47.2 - X50.2)
 502  * FCC2: a - c (X50.2 - 1)
 503  */
 504 #define CONFIG_ETHER_ON_FCC
 505 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 506 #endif
 507
 508 #if defined(CONFIG_TQM8560)
 509 /*
 510  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 511  * can be used at once, since only one FCC port is available on the STK85xx
 512  * Starterkit.
 513  *
 514  * To use this port you have to configure U-Boot to use the FCC port 1...3
 515  * and set the X47/X50 jumper to:
 516  * FCC1: a - b (X47.2 - X50.2)
 517  * FCC2: a - c (X50.2 - 1)
 518  * FCC3: a - d (X50.2 - 3)
 519  */
 520 #define CONFIG_ETHER_ON_FCC
 521 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 522 #endif
 523
 524 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 525 #define CONFIG_ETHER_ON_FCC1
 526 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 527                                  CMXFCR_TF1CS_MSK)
 528 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 529 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 530 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 531 #endif
 532
 533 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 534 #define CONFIG_ETHER_ON_FCC2
 535 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 536                                  CMXFCR_TF2CS_MSK)
 537 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 538 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 539 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 540 #endif
 541
 542 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 543 #define CONFIG_ETHER_ON_FCC3
 544 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 545                                  CMXFCR_TF3CS_MSK)
 546 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 547 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 548 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 549 #endif
 550
 551 /*
 552  * Environment
 553  */
 554 #define CONFIG_ENV_IS_IN_FLASH  1
 555
 556 #ifdef CONFIG_TQM_FLASH_N_TYPE
 557 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K (one sector) for env    */
 558 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 559 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env    */
 560 #endif /* CONFIG_TQM_FLASH_N_TYPE */
 561 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 562 #define CONFIG_ENV_SIZE         0x2000
 563 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 564 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 565
 566 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 568
 569 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 570
 571 /*
 572  * BOOTP options
 573  */
 574 #define CONFIG_BOOTP_BOOTFILESIZE
 575 #define CONFIG_BOOTP_BOOTPATH
 576 #define CONFIG_BOOTP_GATEWAY
 577 #define CONFIG_BOOTP_HOSTNAME
 578
 579 #ifdef CONFIG_NAND
 580 /*
 581  * Use NAND-FLash as JFFS2 device
 582  */
 583 #define CONFIG_CMD_NAND
 584 #define CONFIG_CMD_JFFS2
 585
 586 #define CONFIG_JFFS2_NAND       1
 587
 588 #ifdef CONFIG_JFFS2_CMDLINE
 589 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 590 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 591 #else
 592 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 593 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 594 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 595 #endif /* CONFIG_JFFS2_CMDLINE */
 596
 597 #endif /* CONFIG_NAND */
 598
 599 /*
 600  * Command line configuration.
 601  */
 602 #include <config_cmd_default.h>
 603
 604 #define CONFIG_CMD_PING
 605 #define CONFIG_CMD_I2C
 606 #define CONFIG_CMD_DHCP
 607 #define CONFIG_CMD_NFS
 608 #define CONFIG_CMD_SNTP
 609 #define CONFIG_CMD_DATE
 610 #define CONFIG_CMD_EEPROM
 611 #define CONFIG_CMD_DTT
 612 #define CONFIG_CMD_MII
 613
 614 #if defined(CONFIG_PCI)
 615 #define CONFIG_CMD_PCI
 616 #endif
 617
 618 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 619
 620 /*
 621  * Miscellaneous configurable options
 622  */
 623 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 624 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
 625 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 626
 627 #if defined(CONFIG_CMD_KGDB)
 628 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 629 #else
 630 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 631 #endif
 632
 633 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 634                          sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size    */
 635 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 636 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 637 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks  */
 638
 639 /*
 640  * For booting Linux, the board info and command line data
 641  * have to be in the first 8 MB of memory, since this is
 642  * the maximum mapped by the Linux kernel during initialization.
 643  */
 644 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 645
 646 /*
 647  * Internal Definitions
 648  *
 649  * Boot Flags
 650  */
 651 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 652 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 653
 654 #if defined(CONFIG_CMD_KGDB)
 655 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 656 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 657 #endif
 658
 659 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 660
 661 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 662
 663 #define CONFIG_PREBOOT  "echo;" \
 664         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 665         "echo"
 666
 667 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 668
 669
 670 /*
 671  * Setup some board specific values for the default environment variables
 672  */
 673 #ifdef CONFIG_CPM2
 674 #define CONFIG_ENV_CONSDEV              "consdev=ttyCPM0\0"
 675 #else
 676 #define CONFIG_ENV_CONSDEV              "consdev=ttyS0\0"
 677 #endif
 678 #define CONFIG_ENV_FDT_FILE     "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 679                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 680 #define CONFIG_ENV_BOOTFILE     "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 681 #define CONFIG_ENV_UBOOT                "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 682                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 683
 684 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 685         CONFIG_ENV_BOOTFILE                                             \
 686         CONFIG_ENV_FDT_FILE                                             \
 687         CONFIG_ENV_CONSDEV                                                      \
 688         "netdev=eth0\0"                                                 \
 689         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 690                 "nfsroot=$serverip:$rootpath\0"                         \
 691         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 692         "addip=setenv bootargs $bootargs "                              \
 693                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 694                 ":$hostname:$netdev:off panic=1\0"                      \
 695         "addcons=setenv bootargs $bootargs "                            \
 696                 "console=$consdev,$baudrate\0"                          \
 697         "flash_nfs=run nfsargs addip addcons;"                          \
 698                 "bootm $kernel_addr - $fdt_addr\0"                      \
 699         "flash_self=run ramargs addip addcons;"                         \
 700                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 701         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 702                 "tftp $fdt_addr_r $fdt_file;"                           \
 703                 "run nfsargs addip addcons;"                            \
 704                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 705         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 706         "fdt_addr_r=900000\0"                                           \
 707         "kernel_addr_r=1000000\0"                                       \
 708         "fdt_addr=ffec0000\0"                                           \
 709         "kernel_addr=ffd00000\0"                                        \
 710         "ramdisk_addr=ff800000\0"                                       \
 711         CONFIG_ENV_UBOOT                                                        \
 712         "load=tftp 100000 $uboot\0"                                     \
 713         "update=protect off $uboot_addr +$filesize;"                    \
 714                 "erase $uboot_addr +$filesize;"                         \
 715                 "cp.b 100000 $uboot_addr $filesize;"                    \
 716                 "setenv filesize;saveenv\0"                             \
 717         "upd=run load update\0"                                         \
 718         ""
 719 #define CONFIG_BOOTCOMMAND      "run flash_self"
 720
 721 #endif /* __CONFIG_H */