include/configs/TQM860M.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  21 #define CONFIG_TQM860M          1       /* ...on a TQM8xxM module       */
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 #define CONFIG_SYS_TEXT_BASE    0x40000000
  25
  26 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  27 #define CONFIG_SYS_SMC_RXBUFLEN 128
  28 #define CONFIG_SYS_MAXIDLE      10
  29 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  30
  31 #define CONFIG_BOOTCOUNT_LIMIT
  32
  33 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  34
  35 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  36
  37 #define CONFIG_PREBOOT  "echo;" \
  38         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  39         "echo"
  40
  41 #undef  CONFIG_BOOTARGS
  42
  43 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  44         "netdev=eth0\0"                                                 \
  45         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  46                 "nfsroot=${serverip}:${rootpath}\0"                     \
  47         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  48         "addip=setenv bootargs ${bootargs} "                            \
  49                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  50                 ":${hostname}:${netdev}:off panic=1\0"                  \
  51         "flash_nfs=run nfsargs addip;"                                  \
  52                 "bootm ${kernel_addr}\0"                                \
  53         "flash_self=run ramargs addip;"                                 \
  54                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  55         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  56         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  57         "hostname=TQM860M\0"                                            \
  58         "bootfile=TQM860M/uImage\0"                                     \
  59         "fdt_addr=400C0000\0"                                           \
  60         "kernel_addr=40100000\0"                                        \
  61         "ramdisk_addr=40280000\0"                                       \
  62         "u-boot=TQM860M/u-image.bin\0"                                  \
  63         "load=tftp 200000 ${u-boot}\0"                                  \
  64         "update=prot off 40000000 +${filesize};"                        \
  65                 "era 40000000 +${filesize};"                            \
  66                 "cp.b 200000 40000000 ${filesize};"                     \
  67                 "sete filesize;save\0"                                  \
  68         ""
  69 #define CONFIG_BOOTCOMMAND      "run flash_self"
  70
  71 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  72 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  73
  74 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  75
  76 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  77
  78 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_SUBNETMASK
  84 #define CONFIG_BOOTP_GATEWAY
  85 #define CONFIG_BOOTP_HOSTNAME
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88
  89 #define CONFIG_MAC_PARTITION
  90 #define CONFIG_DOS_PARTITION
  91
  92 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  93
  94 /*
  95  * Command line configuration.
  96  */
  97 #define CONFIG_CMD_DATE
  98 #define CONFIG_CMD_IDE
  99 #define CONFIG_CMD_JFFS2
 100
 101 #define CONFIG_NETCONSOLE
 102
 103 /*
 104  * Miscellaneous configurable options
 105  */
 106 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 107
 108 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 109
 110 #if defined(CONFIG_CMD_KGDB)
 111 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 112 #else
 113 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 114 #endif
 115 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 116 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 117 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 118
 119 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 120 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 121
 122 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 123
 124 /*
 125  * Low Level Configuration Settings
 126  * (address mappings, register initial values, etc.)
 127  * You should know what you are doing if you make changes here.
 128  */
 129 /*-----------------------------------------------------------------------
 130  * Internal Memory Mapped Register
 131  */
 132 #define CONFIG_SYS_IMMR         0xFFF00000
 133
 134 /*-----------------------------------------------------------------------
 135  * Definitions for initial stack pointer and data area (in DPRAM)
 136  */
 137 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 138 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 /*-----------------------------------------------------------------------
 143  * Start addresses for the final memory configuration
 144  * (Set up by the startup code)
 145  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 146  */
 147 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 148 #define CONFIG_SYS_FLASH_BASE           0x40000000
 149 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 151 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 152
 153 /*
 154  * For booting Linux, the board info and command line data
 155  * have to be in the first 8 MB of memory, since this is
 156  * the maximum mapped by the Linux kernel during initialization.
 157  */
 158 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 159
 160 /*-----------------------------------------------------------------------
 161  * FLASH organization
 162  */
 163 /* use CFI flash driver */
 164 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 165 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 166 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 167 #define CONFIG_SYS_FLASH_EMPTY_INFO
 168 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 169 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 170 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 171
 172 #define CONFIG_ENV_IS_IN_FLASH  1
 173 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 174 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment Sector     */
 175 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 176
 177 /* Address and size of Redundant Environment Sector     */
 178 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 179 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 180
 181 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 182
 183 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 184
 185 /*-----------------------------------------------------------------------
 186  * Dynamic MTD partition support
 187  */
 188 #define CONFIG_CMD_MTDPARTS
 189 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 190 #define CONFIG_FLASH_CFI_MTD
 191 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 192
 193 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 194                                                 "128k(dtb),"            \
 195                                                 "1920k(kernel),"        \
 196                                                 "5632(rootfs),"         \
 197                                                 "4m(data)"
 198
 199 /*-----------------------------------------------------------------------
 200  * Hardware Information Block
 201  */
 202 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 203 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 204 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 205
 206 /*-----------------------------------------------------------------------
 207  * Cache Configuration
 208  */
 209 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 210 #if defined(CONFIG_CMD_KGDB)
 211 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 212 #endif
 213
 214 /*-----------------------------------------------------------------------
 215  * SYPCR - System Protection Control                            11-9
 216  * SYPCR can only be written once after reset!
 217  *-----------------------------------------------------------------------
 218  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 219  */
 220 #if defined(CONFIG_WATCHDOG)
 221 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 222                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 223 #else
 224 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SIUMCR - SIU Module Configuration                            11-6
 229  *-----------------------------------------------------------------------
 230  * PCMCIA config., multi-function pin tri-state
 231  */
 232 #ifndef CONFIG_CAN_DRIVER
 233 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 234 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 235 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 236 #endif  /* CONFIG_CAN_DRIVER */
 237
 238 /*-----------------------------------------------------------------------
 239  * TBSCR - Time Base Status and Control                         11-26
 240  *-----------------------------------------------------------------------
 241  * Clear Reference Interrupt Status, Timebase freezing enabled
 242  */
 243 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 244
 245 /*-----------------------------------------------------------------------
 246  * RTCSC - Real-Time Clock Status and Control Register          11-27
 247  *-----------------------------------------------------------------------
 248  */
 249 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 250
 251 /*-----------------------------------------------------------------------
 252  * PISCR - Periodic Interrupt Status and Control                11-31
 253  *-----------------------------------------------------------------------
 254  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 255  */
 256 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 257
 258 /*-----------------------------------------------------------------------
 259  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 260  *-----------------------------------------------------------------------
 261  * Reset PLL lock status sticky bit, timer expired status bit and timer
 262  * interrupt status bit
 263  */
 264 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 265
 266 /*-----------------------------------------------------------------------
 267  * SCCR - System Clock and reset Control Register               15-27
 268  *-----------------------------------------------------------------------
 269  * Set clock output, timebase and RTC source and divider,
 270  * power management and some other internal clocks
 271  */
 272 #define SCCR_MASK       SCCR_EBDF11
 273 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 274                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 275                          SCCR_DFALCD00)
 276
 277 /*-----------------------------------------------------------------------
 278  * PCMCIA stuff
 279  *-----------------------------------------------------------------------
 280  *
 281  */
 282 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 283 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 284 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 285 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 286 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 287 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 288 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 289 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 290
 291 /*-----------------------------------------------------------------------
 292  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 293  *-----------------------------------------------------------------------
 294  */
 295
 296 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 297 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 298
 299 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 300 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 301 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 302
 303 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 304 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 305
 306 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 307
 308 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 309
 310 /* Offset for data I/O                  */
 311 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 312
 313 /* Offset for normal register accesses  */
 314 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 315
 316 /* Offset for alternate registers       */
 317 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 318
 319 /*-----------------------------------------------------------------------
 320  *
 321  *-----------------------------------------------------------------------
 322  *
 323  */
 324 #define CONFIG_SYS_DER  0
 325
 326 /*
 327  * Init Memory Controller:
 328  *
 329  * BR0/1 and OR0/1 (FLASH)
 330  */
 331
 332 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 333 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 334
 335 /* used to re-map FLASH both when starting from SRAM or FLASH:
 336  * restrict access enough to keep SRAM working (if any)
 337  * but not too much to meddle with FLASH accesses
 338  */
 339 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 340 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 341
 342 /*
 343  * FLASH timing:
 344  */
 345 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 346                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 347
 348 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 349 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 350 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 351
 352 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 353 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 354 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 355
 356 /*
 357  * BR2/3 and OR2/3 (SDRAM)
 358  *
 359  */
 360 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 361 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 362 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB per bank  */
 363
 364 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 365 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 366
 367 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 368 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 369
 370 #ifndef CONFIG_CAN_DRIVER
 371 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 372 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 373 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 374 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 375 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 376 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 377 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 378                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 379 #endif  /* CONFIG_CAN_DRIVER */
 380
 381 /*
 382  * Memory Periodic Timer Prescaler
 383  *
 384  * The Divider for PTA (refresh timer) configuration is based on an
 385  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 386  * the number of chip selects (NCS) and the actually needed refresh
 387  * rate is done by setting MPTPR.
 388  *
 389  * PTA is calculated from
 390  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 391  *
 392  *      gclk      CPU clock (not bus clock!)
 393  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 394  *
 395  * 4096  Rows from SDRAM example configuration
 396  * 1000  factor s -> ms
 397  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 398  *    4  Number of refresh cycles per period
 399  *   64  Refresh cycle in ms per number of rows
 400  * --------------------------------------------
 401  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 402  *
 403  * 50 MHz => 50.000.000 / Divider =  98
 404  * 66 Mhz => 66.000.000 / Divider = 129
 405  * 80 Mhz => 80.000.000 / Divider = 156
 406  */
 407
 408 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 409 #define CONFIG_SYS_MAMR_PTA     98
 410
 411 /*
 412  * For 16 MBit, refresh rates could be 31.3 us
 413  * (= 64 ms / 2K = 125 / quad bursts).
 414  * For a simpler initialization, 15.6 us is used instead.
 415  *
 416  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 417  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 418  */
 419 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 420 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 421
 422 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 423 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 424 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 425
 426 /*
 427  * MAMR settings for SDRAM
 428  */
 429
 430 /* 8 column SDRAM */
 431 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 432                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 433                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 434 /* 9 column SDRAM */
 435 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 436                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 437                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 438 /* 10 column SDRAM */
 439 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 440                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 441                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 442
 443 #define CONFIG_SCC1_ENET
 444 #define CONFIG_FEC_ENET
 445 #define CONFIG_ETHPRIME         "SCC"
 446
 447 #define CONFIG_HWCONFIG         1
 448
 449 #endif  /* __CONFIG_H */