include/configs/TQM860M.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  21 #define CONFIG_TQM860M          1       /* ...on a TQM8xxM module       */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  26 #define CONFIG_SYS_SMC_RXBUFLEN 128
  27 #define CONFIG_SYS_MAXIDLE      10
  28 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  29
  30 #define CONFIG_BOOTCOUNT_LIMIT
  31
  32 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  33
  34 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  35
  36 #define CONFIG_PREBOOT  "echo;" \
  37         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  38         "echo"
  39
  40 #undef  CONFIG_BOOTARGS
  41
  42 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  43         "netdev=eth0\0"                                                 \
  44         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  45                 "nfsroot=${serverip}:${rootpath}\0"                     \
  46         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  47         "addip=setenv bootargs ${bootargs} "                            \
  48                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  49                 ":${hostname}:${netdev}:off panic=1\0"                  \
  50         "flash_nfs=run nfsargs addip;"                                  \
  51                 "bootm ${kernel_addr}\0"                                \
  52         "flash_self=run ramargs addip;"                                 \
  53                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  54         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  55         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  56         "hostname=TQM860M\0"                                            \
  57         "bootfile=TQM860M/uImage\0"                                     \
  58         "fdt_addr=400C0000\0"                                           \
  59         "kernel_addr=40100000\0"                                        \
  60         "ramdisk_addr=40280000\0"                                       \
  61         "u-boot=TQM860M/u-image.bin\0"                                  \
  62         "load=tftp 200000 ${u-boot}\0"                                  \
  63         "update=prot off 40000000 +${filesize};"                        \
  64                 "era 40000000 +${filesize};"                            \
  65                 "cp.b 200000 40000000 ${filesize};"                     \
  66                 "sete filesize;save\0"                                  \
  67         ""
  68 #define CONFIG_BOOTCOMMAND      "run flash_self"
  69
  70 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  71 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  72
  73 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  74
  75 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  76
  77 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  78
  79 /*
  80  * BOOTP options
  81  */
  82 #define CONFIG_BOOTP_SUBNETMASK
  83 #define CONFIG_BOOTP_GATEWAY
  84 #define CONFIG_BOOTP_HOSTNAME
  85 #define CONFIG_BOOTP_BOOTPATH
  86 #define CONFIG_BOOTP_BOOTFILESIZE
  87
  88
  89 #define CONFIG_MAC_PARTITION
  90 #define CONFIG_DOS_PARTITION
  91
  92 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  93
  94
  95 /*
  96  * Command line configuration.
  97  */
  98 #include <config_cmd_default.h>
  99
 100 #define CONFIG_CMD_ASKENV
 101 #define CONFIG_CMD_DATE
 102 #define CONFIG_CMD_DHCP
 103 #define CONFIG_CMD_ELF
 104 #define CONFIG_CMD_EXT2
 105 #define CONFIG_CMD_IDE
 106 #define CONFIG_CMD_JFFS2
 107 #define CONFIG_CMD_NFS
 108 #define CONFIG_CMD_SNTP
 109
 110
 111 #define CONFIG_NETCONSOLE
 112
 113
 114 /*
 115  * Miscellaneous configurable options
 116  */
 117 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 118 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 119
 120 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 121 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 122
 123 #if defined(CONFIG_CMD_KGDB)
 124 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 125 #else
 126 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 127 #endif
 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 129 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 130 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 131
 132 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 133 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 134
 135 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 136
 137 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 138
 139 /*
 140  * Low Level Configuration Settings
 141  * (address mappings, register initial values, etc.)
 142  * You should know what you are doing if you make changes here.
 143  */
 144 /*-----------------------------------------------------------------------
 145  * Internal Memory Mapped Register
 146  */
 147 #define CONFIG_SYS_IMMR         0xFFF00000
 148
 149 /*-----------------------------------------------------------------------
 150  * Definitions for initial stack pointer and data area (in DPRAM)
 151  */
 152 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 153 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 154 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 155 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 156
 157 /*-----------------------------------------------------------------------
 158  * Start addresses for the final memory configuration
 159  * (Set up by the startup code)
 160  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 161  */
 162 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 163 #define CONFIG_SYS_FLASH_BASE           0x40000000
 164 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 166 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 167
 168 /*
 169  * For booting Linux, the board info and command line data
 170  * have to be in the first 8 MB of memory, since this is
 171  * the maximum mapped by the Linux kernel during initialization.
 172  */
 173 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 174
 175 /*-----------------------------------------------------------------------
 176  * FLASH organization
 177  */
 178 /* use CFI flash driver */
 179 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 180 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 181 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 182 #define CONFIG_SYS_FLASH_EMPTY_INFO
 183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 185 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 186
 187 #define CONFIG_ENV_IS_IN_FLASH  1
 188 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 189 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment Sector     */
 190 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 191
 192 /* Address and size of Redundant Environment Sector     */
 193 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 194 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 195
 196 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 197
 198 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 199
 200 /*-----------------------------------------------------------------------
 201  * Dynamic MTD partition support
 202  */
 203 #define CONFIG_CMD_MTDPARTS
 204 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 205 #define CONFIG_FLASH_CFI_MTD
 206 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 207
 208 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 209                                                 "128k(dtb),"            \
 210                                                 "1920k(kernel),"        \
 211                                                 "5632(rootfs),"         \
 212                                                 "4m(data)"
 213
 214 /*-----------------------------------------------------------------------
 215  * Hardware Information Block
 216  */
 217 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 218 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 219 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 220
 221 /*-----------------------------------------------------------------------
 222  * Cache Configuration
 223  */
 224 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 225 #if defined(CONFIG_CMD_KGDB)
 226 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 227 #endif
 228
 229 /*-----------------------------------------------------------------------
 230  * SYPCR - System Protection Control                            11-9
 231  * SYPCR can only be written once after reset!
 232  *-----------------------------------------------------------------------
 233  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 234  */
 235 #if defined(CONFIG_WATCHDOG)
 236 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 237                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 238 #else
 239 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 240 #endif
 241
 242 /*-----------------------------------------------------------------------
 243  * SIUMCR - SIU Module Configuration                            11-6
 244  *-----------------------------------------------------------------------
 245  * PCMCIA config., multi-function pin tri-state
 246  */
 247 #ifndef CONFIG_CAN_DRIVER
 248 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 249 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 250 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 251 #endif  /* CONFIG_CAN_DRIVER */
 252
 253 /*-----------------------------------------------------------------------
 254  * TBSCR - Time Base Status and Control                         11-26
 255  *-----------------------------------------------------------------------
 256  * Clear Reference Interrupt Status, Timebase freezing enabled
 257  */
 258 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 259
 260 /*-----------------------------------------------------------------------
 261  * RTCSC - Real-Time Clock Status and Control Register          11-27
 262  *-----------------------------------------------------------------------
 263  */
 264 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 265
 266 /*-----------------------------------------------------------------------
 267  * PISCR - Periodic Interrupt Status and Control                11-31
 268  *-----------------------------------------------------------------------
 269  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 270  */
 271 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 272
 273 /*-----------------------------------------------------------------------
 274  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 275  *-----------------------------------------------------------------------
 276  * Reset PLL lock status sticky bit, timer expired status bit and timer
 277  * interrupt status bit
 278  */
 279 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 280
 281 /*-----------------------------------------------------------------------
 282  * SCCR - System Clock and reset Control Register               15-27
 283  *-----------------------------------------------------------------------
 284  * Set clock output, timebase and RTC source and divider,
 285  * power management and some other internal clocks
 286  */
 287 #define SCCR_MASK       SCCR_EBDF11
 288 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 289                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 290                          SCCR_DFALCD00)
 291
 292 /*-----------------------------------------------------------------------
 293  * PCMCIA stuff
 294  *-----------------------------------------------------------------------
 295  *
 296  */
 297 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 298 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 299 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 300 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 301 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 302 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 303 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 304 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 305
 306 /*-----------------------------------------------------------------------
 307  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 308  *-----------------------------------------------------------------------
 309  */
 310
 311 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 312 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 313
 314 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 315 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 316 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 317
 318 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 319 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 320
 321 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 322
 323 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 324
 325 /* Offset for data I/O                  */
 326 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 327
 328 /* Offset for normal register accesses  */
 329 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 330
 331 /* Offset for alternate registers       */
 332 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 333
 334 /*-----------------------------------------------------------------------
 335  *
 336  *-----------------------------------------------------------------------
 337  *
 338  */
 339 #define CONFIG_SYS_DER  0
 340
 341 /*
 342  * Init Memory Controller:
 343  *
 344  * BR0/1 and OR0/1 (FLASH)
 345  */
 346
 347 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 348 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 349
 350 /* used to re-map FLASH both when starting from SRAM or FLASH:
 351  * restrict access enough to keep SRAM working (if any)
 352  * but not too much to meddle with FLASH accesses
 353  */
 354 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 355 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 356
 357 /*
 358  * FLASH timing:
 359  */
 360 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 361                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 362
 363 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 364 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 365 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 366
 367 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 368 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 369 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 370
 371 /*
 372  * BR2/3 and OR2/3 (SDRAM)
 373  *
 374  */
 375 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 376 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 377 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB per bank  */
 378
 379 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 380 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 381
 382 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 383 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 384
 385 #ifndef CONFIG_CAN_DRIVER
 386 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 387 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 388 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 389 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 390 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 391 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 392 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 393                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 394 #endif  /* CONFIG_CAN_DRIVER */
 395
 396 /*
 397  * Memory Periodic Timer Prescaler
 398  *
 399  * The Divider for PTA (refresh timer) configuration is based on an
 400  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 401  * the number of chip selects (NCS) and the actually needed refresh
 402  * rate is done by setting MPTPR.
 403  *
 404  * PTA is calculated from
 405  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 406  *
 407  *      gclk      CPU clock (not bus clock!)
 408  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 409  *
 410  * 4096  Rows from SDRAM example configuration
 411  * 1000  factor s -> ms
 412  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 413  *    4  Number of refresh cycles per period
 414  *   64  Refresh cycle in ms per number of rows
 415  * --------------------------------------------
 416  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 417  *
 418  * 50 MHz => 50.000.000 / Divider =  98
 419  * 66 Mhz => 66.000.000 / Divider = 129
 420  * 80 Mhz => 80.000.000 / Divider = 156
 421  */
 422
 423 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 424 #define CONFIG_SYS_MAMR_PTA     98
 425
 426 /*
 427  * For 16 MBit, refresh rates could be 31.3 us
 428  * (= 64 ms / 2K = 125 / quad bursts).
 429  * For a simpler initialization, 15.6 us is used instead.
 430  *
 431  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 432  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 433  */
 434 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 435 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 436
 437 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 438 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 439 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 440
 441 /*
 442  * MAMR settings for SDRAM
 443  */
 444
 445 /* 8 column SDRAM */
 446 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 447                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 448                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 449 /* 9 column SDRAM */
 450 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 451                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 452                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 453 /* 10 column SDRAM */
 454 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 455                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 456                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 457
 458 #define CONFIG_SCC1_ENET
 459 #define CONFIG_FEC_ENET
 460 #define CONFIG_ETHPRIME         "SCC"
 461
 462 /* pass open firmware flat tree */
 463 #define CONFIG_OF_LIBFDT        1
 464 #define CONFIG_OF_BOARD_SETUP   1
 465 #define CONFIG_HWCONFIG         1
 466
 467 #endif  /* __CONFIG_H */