include/configs/TQM862M.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1
  21 #define CONFIG_MPC860T          1
  22 #define CONFIG_MPC862           1
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_TQM862M          1       /* ...on a TQM8xxM module       */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0x40000000
  28
  29 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  30 #define CONFIG_SYS_SMC_RXBUFLEN 128
  31 #define CONFIG_SYS_MAXIDLE      10
  32 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  33
  34 #define CONFIG_BOOTCOUNT_LIMIT
  35
  36 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  37
  38 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  39
  40 #define CONFIG_PREBOOT  "echo;" \
  41         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  42         "echo"
  43
  44 #undef  CONFIG_BOOTARGS
  45
  46 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  47         "netdev=eth0\0"                                                 \
  48         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  49                 "nfsroot=${serverip}:${rootpath}\0"                     \
  50         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  51         "addip=setenv bootargs ${bootargs} "                            \
  52                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  53                 ":${hostname}:${netdev}:off panic=1\0"                  \
  54         "flash_nfs=run nfsargs addip;"                                  \
  55                 "bootm ${kernel_addr}\0"                                \
  56         "flash_self=run ramargs addip;"                                 \
  57                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  58         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  59         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  60         "hostname=TQM862M\0"                                            \
  61         "bootfile=TQM862M/uImage\0"                                     \
  62         "fdt_addr=40080000\0"                                           \
  63         "kernel_addr=400A0000\0"                                        \
  64         "ramdisk_addr=40280000\0"                                       \
  65         "u-boot=TQM862M/u-image.bin\0"                                  \
  66         "load=tftp 200000 ${u-boot}\0"                                  \
  67         "update=prot off 40000000 +${filesize};"                        \
  68                 "era 40000000 +${filesize};"                            \
  69                 "cp.b 200000 40000000 ${filesize};"                     \
  70                 "sete filesize;save\0"                                  \
  71         ""
  72 #define CONFIG_BOOTCOMMAND      "run flash_self"
  73
  74 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  75 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  80
  81 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_SUBNETMASK
  87 #define CONFIG_BOOTP_GATEWAY
  88 #define CONFIG_BOOTP_HOSTNAME
  89 #define CONFIG_BOOTP_BOOTPATH
  90 #define CONFIG_BOOTP_BOOTFILESIZE
  91
  92
  93 #define CONFIG_MAC_PARTITION
  94 #define CONFIG_DOS_PARTITION
  95
  96 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  97
  98
  99 /*
 100  * Command line configuration.
 101  */
 102 #define CONFIG_CMD_ASKENV
 103 #define CONFIG_CMD_DATE
 104 #define CONFIG_CMD_DHCP
 105 #define CONFIG_CMD_EXT2
 106 #define CONFIG_CMD_IDE
 107 #define CONFIG_CMD_JFFS2
 108 #define CONFIG_CMD_SNTP
 109
 110
 111 #define CONFIG_NETCONSOLE
 112
 113
 114 /*
 115  * Miscellaneous configurable options
 116  */
 117 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 118
 119 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 120 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 121
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 124 #else
 125 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 126 #endif
 127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 128 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 129 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 130
 131 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 132 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 133
 134 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 135
 136 /*
 137  * Low Level Configuration Settings
 138  * (address mappings, register initial values, etc.)
 139  * You should know what you are doing if you make changes here.
 140  */
 141 /*-----------------------------------------------------------------------
 142  * Internal Memory Mapped Register
 143  */
 144 #define CONFIG_SYS_IMMR         0xFFF00000
 145
 146 /*-----------------------------------------------------------------------
 147  * Definitions for initial stack pointer and data area (in DPRAM)
 148  */
 149 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 150 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 151 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 152 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 153
 154 /*-----------------------------------------------------------------------
 155  * Start addresses for the final memory configuration
 156  * (Set up by the startup code)
 157  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 158  */
 159 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 160 #define CONFIG_SYS_FLASH_BASE           0x40000000
 161 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 163 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 164
 165 /*
 166  * For booting Linux, the board info and command line data
 167  * have to be in the first 8 MB of memory, since this is
 168  * the maximum mapped by the Linux kernel during initialization.
 169  */
 170 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 171
 172 /*-----------------------------------------------------------------------
 173  * FLASH organization
 174  */
 175
 176 /* use CFI flash driver */
 177 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 178 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 179 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 180 #define CONFIG_SYS_FLASH_EMPTY_INFO
 181 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 184
 185 #define CONFIG_ENV_IS_IN_FLASH  1
 186 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 187 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 188 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector     */
 189
 190 /* Address and size of Redundant Environment Sector     */
 191 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 192 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 193
 194 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 195
 196 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 197
 198 /*-----------------------------------------------------------------------
 199  * Dynamic MTD partition support
 200  */
 201 #define CONFIG_CMD_MTDPARTS
 202 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 203 #define CONFIG_FLASH_CFI_MTD
 204 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 205
 206 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 207                                                 "128k(dtb),"            \
 208                                                 "1920k(kernel),"        \
 209                                                 "5632(rootfs),"         \
 210                                                 "4m(data)"
 211
 212 /*-----------------------------------------------------------------------
 213  * Hardware Information Block
 214  */
 215 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 216 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 217 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 218
 219 /*-----------------------------------------------------------------------
 220  * Cache Configuration
 221  */
 222 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 223 #if defined(CONFIG_CMD_KGDB)
 224 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SYPCR - System Protection Control                            11-9
 229  * SYPCR can only be written once after reset!
 230  *-----------------------------------------------------------------------
 231  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 232  */
 233 #if defined(CONFIG_WATCHDOG)
 234 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 235                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 236 #else
 237 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 238 #endif
 239
 240 /*-----------------------------------------------------------------------
 241  * SIUMCR - SIU Module Configuration                            11-6
 242  *-----------------------------------------------------------------------
 243  * PCMCIA config., multi-function pin tri-state
 244  */
 245 #ifndef CONFIG_CAN_DRIVER
 246 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 247 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 248 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 249 #endif  /* CONFIG_CAN_DRIVER */
 250
 251 /*-----------------------------------------------------------------------
 252  * TBSCR - Time Base Status and Control                         11-26
 253  *-----------------------------------------------------------------------
 254  * Clear Reference Interrupt Status, Timebase freezing enabled
 255  */
 256 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 257
 258 /*-----------------------------------------------------------------------
 259  * RTCSC - Real-Time Clock Status and Control Register          11-27
 260  *-----------------------------------------------------------------------
 261  */
 262 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 263
 264 /*-----------------------------------------------------------------------
 265  * PISCR - Periodic Interrupt Status and Control                11-31
 266  *-----------------------------------------------------------------------
 267  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 268  */
 269 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 270
 271 /*-----------------------------------------------------------------------
 272  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 273  *-----------------------------------------------------------------------
 274  * Reset PLL lock status sticky bit, timer expired status bit and timer
 275  * interrupt status bit
 276  */
 277 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 278
 279 /*-----------------------------------------------------------------------
 280  * SCCR - System Clock and reset Control Register               15-27
 281  *-----------------------------------------------------------------------
 282  * Set clock output, timebase and RTC source and divider,
 283  * power management and some other internal clocks
 284  */
 285 #define SCCR_MASK       SCCR_EBDF11
 286 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 287                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 288                          SCCR_DFALCD00)
 289
 290 /*-----------------------------------------------------------------------
 291  * PCMCIA stuff
 292  *-----------------------------------------------------------------------
 293  *
 294  */
 295 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 296 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 297 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 298 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 299 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 300 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 301 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 302 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 303
 304 /*-----------------------------------------------------------------------
 305  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 306  *-----------------------------------------------------------------------
 307  */
 308
 309 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 310 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 311
 312 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 313 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 314 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 315
 316 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 317 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 318
 319 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 320
 321 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 322
 323 /* Offset for data I/O                  */
 324 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 325
 326 /* Offset for normal register accesses  */
 327 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 328
 329 /* Offset for alternate registers       */
 330 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 331
 332 /*-----------------------------------------------------------------------
 333  *
 334  *-----------------------------------------------------------------------
 335  *
 336  */
 337 #define CONFIG_SYS_DER  0
 338
 339 /*
 340  * Init Memory Controller:
 341  *
 342  * BR0/1 and OR0/1 (FLASH)
 343  */
 344
 345 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 346 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #1        */
 347
 348 /* used to re-map FLASH both when starting from SRAM or FLASH:
 349  * restrict access enough to keep SRAM working (if any)
 350  * but not too much to meddle with FLASH accesses
 351  */
 352 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 353 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 354
 355 /*
 356  * FLASH timing:
 357  */
 358 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 359                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 360
 361 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 362 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 363 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 364
 365 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 366 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 367 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 368
 369 /*
 370  * BR2/3 and OR2/3 (SDRAM)
 371  *
 372  */
 373 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 374 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 375 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 376
 377 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 378 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 379
 380 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 381 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 382
 383 #ifndef CONFIG_CAN_DRIVER
 384 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 385 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 386 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 387 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 388 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 389 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 390 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 391                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 392 #endif  /* CONFIG_CAN_DRIVER */
 393
 394 /*
 395  * Memory Periodic Timer Prescaler
 396  *
 397  * The Divider for PTA (refresh timer) configuration is based on an
 398  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 399  * the number of chip selects (NCS) and the actually needed refresh
 400  * rate is done by setting MPTPR.
 401  *
 402  * PTA is calculated from
 403  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 404  *
 405  *      gclk      CPU clock (not bus clock!)
 406  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 407  *
 408  * 4096  Rows from SDRAM example configuration
 409  * 1000  factor s -> ms
 410  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 411  *    4  Number of refresh cycles per period
 412  *   64  Refresh cycle in ms per number of rows
 413  * --------------------------------------------
 414  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 415  *
 416  *  50 MHz =>  50.000.000 / Divider =  98
 417  *  66 Mhz =>  66.000.000 / Divider = 129
 418  *  80 Mhz =>  80.000.000 / Divider = 156
 419  * 100 Mhz => 100.000.000 / Divider = 195
 420  */
 421
 422 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 423 #define CONFIG_SYS_MAMR_PTA     98
 424
 425 /*
 426  * For 16 MBit, refresh rates could be 31.3 us
 427  * (= 64 ms / 2K = 125 / quad bursts).
 428  * For a simpler initialization, 15.6 us is used instead.
 429  *
 430  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 431  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 432  */
 433 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 434 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 435
 436 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 437 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 438 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 439
 440 /*
 441  * MAMR settings for SDRAM
 442  */
 443
 444 /* 8 column SDRAM */
 445 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 446                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 447                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 448 /* 9 column SDRAM */
 449 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 450                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 451                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 452
 453 #define CONFIG_SCC1_ENET
 454 #define CONFIG_FEC_ENET
 455 #define CONFIG_ETHPRIME         "SCC"
 456
 457 /* pass open firmware flat tree */
 458 #define CONFIG_OF_BOARD_SETUP   1
 459 #define CONFIG_HWCONFIG         1
 460
 461 #endif  /* __CONFIG_H */