include/configs/TQM866M.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC866           1       /* This is a MPC866 CPU         */
  37 #define CONFIG_TQM866M          1       /* ...on a TQM8xxM module       */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40000000
  40
  41 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  42 #define CONFIG_SYS_8xx_CPUCLK_MIN               15000000        /*  15 MHz - CPU minimum clock  */
  43 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000       /* 133 MHz - CPU maximum clock  */
  44 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000        /*  50 MHz - CPU default clock  */
  45                                                 /* (it will be used if there is no      */
  46                                                 /* 'cpuclk' variable with valid value)  */
  47
  48 #undef CONFIG_SYS_MEASURE_CPUCLK                        /* Measure real cpu clock       */
  49                                                 /* (function measure_gclk()     */
  50                                                 /* will be called)              */
  51 #ifdef CONFIG_SYS_MEASURE_CPUCLK
  52 #define CONFIG_SYS_8XX_XIN              10000000        /* measure_gclk() needs this    */
  53 #endif
  54
  55 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  56 #define CONFIG_SYS_SMC_RXBUFLEN 128
  57 #define CONFIG_SYS_MAXIDLE      10
  58 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  59
  60 #define CONFIG_BOOTCOUNT_LIMIT
  61
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63
  64 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  65
  66 #define CONFIG_PREBOOT  "echo;" \
  67         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  68         "echo"
  69
  70 #undef  CONFIG_BOOTARGS
  71
  72 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  73         "netdev=eth0\0"                                                 \
  74         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  75                 "nfsroot=${serverip}:${rootpath}\0"                     \
  76         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  77         "addip=setenv bootargs ${bootargs} "                            \
  78                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  79                 ":${hostname}:${netdev}:off panic=1\0"                  \
  80         "flash_nfs=run nfsargs addip;"                                  \
  81                 "bootm ${kernel_addr}\0"                                \
  82         "flash_self=run ramargs addip;"                                 \
  83                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  84         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  85         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  86         "hostname=TQM866M\0"                                            \
  87         "bootfile=TQM866M/uImage\0"                                     \
  88         "fdt_addr=400C0000\0"                                           \
  89         "kernel_addr=40100000\0"                                        \
  90         "ramdisk_addr=40280000\0"                                       \
  91         "u-boot=TQM866M/u-image.bin\0"                                  \
  92         "load=tftp 200000 ${u-boot}\0"                                  \
  93         "update=prot off 40000000 +${filesize};"                        \
  94                 "era 40000000 +${filesize};"                            \
  95                 "cp.b 200000 40000000 ${filesize};"                     \
  96                 "sete filesize;save\0"                                  \
  97         ""
  98 #define CONFIG_BOOTCOMMAND      "run flash_self"
  99
 100 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 101 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 102
 103 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 104
 105 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 106
 107 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 108
 109 /* enable I2C and select the hardware/software driver */
 110 #define CONFIG_SYS_I2C
 111 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 112 #define CONFIG_SYS_I2C_SOFT_SPEED       93000   /* 93 kHz is supposed to work */
 113 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 114
 115 /*
 116  * Software (bit-bang) I2C driver configuration
 117  */
 118 #define PB_SCL          0x00000020      /* PB 26 */
 119 #define PB_SDA          0x00000010      /* PB 27 */
 120
 121 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 122 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 123 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 124 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 125 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 126                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 127 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 128                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 129 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 130
 131 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM AT24C256      */
 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2                /* two byte address     */
 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 135
 136 /*
 137  * BOOTP options
 138  */
 139 #define CONFIG_BOOTP_SUBNETMASK
 140 #define CONFIG_BOOTP_GATEWAY
 141 #define CONFIG_BOOTP_HOSTNAME
 142 #define CONFIG_BOOTP_BOOTPATH
 143 #define CONFIG_BOOTP_BOOTFILESIZE
 144
 145
 146 #define CONFIG_MAC_PARTITION
 147 #define CONFIG_DOS_PARTITION
 148
 149 #undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 150
 151 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 152
 153
 154 /*
 155  * Command line configuration.
 156  */
 157 #include <config_cmd_default.h>
 158
 159 #define CONFIG_CMD_ASKENV
 160 #define CONFIG_CMD_DHCP
 161 #define CONFIG_CMD_EEPROM
 162 #define CONFIG_CMD_ELF
 163 #define CONFIG_CMD_EXT2
 164 #define CONFIG_CMD_IDE
 165 #define CONFIG_CMD_JFFS2
 166 #define CONFIG_CMD_NFS
 167 #define CONFIG_CMD_SNTP
 168
 169
 170 #define CONFIG_NETCONSOLE
 171
 172
 173 /*
 174  * Miscellaneous configurable options
 175  */
 176 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 177 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 178
 179 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 180 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 181
 182 #if defined(CONFIG_CMD_KGDB)
 183 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 184 #else
 185 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 186 #endif
 187 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 188 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 189 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 190
 191 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 192 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 193
 194 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 195
 196 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 197
 198 /*
 199  * Low Level Configuration Settings
 200  * (address mappings, register initial values, etc.)
 201  * You should know what you are doing if you make changes here.
 202  */
 203 /*-----------------------------------------------------------------------
 204  * Internal Memory Mapped Register
 205  */
 206 #define CONFIG_SYS_IMMR         0xFFF00000
 207
 208 /*-----------------------------------------------------------------------
 209  * Definitions for initial stack pointer and data area (in DPRAM)
 210  */
 211 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 212 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 213 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 214 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 215
 216 /*-----------------------------------------------------------------------
 217  * Start addresses for the final memory configuration
 218  * (Set up by the startup code)
 219  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 220  */
 221 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 222 #define CONFIG_SYS_FLASH_BASE           0x40000000
 223 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 225 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 226
 227 /*
 228  * For booting Linux, the board info and command line data
 229  * have to be in the first 8 MB of memory, since this is
 230  * the maximum mapped by the Linux kernel during initialization.
 231  */
 232 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 233
 234 /*-----------------------------------------------------------------------
 235  * FLASH organization
 236  */
 237 /* use CFI flash driver */
 238 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 239 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 240 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 241 #define CONFIG_SYS_FLASH_EMPTY_INFO
 242 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 243 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 244 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 245
 246 #define CONFIG_ENV_IS_IN_FLASH  1
 247 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 248 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment Sector     */
 249 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 250
 251 /* Address and size of Redundant Environment Sector     */
 252 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 253 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 254
 255 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 256
 257 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 258
 259 /*-----------------------------------------------------------------------
 260  * Dynamic MTD partition support
 261  */
 262 #define CONFIG_CMD_MTDPARTS
 263 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 264 #define CONFIG_FLASH_CFI_MTD
 265 #define MTDIDS_DEFAULT          "nor0=TQM8xxM-0"
 266
 267 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxM-0:512k(u-boot),"      \
 268                                                 "128k(dtb),"            \
 269                                                 "1920k(kernel),"        \
 270                                                 "5632(rootfs),"         \
 271                                                 "4m(data)"
 272
 273 /*-----------------------------------------------------------------------
 274  * Hardware Information Block
 275  */
 276 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 277 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 278 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 279
 280 /*-----------------------------------------------------------------------
 281  * Cache Configuration
 282  */
 283 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 284 #if defined(CONFIG_CMD_KGDB)
 285 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 286 #endif
 287
 288 /*-----------------------------------------------------------------------
 289  * SYPCR - System Protection Control                            11-9
 290  * SYPCR can only be written once after reset!
 291  *-----------------------------------------------------------------------
 292  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 293  */
 294 #if defined(CONFIG_WATCHDOG)
 295 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 296                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 297 #else
 298 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 299 #endif
 300
 301 /*-----------------------------------------------------------------------
 302  * SIUMCR - SIU Module Configuration                            11-6
 303  *-----------------------------------------------------------------------
 304  * PCMCIA config., multi-function pin tri-state
 305  */
 306 #ifndef CONFIG_CAN_DRIVER
 307 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 308 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 309 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 310 #endif  /* CONFIG_CAN_DRIVER */
 311
 312 /*-----------------------------------------------------------------------
 313  * TBSCR - Time Base Status and Control                         11-26
 314  *-----------------------------------------------------------------------
 315  * Clear Reference Interrupt Status, Timebase freezing enabled
 316  */
 317 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 318
 319 /*-----------------------------------------------------------------------
 320  * PISCR - Periodic Interrupt Status and Control                11-31
 321  *-----------------------------------------------------------------------
 322  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 323  */
 324 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 325
 326 /*-----------------------------------------------------------------------
 327  * SCCR - System Clock and reset Control Register               15-27
 328  *-----------------------------------------------------------------------
 329  * Set clock output, timebase and RTC source and divider,
 330  * power management and some other internal clocks
 331  */
 332 #define SCCR_MASK       SCCR_EBDF11
 333 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 334                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 335                          SCCR_DFALCD00)
 336
 337 /*-----------------------------------------------------------------------
 338  * PCMCIA stuff
 339  *-----------------------------------------------------------------------
 340  *
 341  */
 342 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 343 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 344 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 345 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 346 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 347 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 348 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 349 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 350
 351 /*-----------------------------------------------------------------------
 352  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 353  *-----------------------------------------------------------------------
 354  */
 355
 356 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 357 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 358
 359 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 360 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 361 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 362
 363 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 364 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 365
 366 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 367
 368 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 369
 370 /* Offset for data I/O                  */
 371 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 372
 373 /* Offset for normal register accesses  */
 374 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 375
 376 /* Offset for alternate registers       */
 377 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 378
 379 /*-----------------------------------------------------------------------
 380  *
 381  *-----------------------------------------------------------------------
 382  *
 383  */
 384 #define CONFIG_SYS_DER 0
 385
 386 /*
 387  * Init Memory Controller:
 388  *
 389  * BR0/1 and OR0/1 (FLASH)
 390  */
 391
 392 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 393 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 394
 395 /* used to re-map FLASH both when starting from SRAM or FLASH:
 396  * restrict access enough to keep SRAM working (if any)
 397  * but not too much to meddle with FLASH accesses
 398  */
 399 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 400 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 401
 402 /*
 403  * FLASH timing: Default value of OR0 after reset
 404  */
 405 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 406                                  OR_SCY_15_CLK | OR_TRLX)
 407
 408 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 409 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 410 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 411
 412 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 413 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 414 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 415
 416 /*
 417  * BR2/3 and OR2/3 (SDRAM)
 418  *
 419  */
 420 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 421 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 422 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 423
 424 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 425 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 426
 427 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 428 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 429
 430 #ifndef CONFIG_CAN_DRIVER
 431 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 432 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 433 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 434 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 435 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 436 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 437 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 438                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 439 #endif  /* CONFIG_CAN_DRIVER */
 440
 441 /*
 442  * 4096 Rows from SDRAM example configuration
 443  * 1000 factor s -> ms
 444  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 445  * 4    Number of refresh cycles per period
 446  * 64   Refresh cycle in ms per number of rows
 447  */
 448 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 449
 450 /*
 451  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 452  *
 453  *                        CPUclock(MHz) * 31.2
 454  * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 455  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 456  *
 457  * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 458  * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 459  * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 460  * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 461  *
 462  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 463  * be met also in the default configuration, i.e. if environment variable
 464  * 'cpuclk' is not set.
 465  */
 466 #define CONFIG_SYS_MAMR_PTA             97
 467
 468 /*
 469  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 470  */
 471 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 472 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
 473 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 474 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
 475
 476 /*
 477  * MAMR settings for SDRAM
 478  */
 479
 480 /* 8 column SDRAM */
 481 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 482                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 483                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 484 /* 9 column SDRAM */
 485 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 486                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 487                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 488 /* 10 column SDRAM */
 489 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 490                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 491                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 492
 493 #define CONFIG_SCC1_ENET
 494 #define CONFIG_FEC_ENET
 495 #define CONFIG_ETHPRIME         "SCC"
 496
 497 /* pass open firmware flat tree */
 498 #define CONFIG_OF_LIBFDT        1
 499 #define CONFIG_OF_BOARD_SETUP   1
 500 #define CONFIG_HWCONFIG         1
 501
 502 #endif  /* __CONFIG_H */