include/configs/TQM885D.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC885           1       /* This is a MPC885 CPU         */
  40 #define CONFIG_TQM885D          1       /* ...on a TQM88D module        */
  41
  42 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  43 #define CONFIG_SYS_8xx_CPUCLK_MIN               15000000        /*  15 MHz - CPU minimum clock  */
  44 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000       /* 133 MHz - CPU maximum clock  */
  45 #define CONFIG_8xx_CPUCLK_DEFAULT       66000000        /*  66 MHz - CPU default clock  */
  46                                                 /* (it will be used if there is no      */
  47                                                 /* 'cpuclk' variable with valid value)  */
  48
  49 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  50 #define CONFIG_SYS_SMC_RXBUFLEN 128
  51 #define CONFIG_SYS_MAXIDLE      10
  52 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  53
  54 #define CONFIG_BOOTCOUNT_LIMIT
  55
  56 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  57
  58 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  59
  60 #define CONFIG_PREBOOT  "echo;" \
  61         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  62         "echo"
  63
  64 #undef  CONFIG_BOOTARGS
  65
  66 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  67         "netdev=eth0\0"                                                 \
  68         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  69                 "nfsroot=${serverip}:${rootpath}\0"                     \
  70         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  71         "addip=setenv bootargs ${bootargs} "                            \
  72                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  73                 ":${hostname}:${netdev}:off panic=1\0"                  \
  74         "flash_nfs=run nfsargs addip;"                                  \
  75                 "bootm ${kernel_addr}\0"                                \
  76         "flash_self=run ramargs addip;"                                 \
  77                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  78         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  79         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  80         "bootfile=/tftpboot/TQM885D/uImage\0"                           \
  81         "fdt_addr=400C0000\0"                                           \
  82         "kernel_addr=40100000\0"                                        \
  83         "ramdisk_addr=40280000\0"                                       \
  84         "load=tftp 200000 ${u-boot}\0"                                  \
  85         "update=protect off 40000000 +${filesize};"                     \
  86                 "erase 40000000 +${filesize};"                          \
  87                 "cp.b 200000 40000000 ${filesize};"                     \
  88                 "protect on 40000000 +${filesize}\0"                    \
  89         ""
  90 #define CONFIG_BOOTCOMMAND      "run flash_self"
  91
  92 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  93 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  94
  95 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  96
  97 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  98
  99 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 100
 101 /* enable I2C and select the hardware/software driver */
 102 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 103 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 104
 105 #define CONFIG_SYS_I2C_SPEED            93000   /* 93 kHz is supposed to work   */
 106 #define CONFIG_SYS_I2C_SLAVE            0xFE
 107
 108 #ifdef CONFIG_SOFT_I2C
 109 /*
 110  * Software (bit-bang) I2C driver configuration
 111  */
 112 #define PB_SCL          0x00000020      /* PB 26 */
 113 #define PB_SDA          0x00000010      /* PB 27 */
 114
 115 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 116 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 117 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 118 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 119 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 120                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 121 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 122                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 123 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 124 #endif  /* CONFIG_SOFT_I2C */
 125
 126 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM AT24C??       */
 127 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2                /* two byte address     */
 128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 129 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 130
 131 # define CONFIG_RTC_DS1337 1
 132 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
 133
 134 /*
 135  * BOOTP options
 136  */
 137 #define CONFIG_BOOTP_SUBNETMASK
 138 #define CONFIG_BOOTP_GATEWAY
 139 #define CONFIG_BOOTP_HOSTNAME
 140 #define CONFIG_BOOTP_BOOTPATH
 141 #define CONFIG_BOOTP_BOOTFILESIZE
 142
 143
 144 #define CONFIG_MAC_PARTITION
 145 #define CONFIG_DOS_PARTITION
 146
 147 #undef CONFIG_RTC_MPC8xx                /* MPC885 does not support RTC  */
 148
 149 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 150
 151
 152 /*
 153  * Command line configuration.
 154  */
 155 #include <config_cmd_default.h>
 156
 157 #define CONFIG_CMD_ASKENV
 158 #define CONFIG_CMD_DATE
 159 #define CONFIG_CMD_DHCP
 160 #define CONFIG_CMD_EEPROM
 161 #define CONFIG_CMD_EXT2
 162 #define CONFIG_CMD_I2C
 163 #define CONFIG_CMD_IDE
 164 #define CONFIG_CMD_MII
 165 #define CONFIG_CMD_NFS
 166 #define CONFIG_CMD_PING
 167
 168
 169 /*
 170  * Miscellaneous configurable options
 171  */
 172 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 173 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 174
 175 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 176 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 177 #ifdef  CONFIG_SYS_HUSH_PARSER
 178 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 179 #endif
 180
 181 #if defined(CONFIG_CMD_KGDB)
 182 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 183 #else
 184 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 185 #endif
 186 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 187 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 188 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 189
 190 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 191 #define CONFIG_SYS_MEMTEST_END          0x0300000       /* 1 ... 3 MB in DRAM   */
 192 #define CONFIG_SYS_ALT_MEMTEST                          /* alternate, more extensive
 193                                                    memory test.*/
 194
 195 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 196
 197 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 198
 199 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 200
 201 /*
 202  * Enable loopw command.
 203  */
 204 #define CONFIG_LOOPW
 205
 206 /*
 207  * Low Level Configuration Settings
 208  * (address mappings, register initial values, etc.)
 209  * You should know what you are doing if you make changes here.
 210  */
 211 /*-----------------------------------------------------------------------
 212  * Internal Memory Mapped Register
 213  */
 214 #define CONFIG_SYS_IMMR         0xFFF00000
 215
 216 /*-----------------------------------------------------------------------
 217  * Definitions for initial stack pointer and data area (in DPRAM)
 218  */
 219 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 220 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 221 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 222 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 223 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 224
 225 /*-----------------------------------------------------------------------
 226  * Start addresses for the final memory configuration
 227  * (Set up by the startup code)
 228  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 229  */
 230 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 231 #define CONFIG_SYS_FLASH_BASE           0x40000000
 232 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 234 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 128 kB for malloc()  */
 235
 236 /*
 237  * For booting Linux, the board info and command line data
 238  * have to be in the first 8 MB of memory, since this is
 239  * the maximum mapped by the Linux kernel during initialization.
 240  */
 241 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 242
 243 /*-----------------------------------------------------------------------
 244  * FLASH organization
 245  */
 246
 247 /* use CFI flash driver */
 248 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 249 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 250 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 251 #define CONFIG_SYS_FLASH_EMPTY_INFO
 252 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 253 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 254 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 255
 256 #define CONFIG_ENV_IS_IN_FLASH  1
 257 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 258 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 259 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 260
 261 /* Address and size of Redundant Environment Sector     */
 262 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 263 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 264
 265 /*-----------------------------------------------------------------------
 266  * Hardware Information Block
 267  */
 268 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 269 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 270 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 271
 272 /*-----------------------------------------------------------------------
 273  * Cache Configuration
 274  */
 275 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 276 #if defined(CONFIG_CMD_KGDB)
 277 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 278 #endif
 279
 280 /*-----------------------------------------------------------------------
 281  * SYPCR - System Protection Control                            11-9
 282  * SYPCR can only be written once after reset!
 283  *-----------------------------------------------------------------------
 284  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 285  */
 286 #if defined(CONFIG_WATCHDOG)
 287 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 288                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 289 #else
 290 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 291 #endif
 292
 293 /*-----------------------------------------------------------------------
 294  * SIUMCR - SIU Module Configuration                            11-6
 295  *-----------------------------------------------------------------------
 296  * PCMCIA config., multi-function pin tri-state
 297  */
 298 #ifndef CONFIG_CAN_DRIVER
 299 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 300 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 301 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 302 #endif  /* CONFIG_CAN_DRIVER */
 303
 304 /*-----------------------------------------------------------------------
 305  * TBSCR - Time Base Status and Control                         11-26
 306  *-----------------------------------------------------------------------
 307  * Clear Reference Interrupt Status, Timebase freezing enabled
 308  */
 309 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 310
 311 /*-----------------------------------------------------------------------
 312  * PISCR - Periodic Interrupt Status and Control                11-31
 313  *-----------------------------------------------------------------------
 314  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 315  */
 316 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 317
 318 /*-----------------------------------------------------------------------
 319  * SCCR - System Clock and reset Control Register               15-27
 320  *-----------------------------------------------------------------------
 321  * Set clock output, timebase and RTC source and divider,
 322  * power management and some other internal clocks
 323  */
 324 #define SCCR_MASK       SCCR_EBDF11
 325 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 326                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 327                          SCCR_DFALCD00)
 328
 329 /*-----------------------------------------------------------------------
 330  * PCMCIA stuff
 331  *-----------------------------------------------------------------------
 332  *
 333  */
 334 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 335 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 336 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 337 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 338 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 339 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 340 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 341 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 342
 343 /*-----------------------------------------------------------------------
 344  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 345  *-----------------------------------------------------------------------
 346  */
 347
 348 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 349
 350 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 351 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 352 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 353
 354 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 355 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 356
 357 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 358
 359 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 360
 361 /* Offset for data I/O                  */
 362 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 363
 364 /* Offset for normal register accesses  */
 365 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 366
 367 /* Offset for alternate registers       */
 368 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 369
 370 /*-----------------------------------------------------------------------
 371  *
 372  *-----------------------------------------------------------------------
 373  *
 374  */
 375 #define CONFIG_SYS_DER 0
 376
 377 /*
 378  * Init Memory Controller:
 379  *
 380  * BR0/1 and OR0/1 (FLASH)
 381  */
 382
 383 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 384 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 385
 386 /* used to re-map FLASH both when starting from SRAM or FLASH:
 387  * restrict access enough to keep SRAM working (if any)
 388  * but not too much to meddle with FLASH accesses
 389  */
 390 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 391 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 392
 393 /*
 394  * FLASH timing: Default value of OR0 after reset
 395  */
 396 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 397                                  OR_SCY_6_CLK | OR_TRLX)
 398
 399 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 400 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 401 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 402
 403 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 404 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 405 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 406
 407 /*
 408  * BR2/3 and OR2/3 (SDRAM)
 409  *
 410  */
 411 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 412 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 413 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 414
 415 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 416 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 417
 418 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 419 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 420
 421 #ifndef CONFIG_CAN_DRIVER
 422 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 423 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 424 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 425 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 426 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 427 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 428 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 429                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 430 #endif  /* CONFIG_CAN_DRIVER */
 431
 432 /*
 433  * 4096 Rows from SDRAM example configuration
 434  * 1000 factor s -> ms
 435  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 436  * 4    Number of refresh cycles per period
 437  * 64   Refresh cycle in ms per number of rows
 438  */
 439 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 440
 441 /*
 442  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 443  *
 444  *                        CPUclock(MHz) * 31.2
 445  * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 446  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 447  *
 448  * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 449  * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 450  * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 451  * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 452  *
 453  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 454  * be met also in the default configuration, i.e. if environment variable
 455  * 'cpuclk' is not set.
 456  */
 457 #define CONFIG_SYS_MAMR_PTA             128
 458
 459 /*
 460  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 461  */
 462 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 463 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
 464 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 465 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
 466
 467 /*
 468  * MAMR settings for SDRAM
 469  */
 470
 471 /* 8 column SDRAM */
 472 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 473                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 474                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 475 /* 9 column SDRAM */
 476 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 477                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 478                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 479 /* 10 column SDRAM */
 480 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 481                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 482                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 483
 484 /*
 485  * Internal Definitions
 486  *
 487  * Boot Flags
 488  */
 489 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 490 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 491
 492 /*
 493  * Network configuration
 494  */
 495 #define CONFIG_SCC2_ENET                /* enable ethernet on SCC2 */
 496 #define CONFIG_FEC_ENET                 /* enable ethernet on FEC */
 497 #define CONFIG_ETHER_ON_FEC1            /* ... for FEC1 */
 498 #define CONFIG_ETHER_ON_FEC2            /* ... for FEC2 */
 499
 500 #if defined(CONFIG_CMD_MII)
 501 #define CONFIG_SYS_DISCOVER_PHY
 502 #define CONFIG_MII_INIT 1
 503 #endif
 504
 505 #define CONFIG_NET_RETRY_COUNT 1        /* reduce max. timeout before
 506                                            switching to another netwok (if the
 507                                            tried network is unreachable) */
 508
 509 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 510
 511 /* pass open firmware flat tree */
 512 #define CONFIG_OF_LIBFDT        1
 513 #define CONFIG_OF_BOARD_SETUP   1
 514 #define CONFIG_HWCONFIG         1
 515
 516 #endif  /* __CONFIG_H */