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Kconfig: Move CONFIG_FIT and related options to Kconfig
[people/ms/u-boot.git] / include / configs / UCP1020.h
1 /*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_FSL_ELBC
20 #define CONFIG_PCI
21 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
22 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
23 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
24 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
25 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
26 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
27
28 #if defined(CONFIG_TARTGET_UCP1020T1)
29
30 #define CONFIG_UCP1020_REV_1_3
31
32 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
33 #define CONFIG_P1020
34
35 #define CONFIG_TSEC_ENET
36 #define CONFIG_TSEC1
37 #define CONFIG_TSEC3
38 #define CONFIG_HAS_ETH0
39 #define CONFIG_HAS_ETH1
40 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
41 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
42 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
43 #define CONFIG_IPADDR 10.80.41.229
44 #define CONFIG_SERVERIP 10.80.41.227
45 #define CONFIG_NETMASK 255.255.252.0
46 #define CONFIG_ETHPRIME "eTSEC3"
47
48 #ifndef CONFIG_SPI_FLASH
49 #endif
50 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
51
52 #define CONFIG_MMC
53 #define CONFIG_SYS_L2_SIZE (256 << 10)
54
55 #define CONFIG_LAST_STAGE_INIT
56
57 #if !defined(CONFIG_DONGLE)
58 #define CONFIG_SILENT_CONSOLE
59 #endif
60
61 #endif
62
63 #if defined(CONFIG_TARGET_UCP1020)
64
65 #define CONFIG_UCP1020
66 #define CONFIG_UCP1020_REV_1_3
67
68 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
69 #define CONFIG_P1020
70
71 #define CONFIG_TSEC_ENET
72 #define CONFIG_TSEC1
73 #define CONFIG_TSEC2
74 #define CONFIG_TSEC3
75 #define CONFIG_HAS_ETH0
76 #define CONFIG_HAS_ETH1
77 #define CONFIG_HAS_ETH2
78 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
79 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
80 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
81 #define CONFIG_IPADDR 192.168.1.81
82 #define CONFIG_IPADDR1 192.168.1.82
83 #define CONFIG_IPADDR2 192.168.1.83
84 #define CONFIG_SERVERIP 192.168.1.80
85 #define CONFIG_GATEWAYIP 102.168.1.1
86 #define CONFIG_NETMASK 255.255.255.0
87 #define CONFIG_ETHPRIME "eTSEC1"
88
89 #ifndef CONFIG_SPI_FLASH
90 #endif
91 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
92
93 #define CONFIG_MMC
94 #define CONFIG_SYS_L2_SIZE (256 << 10)
95
96 #define CONFIG_LAST_STAGE_INIT
97
98 #endif
99
100 #ifdef CONFIG_SDCARD
101 #define CONFIG_RAMBOOT_SDCARD
102 #define CONFIG_SYS_RAMBOOT
103 #define CONFIG_SYS_EXTRA_ENV_RELOC
104 #define CONFIG_SYS_TEXT_BASE 0x11000000
105 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
106 #endif
107
108 #ifdef CONFIG_SPIFLASH
109 #define CONFIG_RAMBOOT_SPIFLASH
110 #define CONFIG_SYS_RAMBOOT
111 #define CONFIG_SYS_EXTRA_ENV_RELOC
112 #define CONFIG_SYS_TEXT_BASE 0x11000000
113 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
114 #endif
115
116 #ifndef CONFIG_SYS_TEXT_BASE
117 #define CONFIG_SYS_TEXT_BASE 0xeff80000
118 #endif
119 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
120
121 #ifndef CONFIG_RESET_VECTOR_ADDRESS
122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
123 #endif
124
125 #ifndef CONFIG_SYS_MONITOR_BASE
126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
127 #endif
128
129 /* High Level Configuration Options */
130 #define CONFIG_BOOKE
131 #define CONFIG_E500
132 /* #define CONFIG_MPC85xx */
133
134 #define CONFIG_MP
135
136 #define CONFIG_FSL_LAW
137
138 #define CONFIG_ENV_OVERWRITE
139
140 #define CONFIG_CMD_SATA
141 #define CONFIG_SATA_SIL
142 #define CONFIG_SYS_SATA_MAX_DEVICE 2
143 #define CONFIG_LIBATA
144 #define CONFIG_LBA48
145
146 #define CONFIG_SYS_CLK_FREQ 66666666
147 #define CONFIG_DDR_CLK_FREQ 66666666
148
149 #define CONFIG_HWCONFIG
150
151 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
152 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
153 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
154 /*
155 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
156 * there will be one entry in this array for each two (dummy) sensors in
157 * CONFIG_DTT_SENSORS.
158 *
159 * For uCP1020 module:
160 * - only one ADM1021/NCT72
161 * - i2c addr 0x41
162 * - conversion rate 0x02 = 0.25 conversions/second
163 * - ALERT output disabled
164 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
165 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
166 */
167 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
168 0x02, 0, 1, 0, 85, 1, 0, 85} }
169
170 #define CONFIG_CMD_DTT
171
172 /*
173 * These can be toggled for performance analysis, otherwise use default.
174 */
175 #define CONFIG_L2_CACHE
176 #define CONFIG_BTB
177
178 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
179
180 #define CONFIG_ENABLE_36BIT_PHYS
181
182 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
183 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
184 #define CONFIG_PANIC_HANG /* do not reset board on panic */
185
186 #define CONFIG_SYS_CCSRBAR 0xffe00000
187 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
188
189 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
190 SPL code*/
191 #ifdef CONFIG_SPL_BUILD
192 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
193 #endif
194
195 /* DDR Setup */
196 #define CONFIG_DDR_ECC_ENABLE
197 #define CONFIG_SYS_FSL_DDR3
198 #ifndef CONFIG_DDR_ECC_ENABLE
199 #define CONFIG_SYS_DDR_RAW_TIMING
200 #define CONFIG_DDR_SPD
201 #endif
202 #define CONFIG_SYS_SPD_BUS_NUM 1
203 #undef CONFIG_FSL_DDR_INTERACTIVE
204
205 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
206 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
207 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
210
211 #define CONFIG_NUM_DDR_CONTROLLERS 1
212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
213
214 /* Default settings for DDR3 */
215 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
216 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
217 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
218 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
219 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
220 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
221
222 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
223 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
224 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
225 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
226
227 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
228 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
229 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
230 #define CONFIG_SYS_DDR_RCW_1 0x00000000
231 #define CONFIG_SYS_DDR_RCW_2 0x00000000
232 #ifdef CONFIG_DDR_ECC_ENABLE
233 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
234 #else
235 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
236 #endif
237 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
238 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
239 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
240
241 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
242 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
243 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
244 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
245 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
246 #define CONFIG_SYS_DDR_MODE_1 0x40461520
247 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
248 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
249
250 #undef CONFIG_CLOCKS_IN_MHZ
251
252 /*
253 * Memory map
254 *
255 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
256 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
257 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
258 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
259 * (early boot only)
260 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
261 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
262 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
263 */
264
265 /*
266 * Local Bus Definitions
267 */
268 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
269 #define CONFIG_SYS_FLASH_BASE 0xec000000
270
271 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
272
273 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
274 | BR_PS_16 | BR_V)
275
276 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
277
278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
279 #define CONFIG_SYS_FLASH_QUIET_TEST
280 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
281
282 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
283
284 #undef CONFIG_SYS_FLASH_CHECKSUM
285 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
286 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
287
288 #define CONFIG_FLASH_CFI_DRIVER
289 #define CONFIG_SYS_FLASH_CFI
290 #define CONFIG_SYS_FLASH_EMPTY_INFO
291 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
292
293 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
294
295 #define CONFIG_SYS_INIT_RAM_LOCK
296 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
297 /* Initial L1 address */
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
301 /* Size of used area in RAM */
302 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
303
304 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
305 GENERATED_GBL_DATA_SIZE)
306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
307
308 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
309 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
310
311 #define CONFIG_SYS_PMC_BASE 0xff980000
312 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
313 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
314 BR_PS_8 | BR_V)
315 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
316 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
317 OR_GPCM_EAD)
318
319 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
320 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
321 #ifdef CONFIG_NAND_FSL_ELBC
322 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
323 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
324 #endif
325
326 /* Serial Port - controlled on board with jumper J8
327 * open - index 2
328 * shorted - index 1
329 */
330 #define CONFIG_CONS_INDEX 1
331 #undef CONFIG_SERIAL_SOFTWARE_FIFO
332 #define CONFIG_SYS_NS16550_SERIAL
333 #define CONFIG_SYS_NS16550_REG_SIZE 1
334 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
335 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
336 #define CONFIG_NS16550_MIN_FUNCTIONS
337 #endif
338
339 #define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341
342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
344
345 /* Use the HUSH parser */
346 #define CONFIG_SYS_HUSH_PARSER
347
348 /* I2C */
349 #define CONFIG_SYS_I2C
350 #define CONFIG_SYS_I2C_FSL
351 #define CONFIG_SYS_FSL_I2C_SPEED 400000
352 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
353 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
354 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
355 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
356 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
357 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
358 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
359
360 #define CONFIG_RTC_DS1337
361 #define CONFIG_SYS_RTC_DS1337_NOOSC
362 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
363 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
364 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
365 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
366
367 /*
368 * eSPI - Enhanced SPI
369 */
370 #define CONFIG_HARD_SPI
371
372 #define CONFIG_CMD_SF 1
373 #define CONFIG_CMD_SPI 1
374 #define CONFIG_SF_DEFAULT_SPEED 10000000
375 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
376
377 #if defined(CONFIG_PCI)
378 /*
379 * General PCI
380 * Memory space is mapped 1-1, but I/O space must start from 0.
381 */
382
383 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
384 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
385 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
386 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
387 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
388 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
389 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
390 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
391 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
392 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
393
394 /* controller 1, Slot 2, tgtid 1, Base address a000 */
395 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
396 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
397 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
399 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
400 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
401 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
402 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
403 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
404
405 #define CONFIG_PCI_PNP /* do pci plug-and-play */
406 #define CONFIG_CMD_PCI
407
408 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
409 #define CONFIG_DOS_PARTITION
410 #endif /* CONFIG_PCI */
411
412 /*
413 * Environment
414 */
415 #ifdef CONFIG_ENV_FIT_UCBOOT
416
417 #define CONFIG_ENV_IS_IN_FLASH
418 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
419 #define CONFIG_ENV_SIZE 0x20000
420 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
421
422 #else
423
424 #define CONFIG_ENV_SPI_BUS 0
425 #define CONFIG_ENV_SPI_CS 0
426 #define CONFIG_ENV_SPI_MAX_HZ 10000000
427 #define CONFIG_ENV_SPI_MODE 0
428
429 #ifdef CONFIG_RAMBOOT_SPIFLASH
430
431 #define CONFIG_ENV_IS_IN_SPI_FLASH
432 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
433 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
434 #define CONFIG_ENV_SECT_SIZE 0x1000
435
436 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
437 /* Address and size of Redundant Environment Sector */
438 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
439 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
440 #endif
441
442 #elif defined(CONFIG_RAMBOOT_SDCARD)
443 #define CONFIG_ENV_IS_IN_MMC
444 #define CONFIG_FSL_FIXED_MMC_LOCATION
445 #define CONFIG_ENV_SIZE 0x2000
446 #define CONFIG_SYS_MMC_ENV_DEV 0
447
448 #elif defined(CONFIG_SYS_RAMBOOT)
449 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
450 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
451 #define CONFIG_ENV_SIZE 0x2000
452
453 #else
454 #define CONFIG_ENV_IS_IN_FLASH
455 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
456 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
457 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
458 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
459 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
460 /* Address and size of Redundant Environment Sector */
461 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
462 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
463 #endif
464
465 #endif
466
467 #endif /* CONFIG_ENV_FIT_UCBOOT */
468
469 #define CONFIG_LOADS_ECHO /* echo on for serial download */
470 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
471
472 /*
473 * Command line configuration.
474 */
475 #define CONFIG_CMD_IRQ
476 #define CONFIG_CMD_PING
477 #define CONFIG_CMD_I2C
478 #define CONFIG_CMD_MII
479 #define CONFIG_CMD_DATE
480 #define CONFIG_CMD_I2C
481 #define CONFIG_CMD_IRQ
482 #define CONFIG_CMD_MII
483 #define CONFIG_CMD_PING
484 #define CONFIG_CMD_REGINFO
485 #define CONFIG_CMD_ERRATA
486 #define CONFIG_CMD_CRAMFS
487 #define CONFIG_CRAMFS_CMDLINE
488
489 /*
490 * USB
491 */
492 #define CONFIG_HAS_FSL_DR_USB
493
494 #if defined(CONFIG_HAS_FSL_DR_USB)
495 #define CONFIG_USB_EHCI
496
497 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
498
499 #ifdef CONFIG_USB_EHCI
500 #define CONFIG_CMD_USB
501 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
502 #define CONFIG_USB_EHCI_FSL
503 #define CONFIG_USB_STORAGE
504 #endif
505 #endif
506
507 #undef CONFIG_WATCHDOG /* watchdog disabled */
508
509 #ifdef CONFIG_MMC
510 #define CONFIG_FSL_ESDHC
511 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
512 #define CONFIG_CMD_MMC
513 #define CONFIG_MMC_SPI
514 #define CONFIG_CMD_MMC_SPI
515 #define CONFIG_GENERIC_MMC
516 #endif
517
518 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
519 #define CONFIG_CMD_EXT2
520 #define CONFIG_CMD_FAT
521 #define CONFIG_DOS_PARTITION
522 #endif
523
524 /* Misc Extra Settings */
525 #undef CONFIG_WATCHDOG /* watchdog disabled */
526
527 /*
528 * Miscellaneous configurable options
529 */
530 #define CONFIG_SYS_LONGHELP /* undef to save memory */
531 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
532 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
533 #if defined(CONFIG_CMD_KGDB)
534 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
535 #else
536 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
537 #endif
538 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
539 /* Print Buffer Size */
540 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
541 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
542 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
543
544 /*
545 * For booting Linux, the board info and command line data
546 * have to be in the first 64 MB of memory, since this is
547 * the maximum mapped by the Linux kernel during initialization.
548 */
549 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
550 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
551
552 #if defined(CONFIG_CMD_KGDB)
553 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
554 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
555 #endif
556
557 /*
558 * Environment Configuration
559 */
560
561 #if defined(CONFIG_TSEC_ENET)
562
563 #if defined(CONFIG_UCP1020_REV_1_2)
564 #define CONFIG_PHY_MICREL_KSZ9021
565 #elif defined(CONFIG_UCP1020_REV_1_3)
566 #define CONFIG_PHY_MICREL_KSZ9031
567 #else
568 #error "UCP1020 module revision is not defined !!!"
569 #endif
570
571 #define CONFIG_CMD_DHCP
572 #define CONFIG_BOOTP_SERVERIP
573
574 #define CONFIG_MII /* MII PHY management */
575 #define CONFIG_TSEC1_NAME "eTSEC1"
576 #define CONFIG_TSEC2_NAME "eTSEC2"
577 #define CONFIG_TSEC3_NAME "eTSEC3"
578
579 #define TSEC1_PHY_ADDR 4
580 #define TSEC2_PHY_ADDR 0
581 #define TSEC2_PHY_ADDR_SGMII 0x00
582 #define TSEC3_PHY_ADDR 6
583
584 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
585 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
586 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
587
588 #define TSEC1_PHYIDX 0
589 #define TSEC2_PHYIDX 0
590 #define TSEC3_PHYIDX 0
591
592 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
593
594 #endif
595
596 #define CONFIG_HOSTNAME UCP1020
597 #define CONFIG_ROOTPATH "/opt/nfsroot"
598 #define CONFIG_BOOTFILE "uImage"
599 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
600
601 /* default location for tftp and bootm */
602 #define CONFIG_LOADADDR 1000000
603
604 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
605
606 #define CONFIG_BAUDRATE 115200
607
608 #if defined(CONFIG_DONGLE)
609
610 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
611 #define CONFIG_EXTRA_ENV_SETTINGS \
612 "bootcmd=run prog_spi_mbrbootcramfs\0" \
613 "bootfile=uImage\0" \
614 "consoledev=ttyS0\0" \
615 "cramfsfile=image.cramfs\0" \
616 "dtbaddr=0x00c00000\0" \
617 "dtbfile=image.dtb\0" \
618 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
619 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
620 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
621 "fileaddr=0x01000000\0" \
622 "filesize=0x00080000\0" \
623 "flashmbr=sf probe 0; " \
624 "tftp $loadaddr $mbr; " \
625 "sf erase $mbr_offset +$filesize; " \
626 "sf write $loadaddr $mbr_offset $filesize\0" \
627 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
628 "protect off $nor_recoveryaddr +$filesize; " \
629 "erase $nor_recoveryaddr +$filesize; " \
630 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
631 "protect on $nor_recoveryaddr +$filesize\0 " \
632 "flashuboot=tftp $ubootaddr $ubootfile; " \
633 "protect off $nor_ubootaddr +$filesize; " \
634 "erase $nor_ubootaddr +$filesize; " \
635 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
636 "protect on $nor_ubootaddr +$filesize\0 " \
637 "flashworking=tftp $workingaddr $cramfsfile; " \
638 "protect off $nor_workingaddr +$filesize; " \
639 "erase $nor_workingaddr +$filesize; " \
640 "cp.b $workingaddr $nor_workingaddr $filesize; " \
641 "protect on $nor_workingaddr +$filesize\0 " \
642 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
643 "kerneladdr=0x01100000\0" \
644 "kernelfile=uImage\0" \
645 "loadaddr=0x01000000\0" \
646 "mbr=uCP1020d.mbr\0" \
647 "mbr_offset=0x00000000\0" \
648 "mmbr=uCP1020Quiet.mbr\0" \
649 "mmcpart=0:2\0" \
650 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
651 "mmc erase 1 1; " \
652 "mmc write $loadaddr 1 1\0" \
653 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
654 "mmc erase 0x40 0x400; " \
655 "mmc write $loadaddr 0x40 0x400\0" \
656 "netdev=eth0\0" \
657 "nor_recoveryaddr=0xEC0A0000\0" \
658 "nor_ubootaddr=0xEFF80000\0" \
659 "nor_workingaddr=0xECFA0000\0" \
660 "norbootrecovery=setenv bootargs $recoverybootargs" \
661 " console=$consoledev,$baudrate $othbootargs; " \
662 "run norloadrecovery; " \
663 "bootm $kerneladdr - $dtbaddr\0" \
664 "norbootworking=setenv bootargs $workingbootargs" \
665 " console=$consoledev,$baudrate $othbootargs; " \
666 "run norloadworking; " \
667 "bootm $kerneladdr - $dtbaddr\0" \
668 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
669 "setenv cramfsaddr $nor_recoveryaddr; " \
670 "cramfsload $dtbaddr $dtbfile; " \
671 "cramfsload $kerneladdr $kernelfile\0" \
672 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
673 "setenv cramfsaddr $nor_workingaddr; " \
674 "cramfsload $dtbaddr $dtbfile; " \
675 "cramfsload $kerneladdr $kernelfile\0" \
676 "prog_spi_mbr=run spi__mbr\0" \
677 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
678 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
679 "run spi__cramfs\0" \
680 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
681 " console=$consoledev,$baudrate $othbootargs; " \
682 "tftp $rootfsaddr $rootfsfile; " \
683 "tftp $loadaddr $kernelfile; " \
684 "tftp $dtbaddr $dtbfile; " \
685 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
686 "ramdisk_size=120000\0" \
687 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
688 "recoveryaddr=0x02F00000\0" \
689 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
690 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
691 "mw.l 0xffe0f008 0x00400000\0" \
692 "rootfsaddr=0x02F00000\0" \
693 "rootfsfile=rootfs.ext2.gz.uboot\0" \
694 "rootpath=/opt/nfsroot\0" \
695 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
696 "protect off 0xeC000000 +$filesize; " \
697 "erase 0xEC000000 +$filesize; " \
698 "cp.b $loadaddr 0xEC000000 $filesize; " \
699 "cmp.b $loadaddr 0xEC000000 $filesize; " \
700 "protect on 0xeC000000 +$filesize\0" \
701 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
702 "protect off 0xeFF80000 +$filesize; " \
703 "erase 0xEFF80000 +$filesize; " \
704 "cp.b $loadaddr 0xEFF80000 $filesize; " \
705 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
706 "protect on 0xeFF80000 +$filesize\0" \
707 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
708 "sf probe 0; sf erase 0x8000 +$filesize; " \
709 "sf write $loadaddr 0x8000 $filesize\0" \
710 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
711 "protect off 0xec0a0000 +$filesize; " \
712 "erase 0xeC0A0000 +$filesize; " \
713 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
714 "protect on 0xec0a0000 +$filesize\0" \
715 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
716 "sf probe 1; sf erase 0 +$filesize; " \
717 "sf write $loadaddr 0 $filesize\0" \
718 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
719 "sf probe 0; sf erase 0 +$filesize; " \
720 "sf write $loadaddr 0 $filesize\0" \
721 "tftpflash=tftpboot $loadaddr $uboot; " \
722 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
723 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
724 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
725 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
726 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
727 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
728 "ubootaddr=0x01000000\0" \
729 "ubootfile=u-boot.bin\0" \
730 "ubootd=u-boot4dongle.bin\0" \
731 "upgrade=run flashworking\0" \
732 "usb_phy_type=ulpi\0 " \
733 "workingaddr=0x02F00000\0" \
734 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
735
736 #else
737
738 #if defined(CONFIG_UCP1020T1)
739
740 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
741 #define CONFIG_EXTRA_ENV_SETTINGS \
742 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
743 "bootfile=uImage\0" \
744 "consoledev=ttyS0\0" \
745 "cramfsfile=image.cramfs\0" \
746 "dtbaddr=0x00c00000\0" \
747 "dtbfile=image.dtb\0" \
748 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
749 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
750 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
751 "fileaddr=0x01000000\0" \
752 "filesize=0x00080000\0" \
753 "flashmbr=sf probe 0; " \
754 "tftp $loadaddr $mbr; " \
755 "sf erase $mbr_offset +$filesize; " \
756 "sf write $loadaddr $mbr_offset $filesize\0" \
757 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
758 "protect off $nor_recoveryaddr +$filesize; " \
759 "erase $nor_recoveryaddr +$filesize; " \
760 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
761 "protect on $nor_recoveryaddr +$filesize\0 " \
762 "flashuboot=tftp $ubootaddr $ubootfile; " \
763 "protect off $nor_ubootaddr +$filesize; " \
764 "erase $nor_ubootaddr +$filesize; " \
765 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
766 "protect on $nor_ubootaddr +$filesize\0 " \
767 "flashworking=tftp $workingaddr $cramfsfile; " \
768 "protect off $nor_workingaddr +$filesize; " \
769 "erase $nor_workingaddr +$filesize; " \
770 "cp.b $workingaddr $nor_workingaddr $filesize; " \
771 "protect on $nor_workingaddr +$filesize\0 " \
772 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
773 "kerneladdr=0x01100000\0" \
774 "kernelfile=uImage\0" \
775 "loadaddr=0x01000000\0" \
776 "mbr=uCP1020.mbr\0" \
777 "mbr_offset=0x00000000\0" \
778 "netdev=eth0\0" \
779 "nor_recoveryaddr=0xEC0A0000\0" \
780 "nor_ubootaddr=0xEFF80000\0" \
781 "nor_workingaddr=0xECFA0000\0" \
782 "norbootrecovery=setenv bootargs $recoverybootargs" \
783 " console=$consoledev,$baudrate $othbootargs; " \
784 "run norloadrecovery; " \
785 "bootm $kerneladdr - $dtbaddr\0" \
786 "norbootworking=setenv bootargs $workingbootargs" \
787 " console=$consoledev,$baudrate $othbootargs; " \
788 "run norloadworking; " \
789 "bootm $kerneladdr - $dtbaddr\0" \
790 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
791 "setenv cramfsaddr $nor_recoveryaddr; " \
792 "cramfsload $dtbaddr $dtbfile; " \
793 "cramfsload $kerneladdr $kernelfile\0" \
794 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
795 "setenv cramfsaddr $nor_workingaddr; " \
796 "cramfsload $dtbaddr $dtbfile; " \
797 "cramfsload $kerneladdr $kernelfile\0" \
798 "othbootargs=quiet\0" \
799 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
800 " console=$consoledev,$baudrate $othbootargs; " \
801 "tftp $rootfsaddr $rootfsfile; " \
802 "tftp $loadaddr $kernelfile; " \
803 "tftp $dtbaddr $dtbfile; " \
804 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
805 "ramdisk_size=120000\0" \
806 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
807 "recoveryaddr=0x02F00000\0" \
808 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
809 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
810 "mw.l 0xffe0f008 0x00400000\0" \
811 "rootfsaddr=0x02F00000\0" \
812 "rootfsfile=rootfs.ext2.gz.uboot\0" \
813 "rootpath=/opt/nfsroot\0" \
814 "silent=1\0" \
815 "tftpflash=tftpboot $loadaddr $uboot; " \
816 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
817 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
818 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
819 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
820 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
821 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
822 "ubootaddr=0x01000000\0" \
823 "ubootfile=u-boot.bin\0" \
824 "upgrade=run flashworking\0" \
825 "workingaddr=0x02F00000\0" \
826 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
827
828 #else /* For Arcturus Modules */
829
830 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
831 #define CONFIG_EXTRA_ENV_SETTINGS \
832 "bootcmd=run norkernel\0" \
833 "bootfile=uImage\0" \
834 "consoledev=ttyS0\0" \
835 "dtbaddr=0x00c00000\0" \
836 "dtbfile=image.dtb\0" \
837 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
838 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
839 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
840 "fileaddr=0x01000000\0" \
841 "filesize=0x00080000\0" \
842 "flashmbr=sf probe 0; " \
843 "tftp $loadaddr $mbr; " \
844 "sf erase $mbr_offset +$filesize; " \
845 "sf write $loadaddr $mbr_offset $filesize\0" \
846 "flashuboot=tftp $loadaddr $ubootfile; " \
847 "protect off $nor_ubootaddr0 +$filesize; " \
848 "erase $nor_ubootaddr0 +$filesize; " \
849 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
850 "protect on $nor_ubootaddr0 +$filesize; " \
851 "protect off $nor_ubootaddr1 +$filesize; " \
852 "erase $nor_ubootaddr1 +$filesize; " \
853 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
854 "protect on $nor_ubootaddr1 +$filesize\0 " \
855 "format0=protect off $part0base +$part0size; " \
856 "erase $part0base +$part0size\0" \
857 "format1=protect off $part1base +$part1size; " \
858 "erase $part1base +$part1size\0" \
859 "format2=protect off $part2base +$part2size; " \
860 "erase $part2base +$part2size\0" \
861 "format3=protect off $part3base +$part3size; " \
862 "erase $part3base +$part3size\0" \
863 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
864 "kerneladdr=0x01100000\0" \
865 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
866 "kernelfile=uImage\0" \
867 "loadaddr=0x01000000\0" \
868 "mbr=uCP1020.mbr\0" \
869 "mbr_offset=0x00000000\0" \
870 "netdev=eth0\0" \
871 "nor_ubootaddr0=0xEC000000\0" \
872 "nor_ubootaddr1=0xEFF80000\0" \
873 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
874 "run norkernelload; " \
875 "bootm $kerneladdr - $dtbaddr\0" \
876 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
877 "setenv cramfsaddr $part0base; " \
878 "cramfsload $dtbaddr $dtbfile; " \
879 "cramfsload $kerneladdr $kernelfile\0" \
880 "part0base=0xEC100000\0" \
881 "part0size=0x00700000\0" \
882 "part1base=0xEC800000\0" \
883 "part1size=0x02000000\0" \
884 "part2base=0xEE800000\0" \
885 "part2size=0x00800000\0" \
886 "part3base=0xEF000000\0" \
887 "part3size=0x00F80000\0" \
888 "partENVbase=0xEC080000\0" \
889 "partENVsize=0x00080000\0" \
890 "program0=tftp part0-000000.bin; " \
891 "protect off $part0base +$filesize; " \
892 "erase $part0base +$filesize; " \
893 "cp.b $loadaddr $part0base $filesize; " \
894 "echo Verifying...; " \
895 "cmp.b $loadaddr $part0base $filesize\0" \
896 "program1=tftp part1-000000.bin; " \
897 "protect off $part1base +$filesize; " \
898 "erase $part1base +$filesize; " \
899 "cp.b $loadaddr $part1base $filesize; " \
900 "echo Verifying...; " \
901 "cmp.b $loadaddr $part1base $filesize\0" \
902 "program2=tftp part2-000000.bin; " \
903 "protect off $part2base +$filesize; " \
904 "erase $part2base +$filesize; " \
905 "cp.b $loadaddr $part2base $filesize; " \
906 "echo Verifying...; " \
907 "cmp.b $loadaddr $part2base $filesize\0" \
908 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
909 " console=$consoledev,$baudrate $othbootargs; " \
910 "tftp $rootfsaddr $rootfsfile; " \
911 "tftp $loadaddr $kernelfile; " \
912 "tftp $dtbaddr $dtbfile; " \
913 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
914 "ramdisk_size=120000\0" \
915 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
916 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
917 "mw.l 0xffe0f008 0x00400000\0" \
918 "rootfsaddr=0x02F00000\0" \
919 "rootfsfile=rootfs.ext2.gz.uboot\0" \
920 "rootpath=/opt/nfsroot\0" \
921 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
922 "sf probe 0; sf erase 0 +$filesize; " \
923 "sf write $loadaddr 0 $filesize\0" \
924 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
925 "protect off 0xeC000000 +$filesize; " \
926 "erase 0xEC000000 +$filesize; " \
927 "cp.b $loadaddr 0xEC000000 $filesize; " \
928 "cmp.b $loadaddr 0xEC000000 $filesize; " \
929 "protect on 0xeC000000 +$filesize\0" \
930 "tftpflash=tftpboot $loadaddr $uboot; " \
931 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
932 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
933 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
934 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
935 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
936 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
937 "ubootfile=u-boot.bin\0" \
938 "upgrade=run flashuboot\0" \
939 "usb_phy_type=ulpi\0 " \
940 "boot_nfs= " \
941 "setenv bootargs root=/dev/nfs rw " \
942 "nfsroot=$serverip:$rootpath " \
943 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
944 "console=$consoledev,$baudrate $othbootargs;" \
945 "tftp $loadaddr $bootfile;" \
946 "tftp $fdtaddr $fdtfile;" \
947 "bootm $loadaddr - $fdtaddr\0" \
948 "boot_hd = " \
949 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
950 "console=$consoledev,$baudrate $othbootargs;" \
951 "usb start;" \
952 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
953 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
954 "bootm $loadaddr - $fdtaddr\0" \
955 "boot_usb_fat = " \
956 "setenv bootargs root=/dev/ram rw " \
957 "console=$consoledev,$baudrate $othbootargs " \
958 "ramdisk_size=$ramdisk_size;" \
959 "usb start;" \
960 "fatload usb 0:2 $loadaddr $bootfile;" \
961 "fatload usb 0:2 $fdtaddr $fdtfile;" \
962 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
963 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
964 "boot_usb_ext2 = " \
965 "setenv bootargs root=/dev/ram rw " \
966 "console=$consoledev,$baudrate $othbootargs " \
967 "ramdisk_size=$ramdisk_size;" \
968 "usb start;" \
969 "ext2load usb 0:4 $loadaddr $bootfile;" \
970 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
971 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
972 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
973 "boot_nor = " \
974 "setenv bootargs root=/dev/$jffs2nor rw " \
975 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
976 "bootm $norbootaddr - $norfdtaddr\0 " \
977 "boot_ram = " \
978 "setenv bootargs root=/dev/ram rw " \
979 "console=$consoledev,$baudrate $othbootargs " \
980 "ramdisk_size=$ramdisk_size;" \
981 "tftp $ramdiskaddr $ramdiskfile;" \
982 "tftp $loadaddr $bootfile;" \
983 "tftp $fdtaddr $fdtfile;" \
984 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
985
986 #endif
987 #endif
988
989 #endif /* __CONFIG_H */
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