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[people/ms/u-boot.git] / include / configs / UCP1020.h
1 /*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_FSL_ELBC
18 #define CONFIG_PCI
19 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
20 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
21 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
22 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
23 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
24 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
25
26 #if defined(CONFIG_TARTGET_UCP1020T1)
27
28 #define CONFIG_UCP1020_REV_1_3
29
30 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
31 #define CONFIG_P1020
32
33 #define CONFIG_TSEC_ENET
34 #define CONFIG_TSEC1
35 #define CONFIG_TSEC3
36 #define CONFIG_HAS_ETH0
37 #define CONFIG_HAS_ETH1
38 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
39 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
40 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
41 #define CONFIG_IPADDR 10.80.41.229
42 #define CONFIG_SERVERIP 10.80.41.227
43 #define CONFIG_NETMASK 255.255.252.0
44 #define CONFIG_ETHPRIME "eTSEC3"
45
46 #ifndef CONFIG_SPI_FLASH
47 #endif
48 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
49
50 #define CONFIG_MMC
51 #define CONFIG_SYS_L2_SIZE (256 << 10)
52
53 #define CONFIG_LAST_STAGE_INIT
54
55 #if !defined(CONFIG_DONGLE)
56 #define CONFIG_SILENT_CONSOLE
57 #endif
58
59 #endif
60
61 #if defined(CONFIG_TARGET_UCP1020)
62
63 #define CONFIG_UCP1020
64 #define CONFIG_UCP1020_REV_1_3
65
66 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
67 #define CONFIG_P1020
68
69 #define CONFIG_TSEC_ENET
70 #define CONFIG_TSEC1
71 #define CONFIG_TSEC2
72 #define CONFIG_TSEC3
73 #define CONFIG_HAS_ETH0
74 #define CONFIG_HAS_ETH1
75 #define CONFIG_HAS_ETH2
76 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
77 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
78 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
79 #define CONFIG_IPADDR 192.168.1.81
80 #define CONFIG_IPADDR1 192.168.1.82
81 #define CONFIG_IPADDR2 192.168.1.83
82 #define CONFIG_SERVERIP 192.168.1.80
83 #define CONFIG_GATEWAYIP 102.168.1.1
84 #define CONFIG_NETMASK 255.255.255.0
85 #define CONFIG_ETHPRIME "eTSEC1"
86
87 #ifndef CONFIG_SPI_FLASH
88 #endif
89 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
90
91 #define CONFIG_MMC
92 #define CONFIG_SYS_L2_SIZE (256 << 10)
93
94 #define CONFIG_LAST_STAGE_INIT
95
96 #endif
97
98 #ifdef CONFIG_SDCARD
99 #define CONFIG_RAMBOOT_SDCARD
100 #define CONFIG_SYS_RAMBOOT
101 #define CONFIG_SYS_EXTRA_ENV_RELOC
102 #define CONFIG_SYS_TEXT_BASE 0x11000000
103 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
104 #endif
105
106 #ifdef CONFIG_SPIFLASH
107 #define CONFIG_RAMBOOT_SPIFLASH
108 #define CONFIG_SYS_RAMBOOT
109 #define CONFIG_SYS_EXTRA_ENV_RELOC
110 #define CONFIG_SYS_TEXT_BASE 0x11000000
111 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
112 #endif
113
114 #ifndef CONFIG_SYS_TEXT_BASE
115 #define CONFIG_SYS_TEXT_BASE 0xeff80000
116 #endif
117 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
118
119 #ifndef CONFIG_RESET_VECTOR_ADDRESS
120 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
121 #endif
122
123 #ifndef CONFIG_SYS_MONITOR_BASE
124 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
125 #endif
126
127 /* High Level Configuration Options */
128 #define CONFIG_BOOKE
129 #define CONFIG_E500
130 /* #define CONFIG_MPC85xx */
131
132 #define CONFIG_MP
133
134 #define CONFIG_FSL_LAW
135
136 #define CONFIG_ENV_OVERWRITE
137
138 #define CONFIG_CMD_SATA
139 #define CONFIG_SATA_SIL
140 #define CONFIG_SYS_SATA_MAX_DEVICE 2
141 #define CONFIG_LIBATA
142 #define CONFIG_LBA48
143
144 #define CONFIG_SYS_CLK_FREQ 66666666
145 #define CONFIG_DDR_CLK_FREQ 66666666
146
147 #define CONFIG_HWCONFIG
148
149 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
150 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
151 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
152 /*
153 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
154 * there will be one entry in this array for each two (dummy) sensors in
155 * CONFIG_DTT_SENSORS.
156 *
157 * For uCP1020 module:
158 * - only one ADM1021/NCT72
159 * - i2c addr 0x41
160 * - conversion rate 0x02 = 0.25 conversions/second
161 * - ALERT output disabled
162 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
163 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
164 */
165 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
166 0x02, 0, 1, 0, 85, 1, 0, 85} }
167
168 #define CONFIG_CMD_DTT
169
170 /*
171 * These can be toggled for performance analysis, otherwise use default.
172 */
173 #define CONFIG_L2_CACHE
174 #define CONFIG_BTB
175
176 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
177
178 #define CONFIG_ENABLE_36BIT_PHYS
179
180 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
181 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
182 #define CONFIG_PANIC_HANG /* do not reset board on panic */
183
184 #define CONFIG_SYS_CCSRBAR 0xffe00000
185 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
186
187 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
188 SPL code*/
189 #ifdef CONFIG_SPL_BUILD
190 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
191 #endif
192
193 /* DDR Setup */
194 #define CONFIG_DDR_ECC_ENABLE
195 #define CONFIG_SYS_FSL_DDR3
196 #ifndef CONFIG_DDR_ECC_ENABLE
197 #define CONFIG_SYS_DDR_RAW_TIMING
198 #define CONFIG_DDR_SPD
199 #endif
200 #define CONFIG_SYS_SPD_BUS_NUM 1
201 #undef CONFIG_FSL_DDR_INTERACTIVE
202
203 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
204 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
205 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
206 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
207 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
208
209 #define CONFIG_NUM_DDR_CONTROLLERS 1
210 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
211
212 /* Default settings for DDR3 */
213 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
214 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
215 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
216 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
217 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
218 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
219
220 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
221 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
222 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
223 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
224
225 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
226 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
227 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
228 #define CONFIG_SYS_DDR_RCW_1 0x00000000
229 #define CONFIG_SYS_DDR_RCW_2 0x00000000
230 #ifdef CONFIG_DDR_ECC_ENABLE
231 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
232 #else
233 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
234 #endif
235 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
236 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
237 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
238
239 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
240 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
241 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
242 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
243 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
244 #define CONFIG_SYS_DDR_MODE_1 0x40461520
245 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
246 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
247
248 #undef CONFIG_CLOCKS_IN_MHZ
249
250 /*
251 * Memory map
252 *
253 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
254 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
255 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
256 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
257 * (early boot only)
258 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
259 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
260 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
261 */
262
263 /*
264 * Local Bus Definitions
265 */
266 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
267 #define CONFIG_SYS_FLASH_BASE 0xec000000
268
269 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
270
271 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
272 | BR_PS_16 | BR_V)
273
274 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
275
276 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
277 #define CONFIG_SYS_FLASH_QUIET_TEST
278 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
279
280 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
281
282 #undef CONFIG_SYS_FLASH_CHECKSUM
283 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
284 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
285
286 #define CONFIG_FLASH_CFI_DRIVER
287 #define CONFIG_SYS_FLASH_CFI
288 #define CONFIG_SYS_FLASH_EMPTY_INFO
289 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
290
291 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
292
293 #define CONFIG_SYS_INIT_RAM_LOCK
294 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
295 /* Initial L1 address */
296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
299 /* Size of used area in RAM */
300 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
301
302 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
303 GENERATED_GBL_DATA_SIZE)
304 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
305
306 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
307 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
308
309 #define CONFIG_SYS_PMC_BASE 0xff980000
310 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
311 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
312 BR_PS_8 | BR_V)
313 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
314 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
315 OR_GPCM_EAD)
316
317 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
318 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
319 #ifdef CONFIG_NAND_FSL_ELBC
320 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
321 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
322 #endif
323
324 /* Serial Port - controlled on board with jumper J8
325 * open - index 2
326 * shorted - index 1
327 */
328 #define CONFIG_CONS_INDEX 1
329 #undef CONFIG_SERIAL_SOFTWARE_FIFO
330 #define CONFIG_SYS_NS16550_SERIAL
331 #define CONFIG_SYS_NS16550_REG_SIZE 1
332 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
333 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
334 #define CONFIG_NS16550_MIN_FUNCTIONS
335 #endif
336
337 #define CONFIG_SYS_BAUDRATE_TABLE \
338 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
339
340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
342
343 /* I2C */
344 #define CONFIG_SYS_I2C
345 #define CONFIG_SYS_I2C_FSL
346 #define CONFIG_SYS_FSL_I2C_SPEED 400000
347 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
348 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
349 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
350 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
351 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
352 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
353 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
354
355 #define CONFIG_RTC_DS1337
356 #define CONFIG_SYS_RTC_DS1337_NOOSC
357 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
358 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
359 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
360 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
361
362 /*
363 * eSPI - Enhanced SPI
364 */
365 #define CONFIG_HARD_SPI
366
367 #define CONFIG_SF_DEFAULT_SPEED 10000000
368 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
369
370 #if defined(CONFIG_PCI)
371 /*
372 * General PCI
373 * Memory space is mapped 1-1, but I/O space must start from 0.
374 */
375
376 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
377 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
378 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
379 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
380 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
381 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
382 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
383 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
384 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
385 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
386
387 /* controller 1, Slot 2, tgtid 1, Base address a000 */
388 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
389 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
390 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
391 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
392 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
393 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
394 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
395 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
396 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
397
398 #define CONFIG_PCI_PNP /* do pci plug-and-play */
399 #define CONFIG_CMD_PCI
400
401 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
402 #define CONFIG_DOS_PARTITION
403 #endif /* CONFIG_PCI */
404
405 /*
406 * Environment
407 */
408 #ifdef CONFIG_ENV_FIT_UCBOOT
409
410 #define CONFIG_ENV_IS_IN_FLASH
411 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
412 #define CONFIG_ENV_SIZE 0x20000
413 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
414
415 #else
416
417 #define CONFIG_ENV_SPI_BUS 0
418 #define CONFIG_ENV_SPI_CS 0
419 #define CONFIG_ENV_SPI_MAX_HZ 10000000
420 #define CONFIG_ENV_SPI_MODE 0
421
422 #ifdef CONFIG_RAMBOOT_SPIFLASH
423
424 #define CONFIG_ENV_IS_IN_SPI_FLASH
425 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
426 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
427 #define CONFIG_ENV_SECT_SIZE 0x1000
428
429 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
430 /* Address and size of Redundant Environment Sector */
431 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
432 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
433 #endif
434
435 #elif defined(CONFIG_RAMBOOT_SDCARD)
436 #define CONFIG_ENV_IS_IN_MMC
437 #define CONFIG_FSL_FIXED_MMC_LOCATION
438 #define CONFIG_ENV_SIZE 0x2000
439 #define CONFIG_SYS_MMC_ENV_DEV 0
440
441 #elif defined(CONFIG_SYS_RAMBOOT)
442 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
444 #define CONFIG_ENV_SIZE 0x2000
445
446 #else
447 #define CONFIG_ENV_IS_IN_FLASH
448 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
449 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
450 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
451 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
452 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
453 /* Address and size of Redundant Environment Sector */
454 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
455 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
456 #endif
457
458 #endif
459
460 #endif /* CONFIG_ENV_FIT_UCBOOT */
461
462 #define CONFIG_LOADS_ECHO /* echo on for serial download */
463 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
464
465 /*
466 * Command line configuration.
467 */
468 #define CONFIG_CMD_IRQ
469 #define CONFIG_CMD_DATE
470 #define CONFIG_CMD_IRQ
471 #define CONFIG_CMD_REGINFO
472 #define CONFIG_CMD_ERRATA
473 #define CONFIG_CMD_CRAMFS
474
475 /*
476 * USB
477 */
478 #define CONFIG_HAS_FSL_DR_USB
479
480 #if defined(CONFIG_HAS_FSL_DR_USB)
481 #define CONFIG_USB_EHCI
482
483 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
484
485 #ifdef CONFIG_USB_EHCI
486 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
487 #define CONFIG_USB_EHCI_FSL
488 #endif
489 #endif
490
491 #undef CONFIG_WATCHDOG /* watchdog disabled */
492
493 #ifdef CONFIG_MMC
494 #define CONFIG_FSL_ESDHC
495 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
496 #define CONFIG_MMC_SPI
497 #define CONFIG_CMD_MMC_SPI
498 #define CONFIG_GENERIC_MMC
499 #endif
500
501 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
502 #define CONFIG_DOS_PARTITION
503 #endif
504
505 /* Misc Extra Settings */
506 #undef CONFIG_WATCHDOG /* watchdog disabled */
507
508 /*
509 * Miscellaneous configurable options
510 */
511 #define CONFIG_SYS_LONGHELP /* undef to save memory */
512 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
513 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
514 #if defined(CONFIG_CMD_KGDB)
515 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
516 #else
517 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
518 #endif
519 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
520 /* Print Buffer Size */
521 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
522 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
523 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
524
525 /*
526 * For booting Linux, the board info and command line data
527 * have to be in the first 64 MB of memory, since this is
528 * the maximum mapped by the Linux kernel during initialization.
529 */
530 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
531 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
532
533 #if defined(CONFIG_CMD_KGDB)
534 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
535 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
536 #endif
537
538 /*
539 * Environment Configuration
540 */
541
542 #if defined(CONFIG_TSEC_ENET)
543
544 #if defined(CONFIG_UCP1020_REV_1_2)
545 #define CONFIG_PHY_MICREL_KSZ9021
546 #elif defined(CONFIG_UCP1020_REV_1_3)
547 #define CONFIG_PHY_MICREL_KSZ9031
548 #else
549 #error "UCP1020 module revision is not defined !!!"
550 #endif
551
552 #define CONFIG_BOOTP_SERVERIP
553
554 #define CONFIG_MII /* MII PHY management */
555 #define CONFIG_TSEC1_NAME "eTSEC1"
556 #define CONFIG_TSEC2_NAME "eTSEC2"
557 #define CONFIG_TSEC3_NAME "eTSEC3"
558
559 #define TSEC1_PHY_ADDR 4
560 #define TSEC2_PHY_ADDR 0
561 #define TSEC2_PHY_ADDR_SGMII 0x00
562 #define TSEC3_PHY_ADDR 6
563
564 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
565 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
566 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
567
568 #define TSEC1_PHYIDX 0
569 #define TSEC2_PHYIDX 0
570 #define TSEC3_PHYIDX 0
571
572 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
573
574 #endif
575
576 #define CONFIG_HOSTNAME UCP1020
577 #define CONFIG_ROOTPATH "/opt/nfsroot"
578 #define CONFIG_BOOTFILE "uImage"
579 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
580
581 /* default location for tftp and bootm */
582 #define CONFIG_LOADADDR 1000000
583
584 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
585
586 #define CONFIG_BAUDRATE 115200
587
588 #if defined(CONFIG_DONGLE)
589
590 #define CONFIG_EXTRA_ENV_SETTINGS \
591 "bootcmd=run prog_spi_mbrbootcramfs\0" \
592 "bootfile=uImage\0" \
593 "consoledev=ttyS0\0" \
594 "cramfsfile=image.cramfs\0" \
595 "dtbaddr=0x00c00000\0" \
596 "dtbfile=image.dtb\0" \
597 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
598 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
599 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
600 "fileaddr=0x01000000\0" \
601 "filesize=0x00080000\0" \
602 "flashmbr=sf probe 0; " \
603 "tftp $loadaddr $mbr; " \
604 "sf erase $mbr_offset +$filesize; " \
605 "sf write $loadaddr $mbr_offset $filesize\0" \
606 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
607 "protect off $nor_recoveryaddr +$filesize; " \
608 "erase $nor_recoveryaddr +$filesize; " \
609 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
610 "protect on $nor_recoveryaddr +$filesize\0 " \
611 "flashuboot=tftp $ubootaddr $ubootfile; " \
612 "protect off $nor_ubootaddr +$filesize; " \
613 "erase $nor_ubootaddr +$filesize; " \
614 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
615 "protect on $nor_ubootaddr +$filesize\0 " \
616 "flashworking=tftp $workingaddr $cramfsfile; " \
617 "protect off $nor_workingaddr +$filesize; " \
618 "erase $nor_workingaddr +$filesize; " \
619 "cp.b $workingaddr $nor_workingaddr $filesize; " \
620 "protect on $nor_workingaddr +$filesize\0 " \
621 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
622 "kerneladdr=0x01100000\0" \
623 "kernelfile=uImage\0" \
624 "loadaddr=0x01000000\0" \
625 "mbr=uCP1020d.mbr\0" \
626 "mbr_offset=0x00000000\0" \
627 "mmbr=uCP1020Quiet.mbr\0" \
628 "mmcpart=0:2\0" \
629 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
630 "mmc erase 1 1; " \
631 "mmc write $loadaddr 1 1\0" \
632 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
633 "mmc erase 0x40 0x400; " \
634 "mmc write $loadaddr 0x40 0x400\0" \
635 "netdev=eth0\0" \
636 "nor_recoveryaddr=0xEC0A0000\0" \
637 "nor_ubootaddr=0xEFF80000\0" \
638 "nor_workingaddr=0xECFA0000\0" \
639 "norbootrecovery=setenv bootargs $recoverybootargs" \
640 " console=$consoledev,$baudrate $othbootargs; " \
641 "run norloadrecovery; " \
642 "bootm $kerneladdr - $dtbaddr\0" \
643 "norbootworking=setenv bootargs $workingbootargs" \
644 " console=$consoledev,$baudrate $othbootargs; " \
645 "run norloadworking; " \
646 "bootm $kerneladdr - $dtbaddr\0" \
647 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
648 "setenv cramfsaddr $nor_recoveryaddr; " \
649 "cramfsload $dtbaddr $dtbfile; " \
650 "cramfsload $kerneladdr $kernelfile\0" \
651 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
652 "setenv cramfsaddr $nor_workingaddr; " \
653 "cramfsload $dtbaddr $dtbfile; " \
654 "cramfsload $kerneladdr $kernelfile\0" \
655 "prog_spi_mbr=run spi__mbr\0" \
656 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
657 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
658 "run spi__cramfs\0" \
659 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
660 " console=$consoledev,$baudrate $othbootargs; " \
661 "tftp $rootfsaddr $rootfsfile; " \
662 "tftp $loadaddr $kernelfile; " \
663 "tftp $dtbaddr $dtbfile; " \
664 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
665 "ramdisk_size=120000\0" \
666 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
667 "recoveryaddr=0x02F00000\0" \
668 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
669 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
670 "mw.l 0xffe0f008 0x00400000\0" \
671 "rootfsaddr=0x02F00000\0" \
672 "rootfsfile=rootfs.ext2.gz.uboot\0" \
673 "rootpath=/opt/nfsroot\0" \
674 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
675 "protect off 0xeC000000 +$filesize; " \
676 "erase 0xEC000000 +$filesize; " \
677 "cp.b $loadaddr 0xEC000000 $filesize; " \
678 "cmp.b $loadaddr 0xEC000000 $filesize; " \
679 "protect on 0xeC000000 +$filesize\0" \
680 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
681 "protect off 0xeFF80000 +$filesize; " \
682 "erase 0xEFF80000 +$filesize; " \
683 "cp.b $loadaddr 0xEFF80000 $filesize; " \
684 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
685 "protect on 0xeFF80000 +$filesize\0" \
686 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
687 "sf probe 0; sf erase 0x8000 +$filesize; " \
688 "sf write $loadaddr 0x8000 $filesize\0" \
689 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
690 "protect off 0xec0a0000 +$filesize; " \
691 "erase 0xeC0A0000 +$filesize; " \
692 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
693 "protect on 0xec0a0000 +$filesize\0" \
694 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
695 "sf probe 1; sf erase 0 +$filesize; " \
696 "sf write $loadaddr 0 $filesize\0" \
697 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
698 "sf probe 0; sf erase 0 +$filesize; " \
699 "sf write $loadaddr 0 $filesize\0" \
700 "tftpflash=tftpboot $loadaddr $uboot; " \
701 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
702 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
703 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
704 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
705 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
706 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
707 "ubootaddr=0x01000000\0" \
708 "ubootfile=u-boot.bin\0" \
709 "ubootd=u-boot4dongle.bin\0" \
710 "upgrade=run flashworking\0" \
711 "usb_phy_type=ulpi\0 " \
712 "workingaddr=0x02F00000\0" \
713 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
714
715 #else
716
717 #if defined(CONFIG_UCP1020T1)
718
719 #define CONFIG_EXTRA_ENV_SETTINGS \
720 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
721 "bootfile=uImage\0" \
722 "consoledev=ttyS0\0" \
723 "cramfsfile=image.cramfs\0" \
724 "dtbaddr=0x00c00000\0" \
725 "dtbfile=image.dtb\0" \
726 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
727 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
728 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
729 "fileaddr=0x01000000\0" \
730 "filesize=0x00080000\0" \
731 "flashmbr=sf probe 0; " \
732 "tftp $loadaddr $mbr; " \
733 "sf erase $mbr_offset +$filesize; " \
734 "sf write $loadaddr $mbr_offset $filesize\0" \
735 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
736 "protect off $nor_recoveryaddr +$filesize; " \
737 "erase $nor_recoveryaddr +$filesize; " \
738 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
739 "protect on $nor_recoveryaddr +$filesize\0 " \
740 "flashuboot=tftp $ubootaddr $ubootfile; " \
741 "protect off $nor_ubootaddr +$filesize; " \
742 "erase $nor_ubootaddr +$filesize; " \
743 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
744 "protect on $nor_ubootaddr +$filesize\0 " \
745 "flashworking=tftp $workingaddr $cramfsfile; " \
746 "protect off $nor_workingaddr +$filesize; " \
747 "erase $nor_workingaddr +$filesize; " \
748 "cp.b $workingaddr $nor_workingaddr $filesize; " \
749 "protect on $nor_workingaddr +$filesize\0 " \
750 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
751 "kerneladdr=0x01100000\0" \
752 "kernelfile=uImage\0" \
753 "loadaddr=0x01000000\0" \
754 "mbr=uCP1020.mbr\0" \
755 "mbr_offset=0x00000000\0" \
756 "netdev=eth0\0" \
757 "nor_recoveryaddr=0xEC0A0000\0" \
758 "nor_ubootaddr=0xEFF80000\0" \
759 "nor_workingaddr=0xECFA0000\0" \
760 "norbootrecovery=setenv bootargs $recoverybootargs" \
761 " console=$consoledev,$baudrate $othbootargs; " \
762 "run norloadrecovery; " \
763 "bootm $kerneladdr - $dtbaddr\0" \
764 "norbootworking=setenv bootargs $workingbootargs" \
765 " console=$consoledev,$baudrate $othbootargs; " \
766 "run norloadworking; " \
767 "bootm $kerneladdr - $dtbaddr\0" \
768 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
769 "setenv cramfsaddr $nor_recoveryaddr; " \
770 "cramfsload $dtbaddr $dtbfile; " \
771 "cramfsload $kerneladdr $kernelfile\0" \
772 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
773 "setenv cramfsaddr $nor_workingaddr; " \
774 "cramfsload $dtbaddr $dtbfile; " \
775 "cramfsload $kerneladdr $kernelfile\0" \
776 "othbootargs=quiet\0" \
777 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
778 " console=$consoledev,$baudrate $othbootargs; " \
779 "tftp $rootfsaddr $rootfsfile; " \
780 "tftp $loadaddr $kernelfile; " \
781 "tftp $dtbaddr $dtbfile; " \
782 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
783 "ramdisk_size=120000\0" \
784 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
785 "recoveryaddr=0x02F00000\0" \
786 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
787 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
788 "mw.l 0xffe0f008 0x00400000\0" \
789 "rootfsaddr=0x02F00000\0" \
790 "rootfsfile=rootfs.ext2.gz.uboot\0" \
791 "rootpath=/opt/nfsroot\0" \
792 "silent=1\0" \
793 "tftpflash=tftpboot $loadaddr $uboot; " \
794 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
795 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
796 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
797 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
798 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
799 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
800 "ubootaddr=0x01000000\0" \
801 "ubootfile=u-boot.bin\0" \
802 "upgrade=run flashworking\0" \
803 "workingaddr=0x02F00000\0" \
804 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
805
806 #else /* For Arcturus Modules */
807
808 #define CONFIG_EXTRA_ENV_SETTINGS \
809 "bootcmd=run norkernel\0" \
810 "bootfile=uImage\0" \
811 "consoledev=ttyS0\0" \
812 "dtbaddr=0x00c00000\0" \
813 "dtbfile=image.dtb\0" \
814 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
815 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
816 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
817 "fileaddr=0x01000000\0" \
818 "filesize=0x00080000\0" \
819 "flashmbr=sf probe 0; " \
820 "tftp $loadaddr $mbr; " \
821 "sf erase $mbr_offset +$filesize; " \
822 "sf write $loadaddr $mbr_offset $filesize\0" \
823 "flashuboot=tftp $loadaddr $ubootfile; " \
824 "protect off $nor_ubootaddr0 +$filesize; " \
825 "erase $nor_ubootaddr0 +$filesize; " \
826 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
827 "protect on $nor_ubootaddr0 +$filesize; " \
828 "protect off $nor_ubootaddr1 +$filesize; " \
829 "erase $nor_ubootaddr1 +$filesize; " \
830 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
831 "protect on $nor_ubootaddr1 +$filesize\0 " \
832 "format0=protect off $part0base +$part0size; " \
833 "erase $part0base +$part0size\0" \
834 "format1=protect off $part1base +$part1size; " \
835 "erase $part1base +$part1size\0" \
836 "format2=protect off $part2base +$part2size; " \
837 "erase $part2base +$part2size\0" \
838 "format3=protect off $part3base +$part3size; " \
839 "erase $part3base +$part3size\0" \
840 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
841 "kerneladdr=0x01100000\0" \
842 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
843 "kernelfile=uImage\0" \
844 "loadaddr=0x01000000\0" \
845 "mbr=uCP1020.mbr\0" \
846 "mbr_offset=0x00000000\0" \
847 "netdev=eth0\0" \
848 "nor_ubootaddr0=0xEC000000\0" \
849 "nor_ubootaddr1=0xEFF80000\0" \
850 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
851 "run norkernelload; " \
852 "bootm $kerneladdr - $dtbaddr\0" \
853 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
854 "setenv cramfsaddr $part0base; " \
855 "cramfsload $dtbaddr $dtbfile; " \
856 "cramfsload $kerneladdr $kernelfile\0" \
857 "part0base=0xEC100000\0" \
858 "part0size=0x00700000\0" \
859 "part1base=0xEC800000\0" \
860 "part1size=0x02000000\0" \
861 "part2base=0xEE800000\0" \
862 "part2size=0x00800000\0" \
863 "part3base=0xEF000000\0" \
864 "part3size=0x00F80000\0" \
865 "partENVbase=0xEC080000\0" \
866 "partENVsize=0x00080000\0" \
867 "program0=tftp part0-000000.bin; " \
868 "protect off $part0base +$filesize; " \
869 "erase $part0base +$filesize; " \
870 "cp.b $loadaddr $part0base $filesize; " \
871 "echo Verifying...; " \
872 "cmp.b $loadaddr $part0base $filesize\0" \
873 "program1=tftp part1-000000.bin; " \
874 "protect off $part1base +$filesize; " \
875 "erase $part1base +$filesize; " \
876 "cp.b $loadaddr $part1base $filesize; " \
877 "echo Verifying...; " \
878 "cmp.b $loadaddr $part1base $filesize\0" \
879 "program2=tftp part2-000000.bin; " \
880 "protect off $part2base +$filesize; " \
881 "erase $part2base +$filesize; " \
882 "cp.b $loadaddr $part2base $filesize; " \
883 "echo Verifying...; " \
884 "cmp.b $loadaddr $part2base $filesize\0" \
885 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
886 " console=$consoledev,$baudrate $othbootargs; " \
887 "tftp $rootfsaddr $rootfsfile; " \
888 "tftp $loadaddr $kernelfile; " \
889 "tftp $dtbaddr $dtbfile; " \
890 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
891 "ramdisk_size=120000\0" \
892 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
893 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
894 "mw.l 0xffe0f008 0x00400000\0" \
895 "rootfsaddr=0x02F00000\0" \
896 "rootfsfile=rootfs.ext2.gz.uboot\0" \
897 "rootpath=/opt/nfsroot\0" \
898 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
899 "sf probe 0; sf erase 0 +$filesize; " \
900 "sf write $loadaddr 0 $filesize\0" \
901 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
902 "protect off 0xeC000000 +$filesize; " \
903 "erase 0xEC000000 +$filesize; " \
904 "cp.b $loadaddr 0xEC000000 $filesize; " \
905 "cmp.b $loadaddr 0xEC000000 $filesize; " \
906 "protect on 0xeC000000 +$filesize\0" \
907 "tftpflash=tftpboot $loadaddr $uboot; " \
908 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
909 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
910 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
911 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
912 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
913 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
914 "ubootfile=u-boot.bin\0" \
915 "upgrade=run flashuboot\0" \
916 "usb_phy_type=ulpi\0 " \
917 "boot_nfs= " \
918 "setenv bootargs root=/dev/nfs rw " \
919 "nfsroot=$serverip:$rootpath " \
920 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
921 "console=$consoledev,$baudrate $othbootargs;" \
922 "tftp $loadaddr $bootfile;" \
923 "tftp $fdtaddr $fdtfile;" \
924 "bootm $loadaddr - $fdtaddr\0" \
925 "boot_hd = " \
926 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
927 "console=$consoledev,$baudrate $othbootargs;" \
928 "usb start;" \
929 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
930 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
931 "bootm $loadaddr - $fdtaddr\0" \
932 "boot_usb_fat = " \
933 "setenv bootargs root=/dev/ram rw " \
934 "console=$consoledev,$baudrate $othbootargs " \
935 "ramdisk_size=$ramdisk_size;" \
936 "usb start;" \
937 "fatload usb 0:2 $loadaddr $bootfile;" \
938 "fatload usb 0:2 $fdtaddr $fdtfile;" \
939 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
940 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
941 "boot_usb_ext2 = " \
942 "setenv bootargs root=/dev/ram rw " \
943 "console=$consoledev,$baudrate $othbootargs " \
944 "ramdisk_size=$ramdisk_size;" \
945 "usb start;" \
946 "ext2load usb 0:4 $loadaddr $bootfile;" \
947 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
948 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
949 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
950 "boot_nor = " \
951 "setenv bootargs root=/dev/$jffs2nor rw " \
952 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
953 "bootm $norbootaddr - $norfdtaddr\0 " \
954 "boot_ram = " \
955 "setenv bootargs root=/dev/ram rw " \
956 "console=$consoledev,$baudrate $othbootargs " \
957 "ramdisk_size=$ramdisk_size;" \
958 "tftp $ramdiskaddr $ramdiskfile;" \
959 "tftp $loadaddr $bootfile;" \
960 "tftp $fdtaddr $fdtfile;" \
961 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
962
963 #endif
964 #endif
965
966 #endif /* __CONFIG_H */
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