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[people/ms/u-boot.git] / include / configs / UCP1020.h
1 /*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_SYS_GENERIC_BOARD
18 #define CONFIG_DISPLAY_BOARDINFO
19
20 #define CONFIG_FSL_ELBC
21 #define CONFIG_PCI
22 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
23 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
24 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
25 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
26 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
27 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
28
29 #if defined(CONFIG_TARTGET_UCP1020T1)
30
31 #define CONFIG_UCP1020_REV_1_3
32
33 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
34 #define CONFIG_P1020
35
36 #define CONFIG_TSEC_ENET
37 #define CONFIG_TSEC1
38 #define CONFIG_TSEC3
39 #define CONFIG_HAS_ETH0
40 #define CONFIG_HAS_ETH1
41 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
42 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
43 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
44 #define CONFIG_IPADDR 10.80.41.229
45 #define CONFIG_SERVERIP 10.80.41.227
46 #define CONFIG_NETMASK 255.255.252.0
47 #define CONFIG_ETHPRIME "eTSEC3"
48
49 #ifndef CONFIG_SPI_FLASH
50 #endif
51 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
52
53 #define CONFIG_MMC
54 #define CONFIG_SYS_L2_SIZE (256 << 10)
55
56 #define CONFIG_LAST_STAGE_INIT
57
58 #if !defined(CONFIG_DONGLE)
59 #define CONFIG_SILENT_CONSOLE
60 #endif
61
62 #endif
63
64 #if defined(CONFIG_TARGET_UCP1020)
65
66 #define CONFIG_UCP1020
67 #define CONFIG_UCP1020_REV_1_3
68
69 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
70 #define CONFIG_P1020
71
72 #define CONFIG_TSEC_ENET
73 #define CONFIG_TSEC1
74 #define CONFIG_TSEC2
75 #define CONFIG_TSEC3
76 #define CONFIG_HAS_ETH0
77 #define CONFIG_HAS_ETH1
78 #define CONFIG_HAS_ETH2
79 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
80 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
81 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
82 #define CONFIG_IPADDR 192.168.1.81
83 #define CONFIG_IPADDR1 192.168.1.82
84 #define CONFIG_IPADDR2 192.168.1.83
85 #define CONFIG_SERVERIP 192.168.1.80
86 #define CONFIG_GATEWAYIP 102.168.1.1
87 #define CONFIG_NETMASK 255.255.255.0
88 #define CONFIG_ETHPRIME "eTSEC1"
89
90 #ifndef CONFIG_SPI_FLASH
91 #endif
92 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
93
94 #define CONFIG_MMC
95 #define CONFIG_SYS_L2_SIZE (256 << 10)
96
97 #define CONFIG_LAST_STAGE_INIT
98
99 #endif
100
101 #ifdef CONFIG_SDCARD
102 #define CONFIG_RAMBOOT_SDCARD
103 #define CONFIG_SYS_RAMBOOT
104 #define CONFIG_SYS_EXTRA_ENV_RELOC
105 #define CONFIG_SYS_TEXT_BASE 0x11000000
106 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
107 #endif
108
109 #ifdef CONFIG_SPIFLASH
110 #define CONFIG_RAMBOOT_SPIFLASH
111 #define CONFIG_SYS_RAMBOOT
112 #define CONFIG_SYS_EXTRA_ENV_RELOC
113 #define CONFIG_SYS_TEXT_BASE 0x11000000
114 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
115 #endif
116
117 #ifndef CONFIG_SYS_TEXT_BASE
118 #define CONFIG_SYS_TEXT_BASE 0xeff80000
119 #endif
120 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
121
122 #ifndef CONFIG_RESET_VECTOR_ADDRESS
123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124 #endif
125
126 #ifndef CONFIG_SYS_MONITOR_BASE
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
128 #endif
129
130 /* High Level Configuration Options */
131 #define CONFIG_BOOKE
132 #define CONFIG_E500
133 /* #define CONFIG_MPC85xx */
134
135 #define CONFIG_MP
136
137 #define CONFIG_FSL_LAW
138
139 #define CONFIG_ENV_OVERWRITE
140
141 #define CONFIG_CMD_SATA
142 #define CONFIG_SATA_SIL
143 #define CONFIG_SYS_SATA_MAX_DEVICE 2
144 #define CONFIG_LIBATA
145 #define CONFIG_LBA48
146
147 #define CONFIG_SYS_CLK_FREQ 66666666
148 #define CONFIG_DDR_CLK_FREQ 66666666
149
150 #define CONFIG_HWCONFIG
151
152 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
153 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
154 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
155 /*
156 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
157 * there will be one entry in this array for each two (dummy) sensors in
158 * CONFIG_DTT_SENSORS.
159 *
160 * For uCP1020 module:
161 * - only one ADM1021/NCT72
162 * - i2c addr 0x41
163 * - conversion rate 0x02 = 0.25 conversions/second
164 * - ALERT output disabled
165 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
166 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
167 */
168 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
169 0x02, 0, 1, 0, 85, 1, 0, 85} }
170
171 #define CONFIG_CMD_DTT
172
173 /*
174 * These can be toggled for performance analysis, otherwise use default.
175 */
176 #define CONFIG_L2_CACHE
177 #define CONFIG_BTB
178
179 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
180
181 #define CONFIG_ENABLE_36BIT_PHYS
182
183 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
184 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
185 #define CONFIG_PANIC_HANG /* do not reset board on panic */
186
187 #define CONFIG_SYS_CCSRBAR 0xffe00000
188 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
189
190 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
191 SPL code*/
192 #ifdef CONFIG_SPL_BUILD
193 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
194 #endif
195
196 /* DDR Setup */
197 #define CONFIG_DDR_ECC_ENABLE
198 #define CONFIG_SYS_FSL_DDR3
199 #ifndef CONFIG_DDR_ECC_ENABLE
200 #define CONFIG_SYS_DDR_RAW_TIMING
201 #define CONFIG_DDR_SPD
202 #endif
203 #define CONFIG_SYS_SPD_BUS_NUM 1
204 #undef CONFIG_FSL_DDR_INTERACTIVE
205
206 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
207 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
208 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
210 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
211
212 #define CONFIG_NUM_DDR_CONTROLLERS 1
213 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
214
215 /* Default settings for DDR3 */
216 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
217 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
218 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
219 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
220 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
221 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
222
223 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
224 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
225 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
226 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
227
228 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
229 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
230 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
231 #define CONFIG_SYS_DDR_RCW_1 0x00000000
232 #define CONFIG_SYS_DDR_RCW_2 0x00000000
233 #ifdef CONFIG_DDR_ECC_ENABLE
234 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
235 #else
236 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
237 #endif
238 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
239 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
240 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
241
242 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
243 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
244 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
245 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
246 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
247 #define CONFIG_SYS_DDR_MODE_1 0x40461520
248 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
249 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
250
251 #undef CONFIG_CLOCKS_IN_MHZ
252
253 /*
254 * Memory map
255 *
256 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
257 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
258 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
259 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
260 * (early boot only)
261 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
262 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
263 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
264 */
265
266 /*
267 * Local Bus Definitions
268 */
269 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
270 #define CONFIG_SYS_FLASH_BASE 0xec000000
271
272 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
273
274 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
275 | BR_PS_16 | BR_V)
276
277 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
278
279 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
280 #define CONFIG_SYS_FLASH_QUIET_TEST
281 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
282
283 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
284
285 #undef CONFIG_SYS_FLASH_CHECKSUM
286 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
287 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
288
289 #define CONFIG_FLASH_CFI_DRIVER
290 #define CONFIG_SYS_FLASH_CFI
291 #define CONFIG_SYS_FLASH_EMPTY_INFO
292 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
293
294 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
295
296 #define CONFIG_SYS_INIT_RAM_LOCK
297 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
298 /* Initial L1 address */
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
302 /* Size of used area in RAM */
303 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
304
305 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
306 GENERATED_GBL_DATA_SIZE)
307 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
308
309 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
310 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
311
312 #define CONFIG_SYS_PMC_BASE 0xff980000
313 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
314 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
315 BR_PS_8 | BR_V)
316 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
317 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
318 OR_GPCM_EAD)
319
320 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
321 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
322 #ifdef CONFIG_NAND_FSL_ELBC
323 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
324 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
325 #endif
326
327 /* Serial Port - controlled on board with jumper J8
328 * open - index 2
329 * shorted - index 1
330 */
331 #define CONFIG_CONS_INDEX 1
332 #undef CONFIG_SERIAL_SOFTWARE_FIFO
333 #define CONFIG_SYS_NS16550
334 #define CONFIG_SYS_NS16550_SERIAL
335 #define CONFIG_SYS_NS16550_REG_SIZE 1
336 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
337 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
338 #define CONFIG_NS16550_MIN_FUNCTIONS
339 #endif
340
341 #define CONFIG_SYS_BAUDRATE_TABLE \
342 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
343
344 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
345 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
346
347 /* Use the HUSH parser */
348 #define CONFIG_SYS_HUSH_PARSER
349
350 /*
351 * Pass open firmware flat tree
352 */
353 #define CONFIG_OF_LIBFDT
354 #define CONFIG_OF_BOARD_SETUP
355 #define CONFIG_OF_STDOUT_VIA_ALIAS
356
357 /* new uImage format support */
358 #define CONFIG_FIT
359 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
360
361 /* I2C */
362 #define CONFIG_SYS_I2C
363 #define CONFIG_SYS_I2C_FSL
364 #define CONFIG_SYS_FSL_I2C_SPEED 400000
365 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
366 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
367 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
368 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
369 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
370 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
371 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
372
373 #define CONFIG_RTC_DS1337
374 #define CONFIG_SYS_RTC_DS1337_NOOSC
375 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
376 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
377 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
378 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
379
380 /*
381 * eSPI - Enhanced SPI
382 */
383 #define CONFIG_HARD_SPI
384 #define CONFIG_FSL_ESPI
385
386 #define CONFIG_SPI_FLASH_SST 1
387 #define CONFIG_SPI_FLASH_STMICRO 1
388 #define CONFIG_SPI_FLASH_WINBOND 1
389 #define CONFIG_CMD_SF 1
390 #define CONFIG_CMD_SPI 1
391 #define CONFIG_SF_DEFAULT_SPEED 10000000
392 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
393
394 #if defined(CONFIG_PCI)
395 /*
396 * General PCI
397 * Memory space is mapped 1-1, but I/O space must start from 0.
398 */
399
400 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
401 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
402 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
403 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
404 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
405 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
406 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
407 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
408 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
409 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
410
411 /* controller 1, Slot 2, tgtid 1, Base address a000 */
412 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
413 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
414 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
416 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
417 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
418 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
419 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
420 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
421
422 #define CONFIG_PCI_PNP /* do pci plug-and-play */
423 #define CONFIG_CMD_PCI
424
425 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
426 #define CONFIG_DOS_PARTITION
427 #endif /* CONFIG_PCI */
428
429 /*
430 * Environment
431 */
432 #ifdef CONFIG_ENV_FIT_UCBOOT
433
434 #define CONFIG_ENV_IS_IN_FLASH
435 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
436 #define CONFIG_ENV_SIZE 0x20000
437 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
438
439 #else
440
441 #define CONFIG_ENV_SPI_BUS 0
442 #define CONFIG_ENV_SPI_CS 0
443 #define CONFIG_ENV_SPI_MAX_HZ 10000000
444 #define CONFIG_ENV_SPI_MODE 0
445
446 #ifdef CONFIG_RAMBOOT_SPIFLASH
447
448 #define CONFIG_ENV_IS_IN_SPI_FLASH
449 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
450 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
451 #define CONFIG_ENV_SECT_SIZE 0x1000
452
453 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
454 /* Address and size of Redundant Environment Sector */
455 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
456 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
457 #endif
458
459 #elif defined(CONFIG_RAMBOOT_SDCARD)
460 #define CONFIG_ENV_IS_IN_MMC
461 #define CONFIG_FSL_FIXED_MMC_LOCATION
462 #define CONFIG_ENV_SIZE 0x2000
463 #define CONFIG_SYS_MMC_ENV_DEV 0
464
465 #elif defined(CONFIG_SYS_RAMBOOT)
466 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
467 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
468 #define CONFIG_ENV_SIZE 0x2000
469
470 #else
471 #define CONFIG_ENV_IS_IN_FLASH
472 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
473 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
474 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
475 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
476 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
477 /* Address and size of Redundant Environment Sector */
478 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
479 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
480 #endif
481
482 #endif
483
484 #endif /* CONFIG_ENV_FIT_UCBOOT */
485
486 #define CONFIG_LOADS_ECHO /* echo on for serial download */
487 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
488
489 /*
490 * Command line configuration.
491 */
492 #define CONFIG_CMD_IRQ
493 #define CONFIG_CMD_PING
494 #define CONFIG_CMD_I2C
495 #define CONFIG_CMD_MII
496 #define CONFIG_CMD_DATE
497 #define CONFIG_CMD_I2C
498 #define CONFIG_CMD_IRQ
499 #define CONFIG_CMD_MII
500 #define CONFIG_CMD_PING
501 #define CONFIG_CMD_REGINFO
502 #define CONFIG_CMD_ERRATA
503 #define CONFIG_CMD_CRAMFS
504 #define CONFIG_CRAMFS_CMDLINE
505
506 /*
507 * USB
508 */
509 #define CONFIG_HAS_FSL_DR_USB
510
511 #if defined(CONFIG_HAS_FSL_DR_USB)
512 #define CONFIG_USB_EHCI
513
514 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
515
516 #ifdef CONFIG_USB_EHCI
517 #define CONFIG_CMD_USB
518 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
519 #define CONFIG_USB_EHCI_FSL
520 #define CONFIG_USB_STORAGE
521 #endif
522 #endif
523
524 #undef CONFIG_WATCHDOG /* watchdog disabled */
525
526 #ifdef CONFIG_MMC
527 #define CONFIG_FSL_ESDHC
528 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
529 #define CONFIG_CMD_MMC
530 #define CONFIG_MMC_SPI
531 #define CONFIG_CMD_MMC_SPI
532 #define CONFIG_GENERIC_MMC
533 #endif
534
535 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
536 #define CONFIG_CMD_EXT2
537 #define CONFIG_CMD_FAT
538 #define CONFIG_DOS_PARTITION
539 #endif
540
541 /* Misc Extra Settings */
542 #define CONFIG_CMD_GPIO 1
543 #undef CONFIG_WATCHDOG /* watchdog disabled */
544
545 /*
546 * Miscellaneous configurable options
547 */
548 #define CONFIG_SYS_LONGHELP /* undef to save memory */
549 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
550 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
551 #if defined(CONFIG_CMD_KGDB)
552 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
553 #else
554 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
555 #endif
556 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
557 /* Print Buffer Size */
558 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
559 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
560 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
561
562 /*
563 * For booting Linux, the board info and command line data
564 * have to be in the first 64 MB of memory, since this is
565 * the maximum mapped by the Linux kernel during initialization.
566 */
567 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
568 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
569
570 #if defined(CONFIG_CMD_KGDB)
571 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
572 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
573 #endif
574
575 /*
576 * Environment Configuration
577 */
578
579 #if defined(CONFIG_TSEC_ENET)
580
581 #if defined(CONFIG_UCP1020_REV_1_2)
582 #define CONFIG_PHY_MICREL_KSZ9021
583 #elif defined(CONFIG_UCP1020_REV_1_3)
584 #define CONFIG_PHY_MICREL_KSZ9031
585 #else
586 #error "UCP1020 module revision is not defined !!!"
587 #endif
588
589 #define CONFIG_CMD_DHCP
590 #define CONFIG_BOOTP_SERVERIP
591
592 #define CONFIG_MII /* MII PHY management */
593 #define CONFIG_TSEC1_NAME "eTSEC1"
594 #define CONFIG_TSEC2_NAME "eTSEC2"
595 #define CONFIG_TSEC3_NAME "eTSEC3"
596
597 #define TSEC1_PHY_ADDR 4
598 #define TSEC2_PHY_ADDR 0
599 #define TSEC2_PHY_ADDR_SGMII 0x00
600 #define TSEC3_PHY_ADDR 6
601
602 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
603 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
604 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
605
606 #define TSEC1_PHYIDX 0
607 #define TSEC2_PHYIDX 0
608 #define TSEC3_PHYIDX 0
609
610 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
611
612 #endif
613
614 #define CONFIG_HOSTNAME UCP1020
615 #define CONFIG_ROOTPATH "/opt/nfsroot"
616 #define CONFIG_BOOTFILE "uImage"
617 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
618
619 /* default location for tftp and bootm */
620 #define CONFIG_LOADADDR 1000000
621
622 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
623
624 #define CONFIG_BAUDRATE 115200
625
626 #if defined(CONFIG_DONGLE)
627
628 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
629 #define CONFIG_EXTRA_ENV_SETTINGS \
630 "bootcmd=run prog_spi_mbrbootcramfs\0" \
631 "bootfile=uImage\0" \
632 "consoledev=ttyS0\0" \
633 "cramfsfile=image.cramfs\0" \
634 "dtbaddr=0x00c00000\0" \
635 "dtbfile=image.dtb\0" \
636 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
637 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
638 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
639 "fileaddr=0x01000000\0" \
640 "filesize=0x00080000\0" \
641 "flashmbr=sf probe 0; " \
642 "tftp $loadaddr $mbr; " \
643 "sf erase $mbr_offset +$filesize; " \
644 "sf write $loadaddr $mbr_offset $filesize\0" \
645 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
646 "protect off $nor_recoveryaddr +$filesize; " \
647 "erase $nor_recoveryaddr +$filesize; " \
648 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
649 "protect on $nor_recoveryaddr +$filesize\0 " \
650 "flashuboot=tftp $ubootaddr $ubootfile; " \
651 "protect off $nor_ubootaddr +$filesize; " \
652 "erase $nor_ubootaddr +$filesize; " \
653 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
654 "protect on $nor_ubootaddr +$filesize\0 " \
655 "flashworking=tftp $workingaddr $cramfsfile; " \
656 "protect off $nor_workingaddr +$filesize; " \
657 "erase $nor_workingaddr +$filesize; " \
658 "cp.b $workingaddr $nor_workingaddr $filesize; " \
659 "protect on $nor_workingaddr +$filesize\0 " \
660 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
661 "kerneladdr=0x01100000\0" \
662 "kernelfile=uImage\0" \
663 "loadaddr=0x01000000\0" \
664 "mbr=uCP1020d.mbr\0" \
665 "mbr_offset=0x00000000\0" \
666 "mmbr=uCP1020Quiet.mbr\0" \
667 "mmcpart=0:2\0" \
668 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
669 "mmc erase 1 1; " \
670 "mmc write $loadaddr 1 1\0" \
671 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
672 "mmc erase 0x40 0x400; " \
673 "mmc write $loadaddr 0x40 0x400\0" \
674 "netdev=eth0\0" \
675 "nor_recoveryaddr=0xEC0A0000\0" \
676 "nor_ubootaddr=0xEFF80000\0" \
677 "nor_workingaddr=0xECFA0000\0" \
678 "norbootrecovery=setenv bootargs $recoverybootargs" \
679 " console=$consoledev,$baudrate $othbootargs; " \
680 "run norloadrecovery; " \
681 "bootm $kerneladdr - $dtbaddr\0" \
682 "norbootworking=setenv bootargs $workingbootargs" \
683 " console=$consoledev,$baudrate $othbootargs; " \
684 "run norloadworking; " \
685 "bootm $kerneladdr - $dtbaddr\0" \
686 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
687 "setenv cramfsaddr $nor_recoveryaddr; " \
688 "cramfsload $dtbaddr $dtbfile; " \
689 "cramfsload $kerneladdr $kernelfile\0" \
690 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
691 "setenv cramfsaddr $nor_workingaddr; " \
692 "cramfsload $dtbaddr $dtbfile; " \
693 "cramfsload $kerneladdr $kernelfile\0" \
694 "prog_spi_mbr=run spi__mbr\0" \
695 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
696 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
697 "run spi__cramfs\0" \
698 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
699 " console=$consoledev,$baudrate $othbootargs; " \
700 "tftp $rootfsaddr $rootfsfile; " \
701 "tftp $loadaddr $kernelfile; " \
702 "tftp $dtbaddr $dtbfile; " \
703 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
704 "ramdisk_size=120000\0" \
705 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
706 "recoveryaddr=0x02F00000\0" \
707 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
708 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
709 "mw.l 0xffe0f008 0x00400000\0" \
710 "rootfsaddr=0x02F00000\0" \
711 "rootfsfile=rootfs.ext2.gz.uboot\0" \
712 "rootpath=/opt/nfsroot\0" \
713 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
714 "protect off 0xeC000000 +$filesize; " \
715 "erase 0xEC000000 +$filesize; " \
716 "cp.b $loadaddr 0xEC000000 $filesize; " \
717 "cmp.b $loadaddr 0xEC000000 $filesize; " \
718 "protect on 0xeC000000 +$filesize\0" \
719 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
720 "protect off 0xeFF80000 +$filesize; " \
721 "erase 0xEFF80000 +$filesize; " \
722 "cp.b $loadaddr 0xEFF80000 $filesize; " \
723 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
724 "protect on 0xeFF80000 +$filesize\0" \
725 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
726 "sf probe 0; sf erase 0x8000 +$filesize; " \
727 "sf write $loadaddr 0x8000 $filesize\0" \
728 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
729 "protect off 0xec0a0000 +$filesize; " \
730 "erase 0xeC0A0000 +$filesize; " \
731 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
732 "protect on 0xec0a0000 +$filesize\0" \
733 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
734 "sf probe 1; sf erase 0 +$filesize; " \
735 "sf write $loadaddr 0 $filesize\0" \
736 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
737 "sf probe 0; sf erase 0 +$filesize; " \
738 "sf write $loadaddr 0 $filesize\0" \
739 "tftpflash=tftpboot $loadaddr $uboot; " \
740 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
741 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
742 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
743 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
744 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
745 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
746 "ubootaddr=0x01000000\0" \
747 "ubootfile=u-boot.bin\0" \
748 "ubootd=u-boot4dongle.bin\0" \
749 "upgrade=run flashworking\0" \
750 "usb_phy_type=ulpi\0 " \
751 "workingaddr=0x02F00000\0" \
752 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
753
754 #else
755
756 #if defined(CONFIG_UCP1020T1)
757
758 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
759 #define CONFIG_EXTRA_ENV_SETTINGS \
760 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
761 "bootfile=uImage\0" \
762 "consoledev=ttyS0\0" \
763 "cramfsfile=image.cramfs\0" \
764 "dtbaddr=0x00c00000\0" \
765 "dtbfile=image.dtb\0" \
766 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
767 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
768 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
769 "fileaddr=0x01000000\0" \
770 "filesize=0x00080000\0" \
771 "flashmbr=sf probe 0; " \
772 "tftp $loadaddr $mbr; " \
773 "sf erase $mbr_offset +$filesize; " \
774 "sf write $loadaddr $mbr_offset $filesize\0" \
775 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
776 "protect off $nor_recoveryaddr +$filesize; " \
777 "erase $nor_recoveryaddr +$filesize; " \
778 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
779 "protect on $nor_recoveryaddr +$filesize\0 " \
780 "flashuboot=tftp $ubootaddr $ubootfile; " \
781 "protect off $nor_ubootaddr +$filesize; " \
782 "erase $nor_ubootaddr +$filesize; " \
783 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
784 "protect on $nor_ubootaddr +$filesize\0 " \
785 "flashworking=tftp $workingaddr $cramfsfile; " \
786 "protect off $nor_workingaddr +$filesize; " \
787 "erase $nor_workingaddr +$filesize; " \
788 "cp.b $workingaddr $nor_workingaddr $filesize; " \
789 "protect on $nor_workingaddr +$filesize\0 " \
790 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
791 "kerneladdr=0x01100000\0" \
792 "kernelfile=uImage\0" \
793 "loadaddr=0x01000000\0" \
794 "mbr=uCP1020.mbr\0" \
795 "mbr_offset=0x00000000\0" \
796 "netdev=eth0\0" \
797 "nor_recoveryaddr=0xEC0A0000\0" \
798 "nor_ubootaddr=0xEFF80000\0" \
799 "nor_workingaddr=0xECFA0000\0" \
800 "norbootrecovery=setenv bootargs $recoverybootargs" \
801 " console=$consoledev,$baudrate $othbootargs; " \
802 "run norloadrecovery; " \
803 "bootm $kerneladdr - $dtbaddr\0" \
804 "norbootworking=setenv bootargs $workingbootargs" \
805 " console=$consoledev,$baudrate $othbootargs; " \
806 "run norloadworking; " \
807 "bootm $kerneladdr - $dtbaddr\0" \
808 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
809 "setenv cramfsaddr $nor_recoveryaddr; " \
810 "cramfsload $dtbaddr $dtbfile; " \
811 "cramfsload $kerneladdr $kernelfile\0" \
812 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
813 "setenv cramfsaddr $nor_workingaddr; " \
814 "cramfsload $dtbaddr $dtbfile; " \
815 "cramfsload $kerneladdr $kernelfile\0" \
816 "othbootargs=quiet\0" \
817 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
818 " console=$consoledev,$baudrate $othbootargs; " \
819 "tftp $rootfsaddr $rootfsfile; " \
820 "tftp $loadaddr $kernelfile; " \
821 "tftp $dtbaddr $dtbfile; " \
822 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
823 "ramdisk_size=120000\0" \
824 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
825 "recoveryaddr=0x02F00000\0" \
826 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
827 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
828 "mw.l 0xffe0f008 0x00400000\0" \
829 "rootfsaddr=0x02F00000\0" \
830 "rootfsfile=rootfs.ext2.gz.uboot\0" \
831 "rootpath=/opt/nfsroot\0" \
832 "silent=1\0" \
833 "tftpflash=tftpboot $loadaddr $uboot; " \
834 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
835 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
836 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
837 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
838 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
839 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
840 "ubootaddr=0x01000000\0" \
841 "ubootfile=u-boot.bin\0" \
842 "upgrade=run flashworking\0" \
843 "workingaddr=0x02F00000\0" \
844 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
845
846 #else /* For Arcturus Modules */
847
848 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
849 #define CONFIG_EXTRA_ENV_SETTINGS \
850 "bootcmd=run norkernel\0" \
851 "bootfile=uImage\0" \
852 "consoledev=ttyS0\0" \
853 "dtbaddr=0x00c00000\0" \
854 "dtbfile=image.dtb\0" \
855 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
856 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
857 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
858 "fileaddr=0x01000000\0" \
859 "filesize=0x00080000\0" \
860 "flashmbr=sf probe 0; " \
861 "tftp $loadaddr $mbr; " \
862 "sf erase $mbr_offset +$filesize; " \
863 "sf write $loadaddr $mbr_offset $filesize\0" \
864 "flashuboot=tftp $loadaddr $ubootfile; " \
865 "protect off $nor_ubootaddr0 +$filesize; " \
866 "erase $nor_ubootaddr0 +$filesize; " \
867 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
868 "protect on $nor_ubootaddr0 +$filesize; " \
869 "protect off $nor_ubootaddr1 +$filesize; " \
870 "erase $nor_ubootaddr1 +$filesize; " \
871 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
872 "protect on $nor_ubootaddr1 +$filesize\0 " \
873 "format0=protect off $part0base +$part0size; " \
874 "erase $part0base +$part0size\0" \
875 "format1=protect off $part1base +$part1size; " \
876 "erase $part1base +$part1size\0" \
877 "format2=protect off $part2base +$part2size; " \
878 "erase $part2base +$part2size\0" \
879 "format3=protect off $part3base +$part3size; " \
880 "erase $part3base +$part3size\0" \
881 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
882 "kerneladdr=0x01100000\0" \
883 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
884 "kernelfile=uImage\0" \
885 "loadaddr=0x01000000\0" \
886 "mbr=uCP1020.mbr\0" \
887 "mbr_offset=0x00000000\0" \
888 "netdev=eth0\0" \
889 "nor_ubootaddr0=0xEC000000\0" \
890 "nor_ubootaddr1=0xEFF80000\0" \
891 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
892 "run norkernelload; " \
893 "bootm $kerneladdr - $dtbaddr\0" \
894 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
895 "setenv cramfsaddr $part0base; " \
896 "cramfsload $dtbaddr $dtbfile; " \
897 "cramfsload $kerneladdr $kernelfile\0" \
898 "part0base=0xEC100000\0" \
899 "part0size=0x00700000\0" \
900 "part1base=0xEC800000\0" \
901 "part1size=0x02000000\0" \
902 "part2base=0xEE800000\0" \
903 "part2size=0x00800000\0" \
904 "part3base=0xEF000000\0" \
905 "part3size=0x00F80000\0" \
906 "partENVbase=0xEC080000\0" \
907 "partENVsize=0x00080000\0" \
908 "program0=tftp part0-000000.bin; " \
909 "protect off $part0base +$filesize; " \
910 "erase $part0base +$filesize; " \
911 "cp.b $loadaddr $part0base $filesize; " \
912 "echo Verifying...; " \
913 "cmp.b $loadaddr $part0base $filesize\0" \
914 "program1=tftp part1-000000.bin; " \
915 "protect off $part1base +$filesize; " \
916 "erase $part1base +$filesize; " \
917 "cp.b $loadaddr $part1base $filesize; " \
918 "echo Verifying...; " \
919 "cmp.b $loadaddr $part1base $filesize\0" \
920 "program2=tftp part2-000000.bin; " \
921 "protect off $part2base +$filesize; " \
922 "erase $part2base +$filesize; " \
923 "cp.b $loadaddr $part2base $filesize; " \
924 "echo Verifying...; " \
925 "cmp.b $loadaddr $part2base $filesize\0" \
926 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
927 " console=$consoledev,$baudrate $othbootargs; " \
928 "tftp $rootfsaddr $rootfsfile; " \
929 "tftp $loadaddr $kernelfile; " \
930 "tftp $dtbaddr $dtbfile; " \
931 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
932 "ramdisk_size=120000\0" \
933 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
934 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
935 "mw.l 0xffe0f008 0x00400000\0" \
936 "rootfsaddr=0x02F00000\0" \
937 "rootfsfile=rootfs.ext2.gz.uboot\0" \
938 "rootpath=/opt/nfsroot\0" \
939 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
940 "sf probe 0; sf erase 0 +$filesize; " \
941 "sf write $loadaddr 0 $filesize\0" \
942 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
943 "protect off 0xeC000000 +$filesize; " \
944 "erase 0xEC000000 +$filesize; " \
945 "cp.b $loadaddr 0xEC000000 $filesize; " \
946 "cmp.b $loadaddr 0xEC000000 $filesize; " \
947 "protect on 0xeC000000 +$filesize\0" \
948 "tftpflash=tftpboot $loadaddr $uboot; " \
949 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
950 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
951 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
952 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
953 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
954 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
955 "ubootfile=u-boot.bin\0" \
956 "upgrade=run flashuboot\0" \
957 "usb_phy_type=ulpi\0 " \
958 "boot_nfs= " \
959 "setenv bootargs root=/dev/nfs rw " \
960 "nfsroot=$serverip:$rootpath " \
961 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
962 "console=$consoledev,$baudrate $othbootargs;" \
963 "tftp $loadaddr $bootfile;" \
964 "tftp $fdtaddr $fdtfile;" \
965 "bootm $loadaddr - $fdtaddr\0" \
966 "boot_hd = " \
967 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
968 "console=$consoledev,$baudrate $othbootargs;" \
969 "usb start;" \
970 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
971 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
972 "bootm $loadaddr - $fdtaddr\0" \
973 "boot_usb_fat = " \
974 "setenv bootargs root=/dev/ram rw " \
975 "console=$consoledev,$baudrate $othbootargs " \
976 "ramdisk_size=$ramdisk_size;" \
977 "usb start;" \
978 "fatload usb 0:2 $loadaddr $bootfile;" \
979 "fatload usb 0:2 $fdtaddr $fdtfile;" \
980 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
981 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
982 "boot_usb_ext2 = " \
983 "setenv bootargs root=/dev/ram rw " \
984 "console=$consoledev,$baudrate $othbootargs " \
985 "ramdisk_size=$ramdisk_size;" \
986 "usb start;" \
987 "ext2load usb 0:4 $loadaddr $bootfile;" \
988 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
989 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
990 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
991 "boot_nor = " \
992 "setenv bootargs root=/dev/$jffs2nor rw " \
993 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
994 "bootm $norbootaddr - $norfdtaddr\0 " \
995 "boot_ram = " \
996 "setenv bootargs root=/dev/ram rw " \
997 "console=$consoledev,$baudrate $othbootargs " \
998 "ramdisk_size=$ramdisk_size;" \
999 "tftp $ramdiskaddr $ramdiskfile;" \
1000 "tftp $loadaddr $bootfile;" \
1001 "tftp $fdtaddr $fdtfile;" \
1002 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
1003
1004 #endif
1005 #endif
1006
1007 #endif /* __CONFIG_H */
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