include/configs/VOM405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  19 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  20 #define CONFIG_VOM405           1       /* ...on a VOM405 board         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFFC8000
  23
  24 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  25 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  26
  27 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  28
  29 #define CONFIG_BAUDRATE         9600
  30 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  31
  32 #undef  CONFIG_BOOTARGS
  33 #undef  CONFIG_BOOTCOMMAND
  34
  35 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  36
  37 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  38
  39 #undef  CONFIG_HAS_ETH1
  40
  41 #define CONFIG_PPC4xx_EMAC
  42 #define CONFIG_MII              1       /* MII PHY management           */
  43 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  44 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  45 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  46
  47 /*
  48  * BOOTP options
  49  */
  50 #define CONFIG_BOOTP_SUBNETMASK
  51 #define CONFIG_BOOTP_GATEWAY
  52 #define CONFIG_BOOTP_HOSTNAME
  53 #define CONFIG_BOOTP_BOOTPATH
  54 #define CONFIG_BOOTP_DNS
  55 #define CONFIG_BOOTP_DNS2
  56 #define CONFIG_BOOTP_SEND_HOSTNAME
  57
  58 /*
  59  * Command line configuration.
  60  */
  61 #include <config_cmd_default.h>
  62
  63 #define CONFIG_CMD_DHCP
  64 #define CONFIG_CMD_BSP
  65 #define CONFIG_CMD_IRQ
  66 #define CONFIG_CMD_ELF
  67 #define CONFIG_CMD_I2C
  68 #define CONFIG_CMD_MII
  69 #define CONFIG_CMD_PING
  70 #define CONFIG_CMD_EEPROM
  71
  72 #define CONFIG_OF_LIBFDT
  73 #define CONFIG_OF_BOARD_SETUP
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  78
  79 #undef  CONFIG_PRAM                     /* no "protected RAM"           */
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  85
  86 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  87
  88 #if defined(CONFIG_CMD_KGDB)
  89 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  90 #else
  91 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  92 #endif
  93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  94 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  95 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  96
  97 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  98
  99 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 100
 101 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 102 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 103
 104 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 105 #define CONFIG_SYS_NS16550
 106 #define CONFIG_SYS_NS16550_SERIAL
 107 #define CONFIG_SYS_NS16550_REG_SIZE     1
 108 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 109
 110 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 111 #define CONFIG_SYS_BASE_BAUD        691200
 112
 113 /* The following table includes the supported baudrates */
 114 #define CONFIG_SYS_BAUDRATE_TABLE       \
 115         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 116          57600, 115200, 230400, 460800, 921600 }
 117
 118 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 119 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 120
 121 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 122 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 123
 124 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 125
 126 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 127
 128 /*
 129  * For booting Linux, the board info and command line data
 130  * have to be in the first 8 MB of memory, since this is
 131  * the maximum mapped by the Linux kernel during initialization.
 132  */
 133 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 134 /*
 135  * FLASH organization
 136  */
 137 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 138
 139 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 140 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 141
 142 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 143 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 144
 145 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 146 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 147 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 148 /*
 149  * The following defines are added for buggy IOP480 byte interface.
 150  * All other boards should use the standard values (CPCI405 etc.)
 151  */
 152 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 153 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 154 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 155
 156 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 157
 158 /*
 159  * Start addresses for the final memory configuration
 160  * (Set up by the startup code)
 161  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 162  */
 163 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 164 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 165 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 166 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 167 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 168
 169 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 170 # define CONFIG_SYS_RAMBOOT             1
 171 #else
 172 # undef CONFIG_SYS_RAMBOOT
 173 #endif
 174
 175 /*
 176  * Environment Variable setup
 177  */
 178 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 179 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 180 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 181                                    /* total size of a CAT24WC16 is 2048 bytes */
 182
 183 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 184 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 185
 186 /*
 187  * I2C EEPROM (CAT24WC16) for environment
 188  */
 189 #define CONFIG_SYS_I2C
 190 #define CONFIG_SYS_I2C_PPC4XX
 191 #define CONFIG_SYS_I2C_PPC4XX_CH0
 192 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 193 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 194
 195 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 197 /* mask of address bits that overflow into the "EEPROM chip address"    */
 198 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 199 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 200                                         /* 16 byte page write mode using*/
 201                                         /* last 4 bits of the address   */
 202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 203
 204 /*
 205  * External Bus Controller (EBC) Setup
 206  */
 207 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 208
 209 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 210 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 211 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 212
 213 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 214 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 215 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 216
 217 /*
 218  * FPGA stuff
 219  */
 220 #define CONFIG_SYS_XSVF_DEFAULT_ADDR    0xfffc0000
 221
 222 /* FPGA program pin configuration */
 223 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 224 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 225 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 226 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 227 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 228
 229 /*
 230  * Definitions for initial stack pointer and data area (in data cache)
 231  */
 232 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 233 #define CONFIG_SYS_TEMP_STACK_OCM         1
 234
 235 /* On Chip Memory location */
 236 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 237 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 238 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 239 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 240
 241 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 242 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 243
 244 /*
 245  * Definitions for GPIO setup (PPC405EP specific)
 246  *
 247  * GPIO0[0]     - External Bus Controller BLAST output
 248  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 249  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 250  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 251  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 252  * GPIO0[24-27] - UART0 control signal inputs/outputs
 253  * GPIO0[28-29] - UART1 data signal input/output
 254  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 255  */
 256 /* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 257 /* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 258 /* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 259 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 260 #define CONFIG_SYS_GPIO0_OSRL           0x40000500  /*  0 ... 15 */
 261 #define CONFIG_SYS_GPIO0_OSRH           0x00000110  /* 16 ... 31 */
 262 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000  /*  0 ... 15 */
 263 #define CONFIG_SYS_GPIO0_ISR1H          0x14000045  /* 16 ... 31 */
 264 #define CONFIG_SYS_GPIO0_TSRL           0x00000000  /*  0 ... 15 */
 265 #define CONFIG_SYS_GPIO0_TSRH           0x00000000  /* 16 ... 31 */
 266 #define CONFIG_SYS_GPIO0_TCR            0xF7FE0014  /*  0 ... 31 */
 267
 268 /*
 269  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 270  * This value will be set if iic boot eprom is disabled.
 271  */
 272 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 273 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 274
 275 #endif  /* __CONFIG_H */