include/configs/W7OLMG.h

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1               /* This is a PPC405GP CPU       */
  37 #define CONFIG_4xx              1               /* ...member of PPC405 family   */
  38 #define CONFIG_W7O              1               /* ...on a Wave 7 Optics board  */
  39 #define CONFIG_W7OLMG           1               /* ...specifically an LMG       */
  40
  41 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  42
  43 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f      */
  44 #define CONFIG_MISC_INIT_F      1               /* and misc_init_f()            */
  45 #define CONFIG_MISC_INIT_R      1               /* and misc_init_r()            */
  46
  47 #define CONFIG_SYS_CLK_FREQ     33333333        /* external frequency to pll    */
  48
  49 #define CONFIG_BAUDRATE         9600
  50 #define CONFIG_BOOTDELAY        3               /* autoboot after 3 seconds     */
  51
  52 #if 1
  53 #define CONFIG_BOOTCOMMAND      "bootvx"        /* VxWorks boot command         */
  54 #else
  55 #define CONFIG_BOOTCOMMAND      "bootp"         /* autoboot command             */
  56 #endif
  57
  58 #undef CONFIG_BOOTARGS
  59
  60 #define CONFIG_LOADADDR         F0080000
  61
  62 #define CONFIG_ETHADDR          00:06:0D:00:00:00 /* Default, overridden at boot        */
  63 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  64 #define CONFIG_IPADDR           192.168.1.1
  65 #define CONFIG_NETMASK          255.255.255.0
  66 #define CONFIG_SERVERIP         192.168.1.2
  67
  68 #define CONFIG_LOADS_ECHO       1               /* echo on for serial download  */
  69 #undef CONFIG_SYS_LOADS_BAUD_CHANGE                     /* disallow baudrate change     */
  70
  71 #define CONFIG_PPC4xx_EMAC
  72 #define CONFIG_MII              1               /* MII PHY management           */
  73 #define CONFIG_PHY_ADDR         0               /* PHY address                  */
  74
  75 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  76 #define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
  77 #define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
  78 #define CONFIG_SYS_DTT_MAX_TEMP 70
  79 #define CONFIG_SYS_DTT_LOW_TEMP -30
  80 #define CONFIG_SYS_DTT_HYSTERESIS       3
  81
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_BOOTFILESIZE
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90
  91
  92 /*
  93  * Command line configuration.
  94  */
  95 #include <config_cmd_default.h>
  96
  97 #define CONFIG_CMD_PCI
  98 #define CONFIG_CMD_IRQ
  99 #define CONFIG_CMD_ASKENV
 100 #define CONFIG_CMD_DHCP
 101 #define CONFIG_CMD_BEDBUG
 102 #define CONFIG_CMD_DATE
 103 #define CONFIG_CMD_I2C
 104 #define CONFIG_CMD_EEPROM
 105 #define CONFIG_CMD_ELF
 106 #define CONFIG_CMD_BSP
 107 #define CONFIG_CMD_REGINFO
 108 #define CONFIG_CMD_DTT
 109
 110
 111 #undef CONFIG_WATCHDOG                          /* watchdog disabled            */
 112 #define CONFIG_HW_WATCHDOG                      /* HW Watchdog, board specific  */
 113
 114 #define CONFIG_SPD_EEPROM                       /* SPD EEPROM for SDRAM param.  */
 115 #define CONFIG_SPDDRAM_SILENT                   /* No output if spd fails       */
 116 /*
 117  * Miscellaneous configurable options
 118  */
 119 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 120 #define CONFIG_SYS_PROMPT               "Wave7Optics> " /* Monitor Command Prompt       */
 121 #undef  CONFIG_SYS_HUSH_PARSER                          /* No hush parse for U-Boot       */
 122 #ifdef  CONFIG_SYS_HUSH_PARSER
 123 #endif
 124 #if defined(CONFIG_CMD_KGDB)
 125 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 126 #else
 127 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 128 #endif
 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 130 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 131 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 132
 133 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on             */
 134 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM          */
 135
 136 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 137 #define CONFIG_SYS_NS16550
 138 #define CONFIG_SYS_NS16550_SERIAL
 139 #define CONFIG_SYS_NS16550_REG_SIZE     1
 140 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 141
 142 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 143 #define CONFIG_SYS_405_UART_ERRATA_59                   /* 405GP/CR Rev. D silicon */
 144 #define CONFIG_SYS_BASE_BAUD            384000
 145
 146
 147 /* The following table includes the supported baudrates */
 148 #define CONFIG_SYS_BAUDRATE_TABLE       {9600}
 149
 150 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
 151 #define CONFIG_SYS_EXTBDINFO            1               /* use extended board_info (bd_t) */
 152
 153 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 154
 155 /*-----------------------------------------------------------------------
 156  * PCI stuff
 157  *-----------------------------------------------------------------------
 158  */
 159 #define PCI_HOST_ADAPTER        0               /* configure as pci adapter     */
 160 #define PCI_HOST_FORCE          1               /* configure as pci host        */
 161 #define PCI_HOST_AUTO           2               /* detected via arbiter enable  */
 162
 163 #define CONFIG_PCI                              /* include pci support          */
 164 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 165 #define CONFIG_PCI_HOST         PCI_HOST_AUTO   /* select pci host function     */
 166 #define CONFIG_PCI_PNP                          /* pci plug-and-play            */
 167 /* resource configuration       */
 168 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014           /* PCI Vendor ID: IBM           */
 169 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156           /* PCI Device ID: 405GP         */
 170 #define CONFIG_SYS_PCI_PTM1LA           0x00000000      /* point to sdram               */
 171 #define CONFIG_SYS_PCI_PTM1MS           0x80000001      /* 2GB, enable hard-wired to 1  */
 172 #define CONFIG_SYS_PCI_PTM1PCI          0x00000000      /* Host: use this pci address   */
 173 #define CONFIG_SYS_PCI_PTM2LA           0x00000000      /* disabled                     */
 174 #define CONFIG_SYS_PCI_PTM2MS           0x00000000      /* disabled                     */
 175 #define CONFIG_SYS_PCI_PTM2PCI          0x00000000      /* Host: use this pci address   */
 176
 177 /*-----------------------------------------------------------------------
 178  * Set up values for external bus controller
 179  * used by cpu_init.c
 180  *-----------------------------------------------------------------------
 181  */
 182  /* use PerWE instead of PCI_INT ( these functions share a pin ) */
 183 #define CONFIG_USE_PERWE 1
 184
 185 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 186 #define CONFIG_SYS_TEMP_STACK_OCM        1
 187
 188 /* bank 0 is boot flash */
 189 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 190 #define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
 191 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
 192 #define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
 193
 194 /* bank 1 is main flash */
 195 /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
 196 #define CONFIG_SYS_EBC_PB1AP   0x04850240
 197 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
 198 #define CONFIG_SYS_EBC_PB1CR   0xF00FC000
 199
 200 /* bank 2 is RTC/NVRAM */
 201 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 202 #define CONFIG_SYS_EBC_PB2AP   0x03000440
 203 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
 204 #define CONFIG_SYS_EBC_PB2CR   0xFC018000
 205
 206 /* bank 3 is FPGA 0 */
 207 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
 208 #define CONFIG_SYS_EBC_PB3AP   0x02000400
 209 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
 210 #define CONFIG_SYS_EBC_PB3CR   0xFD01A000
 211
 212 /* bank 4 is SAM 8 bit range */
 213 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 214 #define CONFIG_SYS_EBC_PB4AP   0x02840380
 215 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
 216 #define CONFIG_SYS_EBC_PB4CR   0xFE878000
 217
 218 /* bank 5 is SAM 16 bit range */
 219 /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
 220 #define CONFIG_SYS_EBC_PB5AP   0x05040d80
 221 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
 222 #define CONFIG_SYS_EBC_PB5CR   0xFD87A000
 223
 224 /* bank 6 is unused */
 225 /* PB6AP = 0 */
 226 #define CONFIG_SYS_EBC_PB6AP   0x00000000
 227 /* PB6CR = 0 */
 228 #define CONFIG_SYS_EBC_PB6CR   0x00000000
 229
 230 /* bank 7 is LED register */
 231 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 232 #define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
 233 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
 234 #define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
 235
 236 /*-----------------------------------------------------------------------
 237  * Start addresses for the final memory configuration
 238  * (Set up by the startup code)
 239  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 240  */
 241 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 242 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 244 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 196 kB for Monitor   */
 245 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 246
 247 /*
 248  * For booting Linux, the board info and command line data
 249  * have to be in the first 8 MB of memory, since this is
 250  * the maximum mapped by the Linux kernel during initialization.
 251  */
 252 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 253 /*-----------------------------------------------------------------------
 254  * FLASH organization
 255  */
 256 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* max number of memory banks   */
 257 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max number of sec on 1 chip  */
 258
 259 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000          /* Timeout, Flash Erase, in ms  */
 260 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout, Flash Write, in ms  */
 261 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use real Flash protection    */
 262
 263 #if 1 /* Use NVRAM for environment variables */
 264 /*-----------------------------------------------------------------------
 265  * NVRAM organization
 266  */
 267 #define CONFIG_ENV_IS_IN_NVRAM  1               /* use NVRAM for env vars       */
 268 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xfc000000      /* NVRAM base address           */
 269 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)       /* NVRAM size                   */
 270 #define CONFIG_ENV_SIZE         0x1000          /* Size of Environment vars     */
 271 /*define CONFIG_ENV_ADDR                 \
 272         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
 273 #define CONFIG_ENV_ADDR         CONFIG_SYS_NVRAM_BASE_ADDR
 274
 275 #else /* Use Boot Flash for environment variables */
 276 /*-----------------------------------------------------------------------
 277  * Flash EEPROM for environment
 278  */
 279 #define CONFIG_ENV_IS_IN_FLASH 1
 280 #define CONFIG_ENV_OFFSET               0x00040000      /* Offset of Environment Sector */
 281 #define CONFIG_ENV_SIZE         0x10000         /* Total Size of env. sector    */
 282
 283 #define CONFIG_ENV_SECT_SIZE    0x10000         /* see README - env sec tot sze */
 284 #endif
 285
 286 /*-----------------------------------------------------------------------
 287  * I2C EEPROM (ATMEL 24C04N)
 288  */
 289 #define CONFIG_SYS_I2C
 290 #define CONFIG_SYS_I2C_PPC4XX
 291 #define CONFIG_SYS_I2C_PPC4XX_CH0
 292 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 293 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 294
 295 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM ATMEL 24C04N          */
 296 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 298 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 299 /*-----------------------------------------------------------------------
 300  * Definitions for Serial Presence Detect EEPROM address
 301  * (to get SDRAM settings)
 302  */
 303 #define SPD_EEPROM_ADDRESS      0x50    /* XXX conflicting address!!! XXX */
 304
 305 /*
 306  * Init Memory Controller:
 307  */
 308 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0                */
 309 #define FLASH_BASE1_PRELIM      0xF0000000      /* FLASH bank #1                */
 310
 311 /* On Chip Memory location */
 312 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 313 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 314
 315 /*-----------------------------------------------------------------------
 316  * Definitions for initial stack pointer and data area (in RAM)
 317  */
 318 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 319 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 320 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 321 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 322
 323 #if defined(CONFIG_CMD_KGDB)
 324 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 325 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use     */
 326 #endif
 327
 328 /*
 329  * FPGA(s) configuration
 330  */
 331 #define CONFIG_SYS_FPGA_IMAGE_LEN       0x80000         /* 512KB FPGA image             */
 332 #define CONFIG_NUM_FPGAS        1               /* Number of FPGAs on board     */
 333 #define CONFIG_MAX_FPGAS        6               /* Maximum number of FPGAs      */
 334 #define CONFIG_FPGAS_BASE       0xFD000000L     /* Base address of FPGAs        */
 335 #define CONFIG_FPGAS_BANK_SIZE  0x00100000L     /* FPGAs' mmap bank size        */
 336
 337 #endif  /* __CONFIG_H */