include/configs/ZUMA.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #include <asm/processor.h>
  32
  33 #define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
  34 #define CONFIG_ETHER_PORT_MII   /* use two MII ports */
  35 #define CONFIG_INTEL_LXT97X     /* Intel LXT97X phy */
  36
  37 #ifndef __ASSEMBLY__
  38 #include <galileo/core.h>
  39 #endif
  40
  41 #include "../board/evb64260/local.h"
  42
  43 #define CONFIG_EVB64260         1       /* this is an EVB64260 board    */
  44 #define CONFIG_ZUMA_V2          1       /* always define this for ZUMA v2 */
  45
  46 /* #define CONFIG_ZUMA_V2_OLD   1 */    /* backwards compat for old V2 board */
  47
  48 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38400     */
  49
  50 #define CONFIG_ECC                      /* enable ECC support */
  51
  52 #define CONFIG_750CX                    /* we have a 750CX/CXe (override local.h) */
  53
  54 /* which initialization functions to call for this board */
  55 #define CONFIG_MISC_INIT_R
  56 #define CONFIG_BOARD_PRE_INIT
  57 #define CFG_BOARD_ASM_INIT
  58
  59 #define CFG_BOARD_NAME          "Zuma APv2"
  60
  61 #define CFG_HUSH_PARSER
  62 #define CFG_PROMPT_HUSH_PS2     "> "
  63
  64 /*
  65  * The following defines let you select what serial you want to use
  66  * for your console driver.
  67  *
  68  * what to do:
  69  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
  70  * cable onto the second DUART channel, change the CFG_DUART port from 1
  71  * to 0 below.
  72  *
  73  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  74  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  75  */
  76 #define CONFIG_MPSC
  77
  78 #define CONFIG_MPSC_PORT        0
  79
  80 #define CONFIG_NET_MULTI        /* attempt all available adapters */
  81
  82 /* define this if you want to enable GT MAC filtering */
  83 #define CONFIG_GT_USE_MAC_HASH_TABLE
  84
  85 #if 1
  86 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  87 #else
  88 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  89 #endif
  90 #define CONFIG_ZERO_BOOTDELAY_CHECK
  91
  92 #undef  CONFIG_BOOTARGS
  93
  94 #define CONFIG_BOOTCOMMAND                                                      \
  95         "tftpboot && "                                                          \
  96         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
  97         "ip=$ipaddr:$serverip:$gatewayip:"                              \
  98         "$netmask:$hostname:eth0:none panic=5 && bootm"
  99
 100 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 101 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes       */
 102
 103 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 104 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 105
 106 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
 107                                  CONFIG_BOOTP_BOOTFILESIZE)
 108
 109 #define CONFIG_MII              /* enable MII commands */
 110
 111 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
 112                                  CFG_CMD_ASKENV | \
 113                                  CFG_CMD_BSP    | \
 114                                  CFG_CMD_JFFS2  | \
 115                                  CFG_CMD_MII    | \
 116                                  CFG_CMD_DATE)
 117
 118 /* Flash banks JFFS2 should use */
 119 #define CFG_JFFS2_FIRST_BANK    1
 120 #define CFG_JFFS2_NUM_BANKS     2
 121
 122 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 123 #include <cmd_confdefs.h>
 124
 125 /*
 126  * Miscellaneous configurable options
 127  */
 128 #define CFG_LONGHELP                    /* undef to save memory         */
 129 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 130 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 131 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 132 #else
 133 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 134 #endif
 135 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 136 #define CFG_MAXARGS     16              /* max number of command args   */
 137 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 138
 139 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 140 #define CFG_MEMTEST_END         0x00C00000      /* 4 ... 12 MB in DRAM  */
 141
 142 #define CFG_LOAD_ADDR           0x00300000      /* default load address */
 143
 144 #define CFG_HZ                  1000            /* decr freq: 1ms ticks */
 145
 146 #define CFG_BUS_HZ              133000000       /* 133 MHz              */
 147
 148 #define CFG_BUS_CLK             CFG_BUS_HZ
 149
 150 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 151
 152 /*
 153  * Low Level Configuration Settings
 154  * (address mappings, register initial values, etc.)
 155  * You should know what you are doing if you make changes here.
 156  */
 157
 158 /*-----------------------------------------------------------------------
 159  * Definitions for initial stack pointer and data area
 160  */
 161 #define CFG_INIT_RAM_ADDR       0x40000000
 162 #define CFG_INIT_RAM_END        0x1000
 163 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for init data */
 164 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 165 #define CFG_INIT_RAM_LOCK
 166
 167
 168 /*-----------------------------------------------------------------------
 169  * Start addresses for the final memory configuration
 170  * (Set up by the startup code)
 171  * Please note that CFG_SDRAM_BASE _must_ start at 0
 172  */
 173 #define CFG_SDRAM_BASE          0x00000000
 174 #define CFG_FLASH_BASE          0xfff00000
 175 #define CFG_RESET_ADDRESS       0xfff00100
 176 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 177 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 178 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc */
 179
 180 /* areas to map different things with the GT in physical space */
 181 #define CFG_DRAM_BANKS          4
 182 #define CFG_DFL_GT_REGS         0x14000000      /* boot time GT_REGS */
 183
 184 /* What to put in the bats. */
 185 #define CFG_MISC_REGION_BASE    0xf0000000
 186
 187 /* Peripheral Device section */
 188 #define CFG_GT_REGS             0xf8000000      /* later mapped GT_REGS */
 189 #define CFG_DEV_BASE            0xf0000000
 190 #define CFG_DEV0_SIZE           _64M /* zuma flash @ 0xf000.0000*/
 191 #define CFG_DEV1_SIZE            _8M /* zuma IDE   @ 0xf400.0000 */
 192 #define CFG_DEV2_SIZE            _8M /* unused */
 193 #define CFG_DEV3_SIZE            _8M /* unused */
 194
 195 #define CFG_DEV0_PAR            0xc498243c
 196         /*     c    4     9     8     2     4     3     c */
 197         /* 33 22|2222|22 22|111 1|11 11|1 1  |     |      */
 198         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
 199         /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
 200         /*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
 201
 202 #define CFG_DEV1_PAR            0xc01b6ac5
 203         /*     c    0     1     b     6     a     c     5 */
 204         /* 33 22|2222|22 22|111 1|11 11|1 1  |     |      */
 205         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
 206         /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
 207         /*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
 208
 209
 210 #define CFG_8BIT_BOOT_PAR       0xc00b5e7c
 211
 212 #define CFG_MPP_CONTROL_0       0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
 213 #define CFG_MPP_CONTROL_1       0x00000000 /* GPP[15:12] : GPP[11:8] */
 214 #define CFG_MPP_CONTROL_2       0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
 215 #define CFG_MPP_CONTROL_3       0x00000000 /* GPP[31:28] (int[3:0]) */
 216                                            /* GPP[27:24] (27 is int4, rest are GPP) */
 217
 218 #define CFG_SERIAL_PORT_MUX     0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
 219 #define CFG_GPP_LEVEL_CONTROL   0xf8000000 /* interrupt inputs: GPP[31:27] */
 220
 221 #define CFG_SDRAM_CONFIG        0xe4e18200      /* 0x448 */
 222                                 /* idmas use buffer 1,1
 223                                    comm use buffer 1
 224                                    pci use buffer 0,0 (pci1->0 pci0->0)
 225                                    cpu use buffer 1 (R*18)
 226                                    normal load (see also ifdef HVL)
 227                                    standard SDRAM (see also ifdef REG)
 228                                    non staggered refresh */
 229                                 /* 31:26  25 23  20 19 18 16 */
 230                                 /* 111001 00 111 0  0  00 1 */
 231
 232                                 /* refresh count=0x200
 233                                    phy interleave disable (by default,
 234                                    set later by dram config..)
 235                                    virt interleave enable */
 236                                 /* 15 14 13:0 */
 237                                 /* 1  0  0x200 */
 238
 239 #define CFG_DEV0_SPACE          CFG_DEV_BASE
 240 #define CFG_DEV1_SPACE          (CFG_DEV0_SPACE + CFG_DEV0_SIZE)
 241 #define CFG_DEV2_SPACE          (CFG_DEV1_SPACE + CFG_DEV1_SIZE)
 242 #define CFG_DEV3_SPACE          (CFG_DEV2_SPACE + CFG_DEV2_SIZE)
 243
 244 /*-----------------------------------------------------------------------
 245  * PCI stuff
 246  */
 247
 248 #define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 249 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 250 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 251
 252 #define CONFIG_PCI                      /* include pci support          */
 253 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 254 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 255
 256 /* PCI MEMORY MAP section */
 257 #define CFG_PCI0_MEM_BASE       0x80000000
 258 #define CFG_PCI0_MEM_SIZE       _128M
 259 #define CFG_PCI1_MEM_BASE       0x88000000
 260 #define CFG_PCI1_MEM_SIZE       _128M
 261
 262 #define CFG_PCI0_0_MEM_SPACE    (CFG_PCI0_MEM_BASE)
 263 #define CFG_PCI1_0_MEM_SPACE    (CFG_PCI1_MEM_BASE)
 264
 265 /* PCI I/O MAP section */
 266 #define CFG_PCI0_IO_BASE        0xfa000000
 267 #define CFG_PCI0_IO_SIZE        _16M
 268 #define CFG_PCI1_IO_BASE        0xfb000000
 269 #define CFG_PCI1_IO_SIZE        _16M
 270
 271 #define CFG_PCI0_IO_SPACE       (CFG_PCI0_IO_BASE)
 272 #define CFG_PCI0_IO_SPACE_PCI   0x00000000
 273 #define CFG_PCI1_IO_SPACE       (CFG_PCI1_IO_BASE)
 274 #define CFG_PCI1_IO_SPACE_PCI   0x00000000
 275
 276
 277 /*----------------------------------------------------------------------
 278  * Initial BAT mappings
 279  */
 280
 281 /* NOTES:
 282  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 283  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 284  */
 285
 286 /* SDRAM */
 287 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 288 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 289 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 290 #define CFG_DBAT0U CFG_IBAT0U
 291
 292 /* init ram */
 293 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 294 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 295 #define CFG_DBAT1L  CFG_IBAT1L
 296 #define CFG_DBAT1U  CFG_IBAT1U
 297
 298 /* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
 299 #define CFG_IBAT2L BATL_NO_ACCESS
 300 #define CFG_IBAT2U CFG_DBAT2U
 301 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 302 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 303
 304 /* GT regs, bootrom, all the devices, PCI I/O */
 305 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 306 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 307 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 308 #define CFG_DBAT3U CFG_IBAT3U
 309
 310 /*
 311  * For booting Linux, the board info and command line data
 312  * have to be in the first 8 MB of memory, since this is
 313  * the maximum mapped by the Linux kernel during initialization.
 314  */
 315 #define CFG_BOOTMAPSZ           (8<<20) /* Initial Memory map for Linux */
 316
 317
 318 /*-----------------------------------------------------------------------
 319  * FLASH organization
 320  */
 321 #define CFG_MAX_FLASH_BANKS     3       /* max number of memory banks   */
 322 #define CFG_MAX_FLASH_SECT      130     /* max number of sectors on one chip */
 323
 324 #define CFG_EXTRA_FLASH_DEVICE  DEVICE0 /* extra flash at device 0 */
 325 #define CFG_EXTRA_FLASH_WIDTH   2       /* 16 bit */
 326
 327 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 328 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 329 #define CFG_FLASH_CFI           1
 330
 331 #define CFG_ENV_IS_IN_FLASH     1
 332 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */
 333 #define CFG_ENV_SECT_SIZE       0x10000 /* see README - env sect real size */
 334 #define CFG_ENV_ADDR            (0xfff80000 - CFG_ENV_SECT_SIZE)
 335
 336 /*-----------------------------------------------------------------------
 337  * Cache Configuration
 338  */
 339 #define CFG_CACHELINE_SIZE      32      /* For all MPC74xx CPUs          */
 340 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 341 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 342 #endif
 343
 344 /*-----------------------------------------------------------------------
 345  * L2CR setup -- make sure this is right for your board!
 346  * look in include/74xx_7xx.h for the defines used here
 347  */
 348
 349 #define CFG_L2
 350
 351 #ifdef CONFIG_750CX
 352 #define L2_INIT         0
 353 #else
 354 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 355                         L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 356 #endif
 357
 358 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 359
 360 /*------------------------------------------------------------------------
 361  * Real time clock
 362  */
 363 #define CONFIG_RTC_DS1302
 364
 365
 366 /*------------------------------------------------------------------------
 367  * Galileo I2C driver
 368  */
 369 #define CONFIG_GT_I2C
 370
 371 /*
 372  * Internal Definitions
 373  *
 374  * Boot Flags
 375  */
 376 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 377 #define BOOTFLAG_WARM   0x02            /* Software reboot                  */
 378
 379 #endif  /* __CONFIG_H */