include/configs/a4m072.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is a MPC5200 CPU */
  20 #define CONFIG_A4M072           1       /* ... on A4M072 board */
  21 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  24
  25 #define CONFIG_MISC_INIT_R
  26
  27 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  28
  29 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  30
  31 /*
  32  * Serial console configuration
  33  */
  34 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  35 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  36 /* define to enable silent console */
  37 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  38
  39 /*
  40  * PCI Mapping:
  41  * 0x40000000 - 0x4fffffff - PCI Memory
  42  * 0x50000000 - 0x50ffffff - PCI IO Space
  43  */
  44
  45 #if defined(CONFIG_PCI)
  46 #define CONFIG_PCI_SCAN_SHOW    1
  47 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  48
  49 #define CONFIG_PCI_MEM_BUS      0x40000000
  50 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  51 #define CONFIG_PCI_MEM_SIZE     0x10000000
  52
  53 #define CONFIG_PCI_IO_BUS       0x50000000
  54 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  55 #define CONFIG_PCI_IO_SIZE      0x01000000
  56 #endif
  57
  58 #define CONFIG_SYS_XLB_PIPELINING       1
  59
  60 #undef CONFIG_EEPRO100
  61
  62 /* USB */
  63 #define CONFIG_USB_OHCI_NEW
  64 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  65 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  66 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
  67 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
  68 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
  69 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
  70
  71 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  72
  73 /*
  74  * BOOTP options
  75  */
  76 #define CONFIG_BOOTP_BOOTFILESIZE
  77 #define CONFIG_BOOTP_BOOTPATH
  78 #define CONFIG_BOOTP_GATEWAY
  79 #define CONFIG_BOOTP_HOSTNAME
  80
  81 /*
  82  * Command line configuration.
  83  */
  84 #define CONFIG_CMD_EEPROM
  85 #define CONFIG_CMD_IDE
  86 #define CONFIG_CMD_DISPLAY
  87
  88 #if defined(CONFIG_PCI)
  89 #define CONFIG_CMD_PCI
  90 #endif
  91
  92 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low with 32 MB Flash */
  93 #define CONFIG_SYS_LOWBOOT              1
  94 #define CONFIG_SYS_LOWBOOT32            1
  95 #endif
  96
  97 /*
  98  * Autobooting
  99  */
 100
 101 #define CONFIG_SYS_AUTOLOAD     "n"
 102
 103 #undef  CONFIG_BOOTARGS
 104 #define CONFIG_PREBOOT                          "run try_update"
 105
 106 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 107         "bk=run add_mtd ; run add_consolespec ; bootm 200000\0"         \
 108         "cf1=diskboot 200000 0:1\0"                                     \
 109         "bootcmd_cf1=run bcf1\0"                                        \
 110         "bcf=setenv bootargs root=/dev/hda3\0"                          \
 111         "bootcmd_nfs=run bnfs\0"                                        \
 112         "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
 113                 "panic=1\0"                                             \
 114         "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"                \
 115                         "run norargs addip; run bk\0"                   \
 116         "bnfs=nfs 200000 ${rootpath}/boot/uImage;"                      \
 117                         "run nfsargs addip ; run bk\0"                  \
 118         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 119                                 "nfsroot=${serverip}:${rootpath}\0"     \
 120         "try_update=usb start;sleep 2;usb start;sleep 1;"               \
 121                         "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"   \
 122                         "source 2F0000\0"                               \
 123         "env_addr=FE060000\0"                                           \
 124         "kernel_addr=FE100000\0"                                        \
 125         "rootfs_addr=FE200000\0"                                        \
 126         "add_mtd=setenv bootargs ${bootargs} mtdparts="                 \
 127                 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"      \
 128         "bcf1=run cf1; run bcf; run addip; run bk\0"                    \
 129         "add_consolespec=setenv bootargs ${bootargs} "                  \
 130                                 "console=/dev/null quiet\0"             \
 131         "addip=if test -n ${ethaddr};"                                  \
 132                 "then if test -n ${ipaddr};"                            \
 133                         "then setenv bootargs ${bootargs} "             \
 134                                 "ip=${ipaddr}:${serverip}:${gatewayip}:"\
 135                                 "${netmask}:${hostname}:${netdev}:off;" \
 136                         "fi;"                                           \
 137                 "else;"                                                 \
 138                         "setenv bootargs ${bootargs} no_ethaddr;"       \
 139                 "fi\0"                                                  \
 140         "hostname=CPUP0\0"                                              \
 141         "netdev=eth0\0"                                                 \
 142         "bootcmd=run bootcmd_nor\0"                                     \
 143         ""
 144 /*
 145  * IPB Bus clocking configuration.
 146  */
 147 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 148
 149 /*
 150  * I2C configuration
 151  */
 152 #define CONFIG_HARD_I2C                 1       /* I2C with hardware support */
 153 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 154
 155 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 156 #define CONFIG_SYS_I2C_SLAVE            0x7F
 157
 158 /*
 159  * EEPROM configuration
 160  */
 161 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52    /* 1010010x */
 162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 165 #define CONFIG_SYS_EEPROM_WREN                  1
 166 #define CONFIG_SYS_EEPROM_WP                    GPIO_PSC2_4
 167
 168 /*
 169  * Flash configuration
 170  */
 171 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 172 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 173 #if !defined(CONFIG_SYS_LOWBOOT)
 174 #error "CONFIG_SYS_LOWBOOT not defined?"
 175 #else   /* CONFIG_SYS_LOWBOOT */
 176 #if defined(CONFIG_SYS_LOWBOOT32)
 177 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 178 #endif
 179 #endif  /* CONFIG_SYS_LOWBOOT */
 180
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 182 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 183 #define CONFIG_FLASH_CFI_DRIVER
 184 #define CONFIG_SYS_FLASH_CFI
 185 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 186 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_CS0_START}
 187 #define CONFIG_SYS_FLASH_BANKS_SIZES    {CONFIG_SYS_CS0_SIZE}
 188
 189 /*
 190  * Environment settings
 191  */
 192 #define CONFIG_ENV_IS_IN_FLASH  1
 193 #define CONFIG_ENV_SIZE         0x10000
 194 #define CONFIG_ENV_SECT_SIZE    0x20000
 195 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 196 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 197
 198 #define CONFIG_ENV_OVERWRITE    1
 199
 200 /*
 201  * Memory map
 202  */
 203 #define CONFIG_SYS_MBAR         0xF0000000
 204 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 205 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 206
 207 /* Use SRAM until RAM will be available */
 208 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 209 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 210
 211 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 212 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 213
 214 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 215 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 216 #   define CONFIG_SYS_RAMBOOT           1
 217 #endif
 218
 219 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 220 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 221 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 222
 223 /*
 224  * Ethernet configuration
 225  */
 226 #define CONFIG_MPC5xxx_FEC      1
 227 #define CONFIG_MPC5xxx_FEC_MII100
 228 /*
 229  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 230  */
 231 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 232 #define CONFIG_PHY_ADDR         0x1f
 233 #define CONFIG_PHY_TYPE         0x79c874                /* AMD Phy Controller */
 234
 235 /*
 236  * GPIO configuration
 237  */
 238 #define CONFIG_SYS_GPS_PORT_CONFIG      0x18000004
 239
 240 /*
 241  * Miscellaneous configurable options
 242  */
 243 #define CONFIG_CMDLINE_EDITING  1
 244 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 245 #if defined(CONFIG_CMD_KGDB)
 246 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 247 #else
 248 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 249 #endif
 250 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 251 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 252 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 253
 254 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 255 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 256
 257 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 258
 259 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 260 #if defined(CONFIG_CMD_KGDB)
 261 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 262 #endif
 263
 264 /*
 265  * Various low-level settings
 266  */
 267 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 268 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 269 /* Flash at CSBoot, CS0 */
 270 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 271 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 272 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 273 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 274 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 275 /* External SRAM at CS1 */
 276 #define CONFIG_SYS_CS1_START            0x62000000
 277 #define CONFIG_SYS_CS1_SIZE             0x00400000
 278 #define CONFIG_SYS_CS1_CFG              0x00009930
 279 #define CONFIG_SYS_SRAM_BASE            CONFIG_SYS_CS1_START
 280 #define CONFIG_SYS_SRAM_SIZE            CONFIG_SYS_CS1_SIZE
 281 /* LED display at CS7 */
 282 #define CONFIG_SYS_CS7_START            0x6a000000
 283 #define CONFIG_SYS_CS7_SIZE             (64*1024)
 284 #define CONFIG_SYS_CS7_CFG              0x0000bf30
 285
 286 #define CONFIG_SYS_CS_BURST             0x00000000
 287 #define CONFIG_SYS_CS_DEADCYCLE         0x33333003
 288
 289 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 290
 291 /*-----------------------------------------------------------------------
 292  * USB stuff
 293  *-----------------------------------------------------------------------
 294  */
 295 #define CONFIG_USB_CLOCK        0x0001BBBB
 296 #define CONFIG_USB_CONFIG       0x00001000 /* 0x4000 for SE mode */
 297
 298 /*-----------------------------------------------------------------------
 299  * IDE/ATA stuff Supports IDE harddisk
 300  *-----------------------------------------------------------------------
 301  */
 302
 303 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 304
 305 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 306 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 307
 308 #define CONFIG_IDE_PREINIT
 309
 310 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 311 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
 312
 313 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 314
 315 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 316
 317 /* Offset for data I/O                  */
 318 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 319
 320 /* Offset for normal register accesses  */
 321 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 322
 323 /* Offset for alternate registers       */
 324 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 325
 326 /* Interval between registers                                                */
 327 #define CONFIG_SYS_ATA_STRIDE          4
 328
 329 #define CONFIG_ATAPI                   1
 330
 331 /*-----------------------------------------------------------------------
 332  * Open firmware flat tree support
 333  *-----------------------------------------------------------------------
 334  */
 335 #define OF_CPU                  "PowerPC,5200@0"
 336 #define OF_SOC                  "soc5200@f0000000"
 337 #define OF_TBCLK                (bd->bi_busfreq / 4)
 338 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 339
 340 /* Support for the 7-segment display */
 341 #define CONFIG_SYS_DISP_CHR_RAM      CONFIG_SYS_CS7_START
 342 #define CONFIG_SHOW_ACTIVITY            /* used for display realization */
 343
 344 #define CONFIG_SHOW_BOOT_PROGRESS
 345
 346 #endif /* __CONFIG_H */