include/configs/adp-ag101p.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ag101/ag101.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_ADP_AG101P
  18
  19 #define CONFIG_USE_INTERRUPT
  20
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22
  23 #define CONFIG_CMDLINE_EDITING
  24
  25 #define CONFIG_ARCH_MAP_SYSMEM
  26
  27 #define CONFIG_BOOTP_SEND_HOSTNAME
  28 #define CONFIG_BOOTP_SERVERIP
  29
  30 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  31 #define CONFIG_MEM_REMAP
  32 #endif
  33
  34 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  35 #define CONFIG_SYS_TEXT_BASE    0x00500000
  36 #ifdef CONFIG_OF_CONTROL
  37 #undef CONFIG_OF_SEPARATE
  38 #define CONFIG_OF_EMBED
  39 #endif
  40 #else
  41 #ifdef CONFIG_MEM_REMAP
  42 #define CONFIG_SYS_TEXT_BASE    0x80000000
  43 #else
  44 #define CONFIG_SYS_TEXT_BASE    0x00000000
  45 #endif
  46 #endif
  47
  48 /*
  49  * Timer
  50  */
  51 #define CONFIG_SYS_CLK_FREQ     39062500
  52 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  53
  54 /*
  55  * Use Externel CLOCK or PCLK
  56  */
  57 #undef CONFIG_FTRTC010_EXTCLK
  58
  59 #ifndef CONFIG_FTRTC010_EXTCLK
  60 #define CONFIG_FTRTC010_PCLK
  61 #endif
  62
  63 #ifdef CONFIG_FTRTC010_EXTCLK
  64 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  65 #else
  66 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  67 #endif
  68
  69 #define TIMER_LOAD_VAL  0xffffffff
  70
  71 /*
  72  * Real Time Clock
  73  */
  74 #define CONFIG_RTC_FTRTC010
  75
  76 /*
  77  * Real Time Clock Divider
  78  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  79  */
  80 #define OSC_5MHZ                        (5*1000000)
  81 #define OSC_CLK                         (4*OSC_5MHZ)
  82 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  83
  84 /*
  85  * Serial console configuration
  86  */
  87
  88 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  89 #define CONFIG_CONS_INDEX               1
  90 #define CONFIG_SYS_NS16550_SERIAL
  91 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  92 #ifndef CONFIG_DM_SERIAL
  93 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  94 #endif
  95 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  96
  97 /*
  98  * SD (MMC) controller
  99  */
 100 #define CONFIG_FTSDC010_NUMBER          1
 101 #define CONFIG_FTSDC010_SDIO
 102
 103 /*
 104  * Miscellaneous configurable options
 105  */
 106 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 107
 108 /*
 109  * Size of malloc() pool
 110  */
 111 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 112 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 113
 114 /*
 115  * AHB Controller configuration
 116  */
 117 #define CONFIG_FTAHBC020S
 118
 119 #ifdef CONFIG_FTAHBC020S
 120 #include <faraday/ftahbc020s.h>
 121
 122 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 123 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 124
 125 /*
 126  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 127  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 128  * in C language.
 129  */
 130 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 131         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 132                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 133 #endif
 134
 135 /*
 136  * Watchdog
 137  */
 138 #define CONFIG_FTWDT010_WATCHDOG
 139
 140 /*
 141  * PMU Power controller configuration
 142  */
 143 #define CONFIG_PMU
 144 #define CONFIG_FTPMU010_POWER
 145
 146 #ifdef CONFIG_FTPMU010_POWER
 147 #include <faraday/ftpmu010.h>
 148 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 149 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 150                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 151                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 152                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 153                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 154                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 155                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 156 #endif
 157
 158 /*
 159  * SDRAM controller configuration
 160  */
 161 #define CONFIG_FTSDMC021
 162
 163 #ifdef CONFIG_FTSDMC021
 164 #include <faraday/ftsdmc021.h>
 165
 166 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 167                                          FTSDMC021_TP1_TRP(1)   |       \
 168                                          FTSDMC021_TP1_TRCD(1)  |       \
 169                                          FTSDMC021_TP1_TRF(3)   |       \
 170                                          FTSDMC021_TP1_TWR(1)   |       \
 171                                          FTSDMC021_TP1_TCL(2))
 172
 173 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 174                                          FTSDMC021_TP2_INI_REFT(8) |    \
 175                                          FTSDMC021_TP2_REF_INTV(0x180))
 176
 177 /*
 178  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 179  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 180  * C language.
 181  */
 182 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 183                                          FTSDMC021_CR1_DSZ(3)    |      \
 184                                          FTSDMC021_CR1_MBW(2)    |      \
 185                                          FTSDMC021_CR1_BNKSIZE(6))
 186
 187 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 188                                          FTSDMC021_CR2_IREF      |      \
 189                                          FTSDMC021_CR2_ISMR)
 190
 191 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 192 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 193                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 194
 195 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 196         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 197 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 198                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 199 #endif
 200
 201 /*
 202  * Physical Memory Map
 203  */
 204 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 205 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 206 #else
 207 #ifdef CONFIG_MEM_REMAP
 208 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 209 #else
 210 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 211 #endif
 212 #endif
 213
 214 #define PHYS_SDRAM_1 \
 215         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 216
 217 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 218
 219 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 220 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 221 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 222 #else
 223 #ifdef CONFIG_MEM_REMAP
 224 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 225 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 226 #else
 227 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 228 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 229 #endif
 230 #endif
 231
 232 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 233
 234 #ifdef CONFIG_MEM_REMAP
 235 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 236                                         GENERATED_GBL_DATA_SIZE)
 237 #else
 238 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 239                                         GENERATED_GBL_DATA_SIZE)
 240 #endif /* CONFIG_MEM_REMAP */
 241
 242 /*
 243  * Load address and memory test area should agree with
 244  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 245  */
 246 #define CONFIG_SYS_LOAD_ADDR            0x300000
 247
 248 /* memtest works on 63 MB in DRAM */
 249 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 250 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 251
 252 /*
 253  * Static memory controller configuration
 254  */
 255 #define CONFIG_FTSMC020
 256
 257 #ifdef CONFIG_FTSMC020
 258 #include <faraday/ftsmc020.h>
 259
 260 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 261         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 262         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 263 }
 264
 265 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 266 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 267                                          FTSMC020_BANK_SIZE_32M |       \
 268                                          FTSMC020_BANK_MBW_32)
 269
 270 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 271                                          FTSMC020_TPR_AST(1)    |       \
 272                                          FTSMC020_TPR_CTW(1)    |       \
 273                                          FTSMC020_TPR_ATI(1)    |       \
 274                                          FTSMC020_TPR_AT2(1)    |       \
 275                                          FTSMC020_TPR_WTC(1)    |       \
 276                                          FTSMC020_TPR_AHT(1)    |       \
 277                                          FTSMC020_TPR_TRNA(1))
 278 #endif
 279
 280 /*
 281  * FLASH on ADP_AG101P is connected to BANK0
 282  * Just disalbe the other BANK to avoid detection error.
 283  */
 284 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 285                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 286                                  FTSMC020_BANK_SIZE_32M           |     \
 287                                  FTSMC020_BANK_MBW_32)
 288
 289 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 290                                  FTSMC020_TPR_CTW(3)   |        \
 291                                  FTSMC020_TPR_ATI(0xf) |        \
 292                                  FTSMC020_TPR_AT2(3)   |        \
 293                                  FTSMC020_TPR_WTC(3)   |        \
 294                                  FTSMC020_TPR_AHT(3)   |        \
 295                                  FTSMC020_TPR_TRNA(0xf))
 296
 297 #define FTSMC020_BANK1_CONFIG   (0x00)
 298 #define FTSMC020_BANK1_TIMING   (0x00)
 299 #endif /* CONFIG_FTSMC020 */
 300
 301 /*
 302  * FLASH and environment organization
 303  */
 304 /* use CFI framework */
 305 #define CONFIG_SYS_FLASH_CFI
 306 #define CONFIG_FLASH_CFI_DRIVER
 307
 308 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 309 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 310 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 311
 312 /* support JEDEC */
 313
 314 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 315 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 316 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 317 #else
 318 #ifdef CONFIG_MEM_REMAP
 319 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 320 #else
 321 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 322 #endif
 323 #endif  /* CONFIG_MEM_REMAP */
 324
 325 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 326 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 327 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 328
 329 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 330 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 331
 332 /* max number of memory banks */
 333 /*
 334  * There are 4 banks supported for this Controller,
 335  * but we have only 1 bank connected to flash on board
 336  */
 337 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 338 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 339 #endif
 340 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 341
 342 /* max number of sectors on one chip */
 343 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 344 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 345 #define CONFIG_SYS_MAX_FLASH_SECT       512
 346
 347 /* environments */
 348 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
 349 #define CONFIG_ENV_SIZE                 8192
 350 #define CONFIG_ENV_OVERWRITE
 351
 352 /*
 353  * For booting Linux, the board info and command line data
 354  * have to be in the first 16 MB of memory, since this is
 355  * the maximum mapped by the Linux kernel during initialization.
 356  */
 357
 358 /* Initial Memory map for Linux*/
 359 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 360 /* Increase max gunzip size */
 361 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 362
 363 #endif  /* __CONFIG_H */